Re: [PATCH 13/67] target/arm: Convert disas_add_sub_reg to decodetree

[Peter Maydell]

On Sun, 1 Dec 2024 at 15:15, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> This includes ADD, SUB, ADDS, SUBS (shifted register).
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


> diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
> index b4ccad34fb..4d422a7191 100644
> --- a/target/arm/tcg/a64.decode
> +++ b/target/arm/tcg/a64.decode
> @@ -718,7 +718,7 @@ XPACD           1 10 11010110 00001 010001 11111 rd:5
>  # Logical (shifted reg)
>
>  &logic_shift    rd rn rm sf sa st n
> -@logic_shift    sf:1 .. ..... st:2 n:1 rm:5 sa:6 rn:5 rd:5
> +@logic_shift    sf:1 .. ..... st:2 n:1 rm:5 sa:6 rn:5 rd:5  &logic_shift

I think this change needed to be in some previous patch.

>
>  AND_r           . 00 01010 .. . ..... ...... ..... .....  @logic_shift
>  ORR_r           . 01 01010 .. . ..... ...... ..... .....  @logic_shift
> @@ -726,6 +726,15 @@ EOR_r           . 10 01010 .. . ..... ...... ..... ..... 
>  @logic_shift
>  ANDS_r          . 11 01010 .. . ..... ...... ..... .....  @logic_shift
>
>  # Add/subtract (shifted reg)
> +
> +&addsub_shift    rd rn rm sf sa st
> +@addsub_shift    sf:1 .. ..... st:2 . rm:5 sa:6 rn:5 rd:5  &addsub_shift
> +
> +ADD_r           . 00 01011 .. 0 ..... ...... ..... .....  @addsub_shift
> +SUB_r           . 10 01011 .. 0 ..... ...... ..... .....  @addsub_shift
> +ADDS_r          . 01 01011 .. 0 ..... ...... ..... .....  @addsub_shift
> +SUBS_r          . 11 01011 .. 0 ..... ...... ..... .....  @addsub_shift
> +
>  # Add/subtract (extended reg)

Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM