[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v3 01/69] target/arm: Add section labels for "Data Processing (re
From: |
Richard Henderson |
Subject: |
[PATCH v3 01/69] target/arm: Add section labels for "Data Processing (register)" |
Date: |
Wed, 11 Dec 2024 10:29:28 -0600 |
At the same time, use ### to separate 3rd-level sections.
We already use ### for 4.1.92 Data Processing (immediate),
but not the two following two third-level sections:
4.1.93 Branches, and 4.1.94 Loads and stores.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/a64.decode | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 331a8e180c..d28efb884d 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -161,7 +161,7 @@ UBFM . 10 100110 . ...... ...... ..... .....
@bitfield_32
EXTR 1 00 100111 1 0 rm:5 imm:6 rn:5 rd:5 &extract sf=1
EXTR 0 00 100111 0 0 rm:5 0 imm:5 rn:5 rd:5 &extract sf=0
-# Branches
+### Branches
%imm26 0:s26 !function=times_4
@branch . ..... .......................... &i imm=%imm26
@@ -291,7 +291,7 @@ HLT 1101 0100 010 ................ 000 00 @i16
# DCPS2 1101 0100 101 ................ 000 10 @i16
# DCPS3 1101 0100 101 ................ 000 11 @i16
-# Loads and stores
+### Loads and stores
&stxr rn rt rt2 rs sz lasr
&stlr rn rt sz lasr
@@ -649,6 +649,21 @@ CPYP 00 011 1 01000 ..... .... 01 ..... .....
@cpy
CPYM 00 011 1 01010 ..... .... 01 ..... ..... @cpy
CPYE 00 011 1 01100 ..... .... 01 ..... ..... @cpy
+### Data Processing (register)
+
+# Data Processing (2-source)
+# Data Processing (1-source)
+# Logical (shifted reg)
+# Add/subtract (shifted reg)
+# Add/subtract (extended reg)
+# Add/subtract (carry)
+# Rotate right into flags
+# Evaluate into flags
+# Conditional compare (regster)
+# Conditional compare (immediate)
+# Conditional select
+# Data Processing (3-source)
+
### Cryptographic AES
AESE 01001110 00 10100 00100 10 ..... ..... @r2r_q1e0
--
2.43.0
- [PATCH v3 00/69] target/arm: AArch64 decodetree conversion, final part, Richard Henderson, 2024/12/11
- [PATCH v3 01/69] target/arm: Add section labels for "Data Processing (register)",
Richard Henderson <=
- [PATCH v3 03/69] target/arm: Convert LSLV, LSRV, ASRV, RORV to decodetree, Richard Henderson, 2024/12/11
- [PATCH v3 02/69] target/arm: Convert UDIV, SDIV to decodetree, Richard Henderson, 2024/12/11
- [PATCH v3 04/69] target/arm: Convert CRC32, CRC32C to decodetree, Richard Henderson, 2024/12/11
- [PATCH v3 05/69] target/arm: Convert SUBP, IRG, GMI to decodetree, Richard Henderson, 2024/12/11
- [PATCH v3 08/69] target/arm: Convert CLZ, CLS to decodetree, Richard Henderson, 2024/12/11
- [PATCH v3 07/69] target/arm: Convert RBIT, REV16, REV32, REV64 to decodetree, Richard Henderson, 2024/12/11
- [PATCH v3 09/69] target/arm: Convert PAC[ID]*, AUT[ID]* to decodetree, Richard Henderson, 2024/12/11
- [PATCH v3 06/69] target/arm: Convert PACGA to decodetree, Richard Henderson, 2024/12/11
- [PATCH v3 11/69] target/arm: Convert disas_logic_reg to decodetree, Richard Henderson, 2024/12/11
- [PATCH v3 13/69] target/arm: Convert disas_add_sub_reg to decodetree, Richard Henderson, 2024/12/11