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Re: [Qemu-block] [Qemu-devel] [PATCH v5 28/28] hw/block/pflash_cfi02: Re
From: |
Alistair Francis |
Subject: |
Re: [Qemu-block] [Qemu-devel] [PATCH v5 28/28] hw/block/pflash_cfi02: Reduce I/O accesses to 16-bit |
Date: |
Fri, 28 Jun 2019 16:13:57 -0700 |
On Thu, Jun 27, 2019 at 1:55 PM Philippe Mathieu-Daudé
<address@hidden> wrote:
>
> Parallel NOR flashes are limited to 16-bit bus accesses.
> Remove the 32-bit dead code.
>
> Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Alistair
> ---
> hw/block/pflash_cfi02.c | 5 +----
> 1 file changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c
> index db9dc7d8fb..d1f28b02b9 100644
> --- a/hw/block/pflash_cfi02.c
> +++ b/hw/block/pflash_cfi02.c
> @@ -317,8 +317,6 @@ static uint64_t pflash_read(void *opaque, hwaddr offset,
> unsigned int width)
> boff = offset & 0xFF;
> if (pfl->width == 2) {
> boff = boff >> 1;
> - } else if (pfl->width == 4) {
> - boff = boff >> 2;
> }
> switch (pfl->cmd) {
> default:
> @@ -449,8 +447,6 @@ static void pflash_write(void *opaque, hwaddr offset,
> uint64_t value,
> boff = offset;
> if (pfl->width == 2) {
> boff = boff >> 1;
> - } else if (pfl->width == 4) {
> - boff = boff >> 2;
> }
> /* Only the least-significant 11 bits are used in most cases. */
> boff &= 0x7FF;
> @@ -710,6 +706,7 @@ static void pflash_write(void *opaque, hwaddr offset,
> uint64_t value,
> static const MemoryRegionOps pflash_cfi02_ops = {
> .read = pflash_read,
> .write = pflash_write,
> + .impl.max_access_size = 2,
> .valid.min_access_size = 1,
> .valid.max_access_size = 4,
> .endianness = DEVICE_NATIVE_ENDIAN,
> --
> 2.20.1
>
>
- [Qemu-block] [PATCH v5 22/28] hw/block/pflash_cfi02: Fix reset command not ignored during erase, (continued)
- [Qemu-block] [PATCH v5 22/28] hw/block/pflash_cfi02: Fix reset command not ignored during erase, Philippe Mathieu-Daudé, 2019/06/27
- [Qemu-block] [PATCH v5 21/28] hw/block/pflash_cfi02: Fix CFI in autoselect mode, Philippe Mathieu-Daudé, 2019/06/27
- [Qemu-block] [PATCH v5 25/28] hw/block/pflash_cfi02: Use chip erase time specified in the CFI table, Philippe Mathieu-Daudé, 2019/06/27
- [Qemu-block] [PATCH v5 23/28] hw/block/pflash_cfi02: Implement multi-sector erase, Philippe Mathieu-Daudé, 2019/06/27
- [Qemu-block] [PATCH v5 24/28] hw/block/pflash_cfi02: Implement erase suspend/resume, Philippe Mathieu-Daudé, 2019/06/27
- [Qemu-block] [PATCH v5 26/28] hw/block/pflash_cfi02: Reduce single byte/word write delay, Philippe Mathieu-Daudé, 2019/06/27
- [Qemu-block] [PATCH v5 28/28] hw/block/pflash_cfi02: Reduce I/O accesses to 16-bit, Philippe Mathieu-Daudé, 2019/06/27
- Re: [Qemu-block] [Qemu-devel] [PATCH v5 28/28] hw/block/pflash_cfi02: Reduce I/O accesses to 16-bit,
Alistair Francis <=
- [Qemu-block] [PATCH v5 27/28] hw/block/pflash_cfi02: Document commands, Philippe Mathieu-Daudé, 2019/06/27