[Qemu-commits] [qemu/qemu] 5ca662: arm/translate-a64: mark path as unreachable to eli...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 5ca66278c859bb1ded243755aeead2be6992ce73
      
https://github.com/qemu/qemu/commit/5ca66278c859bb1ded243755aeead2be6992ce73
  Author: Emilio G. Cota <address@hidden>
  Date:   2017-11-13 (Mon, 13 Nov 2017)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  arm/translate-a64: mark path as unreachable to eliminate warning

Fixes the following warning when compiling with gcc 5.4.0 with -O1
optimizations and --enable-debug:

target/arm/translate-a64.c: In function ‘aarch64_tr_translate_insn’:
target/arm/translate-a64.c:2361:8: error: ‘post_index’ may be used 
uninitialized in this function [-Werror=maybe-uninitialized]
     if (!post_index) {
  ^
target/arm/translate-a64.c:2307:10: note: ‘post_index’ was declared here
     bool post_index;
    ^
target/arm/translate-a64.c:2386:8: error: ‘writeback’ may be used uninitialized 
in this function [-Werror=maybe-uninitialized]
     if (writeback) {
  ^
target/arm/translate-a64.c:2308:10: note: ‘writeback’ was declared here
     bool writeback;
    ^

Note that idx comes from selecting 2 bits, and therefore its value
can be at most 3.

Signed-off-by: Emilio G. Cota <address@hidden>
Acked-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c5c752af8cddad3e4e51acef40a46db998638144
      
https://github.com/qemu/qemu/commit/c5c752af8cddad3e4e51acef40a46db998638144
  Author: Prasad J Pandit <address@hidden>
  Date:   2017-11-13 (Mon, 13 Nov 2017)

  Changed paths:
    M hw/arm/highbank.c

  Log Message:
  -----------
  highbank: validate register offset before access

An 'offset' parameter sent to highbank register r/w functions
could be greater than number(NUM_REGS=0x200) of hb registers,
leading to an OOB access issue. Add check to avoid it.

Reported-by: Moguofang (Dennis mo) <address@hidden>
Signed-off-by: Prasad J Pandit <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 670bc4cbdab9a36a3df45667fbaea4d4cebda99f
      
https://github.com/qemu/qemu/commit/670bc4cbdab9a36a3df45667fbaea4d4cebda99f
  Author: Subbaraya Sundeep <address@hidden>
  Date:   2017-11-13 (Mon, 13 Nov 2017)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Add entries for Smartfusion2

Voluntarily add myself as maintainer for Smartfusion2

Signed-off-by: Subbaraya Sundeep <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2dda635410e95843562e5257a8f173e7115a7a1e
      
https://github.com/qemu/qemu/commit/2dda635410e95843562e5257a8f173e7115a7a1e
  Author: Emilio G. Cota <address@hidden>
  Date:   2017-11-13 (Mon, 13 Nov 2017)

  Changed paths:
    M exec.c
    M include/qom/cpu.h

  Log Message:
  -----------
  qom: move CPUClass.tcg_initialize to a global

55c3cee ("qom: Introduce CPUClass.tcg_initialize", 2017-10-24)
introduces a per-CPUClass bool that we check so that the target CPU
is initialized for TCG only once. This works well except when
we end up creating more than one CPUClass, in which case we end
up incorrectly initializing TCG more than once, i.e. once for
each CPUClass.

This can be replicated with:
  $ aarch64-softmmu/qemu-system-aarch64 -machine xlnx-zcu102 -smp 6 \
      -global driver=xlnx,,zynqmp,property=has_rpu,value=on
In this case the class name of the "RPUs" is prefixed by "cortex-r5-",
whereas the "regular" CPUs are prefixed by "cortex-a53-". This
results in two CPUClass instances being created.

Fix it by introducing a static variable, so that only the first
target CPU being initialized will initialize the target-dependent
part of TCG, regardless of CPUClass instances.

Fixes: 55c3ceef61fcf06fc98ddc752b7cce788ce7680b
Signed-off-by: Emilio G. Cota <address@hidden>
Reviewed-by: Eduardo Habkost <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Tested-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6908ec448b4d5fbf98c99a245b7176e39b460130
      
https://github.com/qemu/qemu/commit/6908ec448b4d5fbf98c99a245b7176e39b460130
  Author: Alistair Francis <address@hidden>
  Date:   2017-11-13 (Mon, 13 Nov 2017)

  Changed paths:
    M hw/arm/xlnx-zcu102.c
    M hw/arm/xlnx-zynqmp.c

  Log Message:
  -----------
  xlnx-zynqmp: Properly support the smp command line option

Allow the -smp command line option to control the number of CPUs we
create.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Eduardo Habkost <address@hidden>
Reviewed-by: Emilio G. Cota <address@hidden>
Tested-by: Emilio G. Cota <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 83926ad52789bc13d5b4bbd1fd3366e5bace9a3b
      
https://github.com/qemu/qemu/commit/83926ad52789bc13d5b4bbd1fd3366e5bace9a3b
  Author: Alistair Francis <address@hidden>
  Date:   2017-11-13 (Mon, 13 Nov 2017)

  Changed paths:
    M hw/arm/xlnx-zcu102.c
    M qemu-doc.texi

  Log Message:
  -----------
  xlnx-zcu102: Add an info message deprecating the EP108

The EP108 was an early access development board that is no longer used.
Add an info message to convert any users to the ZCU102 instead. On QEMU
they are both identical.

This patch also updated the qemu-doc.texi file to indicate that the
EP108 has been deprecated.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Emilio G. Cota <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1342b0355ed943ca4ad4e67e03390b69476b8a6b
      
https://github.com/qemu/qemu/commit/1342b0355ed943ca4ad4e67e03390b69476b8a6b
  Author: Emilio G. Cota <address@hidden>
  Date:   2017-11-13 (Mon, 13 Nov 2017)

  Changed paths:
    M hw/arm/xlnx-zcu102.c

  Log Message:
  -----------
  xlnx-zcu102: Specify the max number of CPUs for the EP108

Just like the zcu102, the ep108 can instantiate several CPUs.

Signed-off-by: Emilio G. Cota <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7264961934130df50d151def5eb415efa2e28ec5
      
https://github.com/qemu/qemu/commit/7264961934130df50d151def5eb415efa2e28ec5
  Author: Emilio G. Cota <address@hidden>
  Date:   2017-11-13 (Mon, 13 Nov 2017)

  Changed paths:
    M hw/arm/exynos4_boards.c
    M hw/arm/raspi.c
    M hw/arm/xlnx-zcu102.c
    M include/hw/boards.h
    M vl.c

  Log Message:
  -----------
  hw: add .min_cpus and .default_cpus fields to machine_class

max_cpus needs to be an upper bound on the number of vCPUs
initialized; otherwise TCG region initialization breaks.

Some boards initialize a hard-coded number of vCPUs, which is not
captured by the global max_cpus and therefore breaks TCG initialization.
Fix it by adding the .min_cpus field to machine_class.

This commit also changes some user-facing behaviour: we now die if
-smp is below this hard-coded vCPU minimum instead of silently
ignoring the passed -smp value (sometimes announcing this by printing
a warning). However, the introduction of .default_cpus lessens the
likelihood that users will notice this: if -smp isn't set, we now
assign the value in .default_cpus to both smp_cpus and max_cpus. IOW,
if a user does not set -smp, they always get a correct number of vCPUs.

This change fixes 3468b59 ("tcg: enable multiple TCG contexts in
softmmu", 2017-10-24), which broke TCG initialization for some
ARM boards.

Fixes: 3468b59e18b179bc63c7ce934de912dfa9596122
Reported-by: Thomas Huth <address@hidden>
Reviewed-by: Eduardo Habkost <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Emilio G. Cota <address@hidden>
Message-id: address@hidden
Suggested-by: Peter Maydell <address@hidden>
Signed-off-by: Emilio G. Cota <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d25f2a72272b9ffe0d06710d6217d1169bc2cc7d
      
https://github.com/qemu/qemu/commit/d25f2a72272b9ffe0d06710d6217d1169bc2cc7d
  Author: Alex Bennée <address@hidden>
  Date:   2017-11-13 (Mon, 13 Nov 2017)

  Changed paths:
    M accel/tcg/translate-all.c
    M include/exec/exec-all.h

  Log Message:
  -----------
  accel/tcg/translate-all: expand cpu_restore_state addr check

We are still seeing signals during translation time when we walk over
a page protection boundary. This expands the check to ensure the host
PC is inside the code generation buffer. The original suggestion was
to check versus tcg_ctx.code_gen_ptr but as we now segment the
translation buffer we have to settle for just a general check for
being inside.

I've also fixed up the declaration to make it clear it can deal with
invalid addresses. A later patch will fix up the call sites.

Signed-off-by: Alex Bennée <address@hidden>
Reported-by: Peter Maydell <address@hidden>
Reviewed-by: Laurent Vivier <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Suggested-by: Paolo Bonzini <address@hidden>
Cc: Richard Henderson <address@hidden>
Tested-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 55ed8d600abfd09de89393b3a6bd506793edd874
      
https://github.com/qemu/qemu/commit/55ed8d600abfd09de89393b3a6bd506793edd874
  Author: Peter Maydell <address@hidden>
  Date:   2017-11-14 (Tue, 14 Nov 2017)

  Changed paths:
    M MAINTAINERS
    M accel/tcg/translate-all.c
    M exec.c
    M hw/arm/exynos4_boards.c
    M hw/arm/highbank.c
    M hw/arm/raspi.c
    M hw/arm/xlnx-zcu102.c
    M hw/arm/xlnx-zynqmp.c
    M include/exec/exec-all.h
    M include/hw/boards.h
    M include/qom/cpu.h
    M qemu-doc.texi
    M target/arm/translate-a64.c
    M vl.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20171113' 
into staging

target-arm queue:
 * translate-a64.c: silence gcc5 warning
 * highbank: validate register offset before access
 * MAINTAINERS: Add entries for Smartfusion2
 * accel/tcg/translate-all: expand cpu_restore_state addr check
   (so usermode insn aborts don't crash with an assertion failure)
 * fix TCG initialization of some Arm boards by allowing them
   to specify min/default number of CPUs to create

# gpg: Signature made Mon 13 Nov 2017 14:11:09 GMT
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20171113:
  accel/tcg/translate-all: expand cpu_restore_state addr check
  hw: add .min_cpus and .default_cpus fields to machine_class
  xlnx-zcu102: Specify the max number of CPUs for the EP108
  xlnx-zcu102: Add an info message deprecating the EP108
  xlnx-zynqmp: Properly support the smp command line option
  qom: move CPUClass.tcg_initialize to a global
  MAINTAINERS: Add entries for Smartfusion2
  highbank: validate register offset before access
  arm/translate-a64: mark path as unreachable to eliminate warning

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/2e550e31518f...55ed8d600abf