[Qemu-commits] [qemu/qemu] 9eff78: ppc/pnv: fix PnvChip redefinition in <hw/ppc/pnv_x...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 9eff7830c4490a1394f232937c60adff944b34fd
      
https://github.com/qemu/qemu/commit/9eff7830c4490a1394f232937c60adff944b34fd
  Author: Cédric Le Goater <address@hidden>
  Date:   2018-01-27 (Sat, 27 Jan 2018)

  Changed paths:
    M include/hw/ppc/pnv_xscom.h

  Log Message:
  -----------
  ppc/pnv: fix PnvChip redefinition in <hw/ppc/pnv_xscom.h>

This redefinition generates warnings on some clang compilers and older
gcc4.4.

...include/hw/ppc/pnv_xscom.h:24:24: warning: redefinition of typedef 'PnvChip' 
is a C11
      feature [-Wtypedef-redefinition]
typedef struct PnvChip PnvChip;
                 ^
...include/hw/ppc/pnv.h:65:3: note: previous definition is here
} PnvChip;
  ^
1 warning generated.
  CC      ppc64-softmmu/hw/ppc/pnv_xscom.o

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 64b47457dacc92cf3f1a9a1af243cdec3951168c
      
https://github.com/qemu/qemu/commit/64b47457dacc92cf3f1a9a1af243cdec3951168c
  Author: address@hidden <address@hidden>
  Date:   2018-01-27 (Sat, 27 Jan 2018)

  Changed paths:
    M hw/ppc/ppc405_boards.c
    M hw/ppc/ppc440_bamboo.c
    M hw/ppc/virtex_ml507.c
    M qemu-doc.texi

  Log Message:
  -----------
  ppc: Deprecate qemu-system-ppcemb

qemu-system-ppcemb has been once split of qemu-system-ppc to support
CPU page sizes < 4096 for some of the embedded 4xx PowerPC CPUs.
However, there was hardly any OS available in the wild that really
used such small page sizes (Linux uses 4096 on PPC), so there is
no known recent use case for this separate build anymore. It's
rather cumbersome to maintain a separate set of config switches for
this, and it's wasting compile and test time of all the developers
who have to build all QEMU targets to verify that their changes did
not break anything.

Except for the small CPU page sizes, qemu-system-ppc can be used as
a full replacement for qemu-system-ppcemb since it contains all the
embedded 4xx PPC boards and CPUs, too. Thus let's start the deprecation
process for qemu-system-ppcemb to see whether somebody still needs
the small page sizes or whether we could finally remove this unloved
separate build.

Signed-off-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: b728fbbc27c7c9012c6459c7521b867664238ffd
      
https://github.com/qemu/qemu/commit/b728fbbc27c7c9012c6459c7521b867664238ffd
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-01-27 (Sat, 27 Jan 2018)

  Changed paths:
    M hw/pci-host/grackle.c
    M hw/pci-host/trace-events

  Log Message:
  -----------
  grackle: convert to trace-events

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 0b0c5e90be58196c513ab495675d608ac193216d
      
https://github.com/qemu/qemu/commit/0b0c5e90be58196c513ab495675d608ac193216d
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-01-27 (Sat, 27 Jan 2018)

  Changed paths:
    M hw/pci-host/trace-events
    M hw/pci-host/uninorth.c

  Log Message:
  -----------
  uninorth: convert to trace-events

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: d0fcf3bde4261c5c1f56ee628a1de6814847fdc0
      
https://github.com/qemu/qemu/commit/d0fcf3bde4261c5c1f56ee628a1de6814847fdc0
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-01-27 (Sat, 27 Jan 2018)

  Changed paths:
    M hw/input/trace-events

  Log Message:
  -----------
  input: add missing newline from trace-events

This was accidentally omitted from 77cb0f5aaf "Split adb.c into adb.c, 
adb-mouse.c
and adb-kbd.c".

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 9cbe305b60cc49cfcd134765b85c28be95b1b57d
      
https://github.com/qemu/qemu/commit/9cbe305b60cc49cfcd134765b85c28be95b1b57d
  Author: Greg Kurz <address@hidden>
  Date:   2018-01-29 (Mon, 29 Jan 2018)

  Changed paths:
    M hw/ppc/spapr_pci.c

  Log Message:
  -----------
  spapr_pci: fix MSI/MSIX selection

In various place we don't correctly check if the device supports MSI or
MSI-X. This can cause devices to be advertised with MSI support, even
if they only support MSI-X (like virtio-pci-* devices for example):
           address@hidden {
                  ibm,req#msi = <0x1>; <--- wrong!
                        .
                        ibm,loc-code = "qemu_virtio-net-pci:0000:00:00.0";
                        .
                        ibm,req#msi-x = <0x3>;
          };

Worse, this can also cause the "ibm,change-msi" RTAS call to corrupt the
PCI status and cause migration to fail:

  qemu-system-ppc64: get_pci_config_device: Bad config data: i=0x6
    read: 0 device: 10 cmask: 10 wmask: 0 w1cmask:0
                        ^^
     PCI_STATUS_CAP_LIST bit which is assumed to be constant

This patch changes spapr_populate_pci_child_dt() to properly check for
MSI support using msi_present(): this ensures that PCIDevice::msi_cap
was set by msi_init() and that msi_nr_vectors_allocated() will look at
the right place in the config space.

Checking PCIDevice::msix_entries_nr is enough for MSI-X but let's add
a call to msix_present() there as well for consistency.

It also changes rtas_ibm_change_msi() to select the appropriate MSI
type in Function 1 instead of always selecting plain MSI. This new
behaviour is compliant with LoPAPR 1.1, as described in "Table 71.
ibm,change-msi Argument Call Buffer":

  Function 1: If Number Outputs is equal to 3, request to set to a new
     number of MSIs (including set to 0).
     If the “ibm,change-msix-capable” property exists and Number
     Outputs is equal to 4, request is to set to a new number of
     MSI or MSI-X (platform choice) interrupts (including set to
     0).

Since MSI is the the platform default (LoPAPR 6.2.3 MSI Option), let's
check for MSI support first.

And finally, it checks the input parameters are valid, as described in
LoPAPR 1.1 "R1–7.3.10.5.1–3":

  For the MSI option: The platform must return a Status of -3 (Parameter
  error) from ibm,change-msi, with no change in interrupt assignments if
  the PCI configuration address does not support MSI and Function 3 was
  requested (that is, the “ibm,req#msi” property must exist for the PCI
  configuration address in order to use Function 3), or does not support
  MSI-X and Function 4 is requested (that is, the “ibm,req#msi-x” property
  must exist for the PCI configuration address in order to use Function 4),
  or if neither MSIs nor MSI-Xs are supported and Function 1 is requested.

This ensures that the ret_intr_type variable contains a valid MSI type
for this device, and that spapr_msi_setmsg() won't corrupt the PCI status.

Signed-off-by: Greg Kurz <address@hidden>
Reviewed-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 8acc2ae5e91681ceda3ff4cf946ebf163f6012e9
      
https://github.com/qemu/qemu/commit/8acc2ae5e91681ceda3ff4cf946ebf163f6012e9
  Author: Suraj Jitindar Singh <address@hidden>
  Date:   2018-01-29 (Mon, 29 Jan 2018)

  Changed paths:
    M include/hw/ppc/spapr.h
    M target/ppc/kvm.c
    M target/ppc/kvm_ppc.h

  Log Message:
  -----------
  target/ppc/kvm: Add cap_ppc_safe_[cache/bounds_check/indirect_branch]

Add three new kvm capabilities used to represent the level of host support
for three corresponding workarounds.

Host support for each of the capabilities is queried through the
new ioctl KVM_PPC_GET_CPU_CHAR which returns four uint64 quantities. The
first two, character and behaviour, represent the available
characteristics of the cpu and the behaviour of the cpu respectively.
The second two, c_mask and b_mask, represent the mask of known bits for
the character and beheviour dwords respectively.

Signed-off-by: Suraj Jitindar Singh <address@hidden>
Reviewed-by: David Gibson <address@hidden>
[dwg: Correct some compile errors due to name change in final kernel
 patch version]
Signed-off-by: David Gibson <address@hidden>


  Commit: 6898aed77f4636c3e77af9c12631f583f22cb5db
      
https://github.com/qemu/qemu/commit/6898aed77f4636c3e77af9c12631f583f22cb5db
  Author: Suraj Jitindar Singh <address@hidden>
  Date:   2018-01-29 (Mon, 29 Jan 2018)

  Changed paths:
    M hw/ppc/spapr_caps.c
    M include/hw/ppc/spapr.h

  Log Message:
  -----------
  target/ppc/spapr_caps: Add support for tristate spapr_capabilities

spapr_caps are used to represent the level of support for various
capabilities related to the spapr machine type. Currently there is
only support for boolean capabilities.

Add support for tristate capabilities by implementing their get/set
functions. These capabilities can have the values 0, 1 or 2
corresponding to broken, workaround and fixed.

Signed-off-by: Suraj Jitindar Singh <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 8f38eaf8f9dd194c9961cf76c675724930ce4570
      
https://github.com/qemu/qemu/commit/8f38eaf8f9dd194c9961cf76c675724930ce4570
  Author: Suraj Jitindar Singh <address@hidden>
  Date:   2018-01-29 (Mon, 29 Jan 2018)

  Changed paths:
    M hw/ppc/spapr.c
    M hw/ppc/spapr_caps.c
    M include/hw/ppc/spapr.h

  Log Message:
  -----------
  target/ppc/spapr_caps: Add new tristate cap safe_cache

Add new tristate cap cap-cfpc to represent the cache flush on privilege
change capability.

Signed-off-by: Suraj Jitindar Singh <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 09114fd8179977e4157b36aab2e3d68eaf08adca
      
https://github.com/qemu/qemu/commit/09114fd8179977e4157b36aab2e3d68eaf08adca
  Author: Suraj Jitindar Singh <address@hidden>
  Date:   2018-01-29 (Mon, 29 Jan 2018)

  Changed paths:
    M hw/ppc/spapr.c
    M hw/ppc/spapr_caps.c
    M include/hw/ppc/spapr.h

  Log Message:
  -----------
  target/ppc/spapr_caps: Add new tristate cap safe_bounds_check

Add new tristate cap cap-sbbc to represent the speculation barrier
bounds checking capability.

Signed-off-by: Suraj Jitindar Singh <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 4be8d4e7d935fc8919d61f53a0f0fb7230052bb3
      
https://github.com/qemu/qemu/commit/4be8d4e7d935fc8919d61f53a0f0fb7230052bb3
  Author: Suraj Jitindar Singh <address@hidden>
  Date:   2018-01-29 (Mon, 29 Jan 2018)

  Changed paths:
    M hw/ppc/spapr.c
    M hw/ppc/spapr_caps.c
    M include/hw/ppc/spapr.h

  Log Message:
  -----------
  target/ppc/spapr_caps: Add new tristate cap safe_indirect_branch

Add new tristate cap cap-ibs to represent the indirect branch
serialisation capability.

Signed-off-by: Suraj Jitindar Singh <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: c59704b254734182c3202e0c261589ea2ccf485e
      
https://github.com/qemu/qemu/commit/c59704b254734182c3202e0c261589ea2ccf485e
  Author: Suraj Jitindar Singh <address@hidden>
  Date:   2018-01-29 (Mon, 29 Jan 2018)

  Changed paths:
    M hw/ppc/spapr_hcall.c
    M include/hw/ppc/spapr.h

  Log Message:
  -----------
  target/ppc/spapr: Add H-Call H_GET_CPU_CHARACTERISTICS

The new H-Call H_GET_CPU_CHARACTERISTICS is used by the guest to query
behaviours and available characteristics of the cpu.

Implement the handler for this new H-Call which formulates its response
based on the setting of the spapr_caps cap-cfpc, cap-sbbc and cap-ibs.

Signed-off-by: Suraj Jitindar Singh <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: fccfcc6328d1986ce849183d37901a7cf59ed3ce
      
https://github.com/qemu/qemu/commit/fccfcc6328d1986ce849183d37901a7cf59ed3ce
  Author: Peter Maydell <address@hidden>
  Date:   2018-01-29 (Mon, 29 Jan 2018)

  Changed paths:
    M hw/input/trace-events
    M hw/pci-host/grackle.c
    M hw/pci-host/trace-events
    M hw/pci-host/uninorth.c
    M hw/ppc/ppc405_boards.c
    M hw/ppc/ppc440_bamboo.c
    M hw/ppc/spapr.c
    M hw/ppc/spapr_caps.c
    M hw/ppc/spapr_hcall.c
    M hw/ppc/spapr_pci.c
    M hw/ppc/virtex_ml507.c
    M include/hw/ppc/pnv_xscom.h
    M include/hw/ppc/spapr.h
    M qemu-doc.texi
    M target/ppc/kvm.c
    M target/ppc/kvm_ppc.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.12-20180129' 
into staging

ppc patch queue 2018-01-29

Here's another batch of patches for ppc, spapr and related things.
Higlights:

  * Implement (with a bunch of necessary infrastructure) a hypercall
    to let guests properly apply Spectre and Meltdown workarounds.
  * Convert a number of old devices to trace events
  * Fix some bugs

# gpg: Signature made Mon 29 Jan 2018 03:27:30 GMT
# gpg:                using RSA key 0x6C38CACA20D9B392
# gpg: Good signature from "David Gibson <address@hidden>"
# gpg:                 aka "David Gibson (Red Hat) <address@hidden>"
# gpg:                 aka "David Gibson (ozlabs.org) <address@hidden>"
# gpg:                 aka "David Gibson (kernel.org) <address@hidden>"
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-2.12-20180129:
  target/ppc/spapr: Add H-Call H_GET_CPU_CHARACTERISTICS
  target/ppc/spapr_caps: Add new tristate cap safe_indirect_branch
  target/ppc/spapr_caps: Add new tristate cap safe_bounds_check
  target/ppc/spapr_caps: Add new tristate cap safe_cache
  target/ppc/spapr_caps: Add support for tristate spapr_capabilities
  target/ppc/kvm: Add cap_ppc_safe_[cache/bounds_check/indirect_branch]
  spapr_pci: fix MSI/MSIX selection
  input: add missing newline from trace-events
  uninorth: convert to trace-events
  grackle: convert to trace-events
  ppc: Deprecate qemu-system-ppcemb
  ppc/pnv: fix PnvChip redefinition in <hw/ppc/pnv_xscom.h>

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/6233b4a8c2a3...fccfcc6328d1