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[Qemu-commits] [qemu/qemu] 4af6b6: hw/arm/virt: Introduce virt_set_high_
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 4af6b6: hw/arm/virt: Introduce virt_set_high_memmap() helper |
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Date: |
Thu, 15 Dec 2022 13:39:42 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 4af6b6edece5ef273d29972d53547f823d2bc1c0
https://github.com/qemu/qemu/commit/4af6b6edece5ef273d29972d53547f823d2bc1c0
Author: Gavin Shan <gshan@redhat.com>
Date: 2022-12-15 (Thu, 15 Dec 2022)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Introduce virt_set_high_memmap() helper
This introduces virt_set_high_memmap() helper. The logic of high
memory region address assignment is moved to the helper. The intention
is to make the subsequent optimization for high memory region address
assignment easier.
No functional change intended.
Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Tested-by: Zhenyu Zhang <zhenyzha@redhat.com>
Message-id: 20221029224307.138822-2-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 370bea9d1c78796eec235ed6cb4310f489931a62
https://github.com/qemu/qemu/commit/370bea9d1c78796eec235ed6cb4310f489931a62
Author: Gavin Shan <gshan@redhat.com>
Date: 2022-12-15 (Thu, 15 Dec 2022)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Rename variable size to region_size in virt_set_high_memmap()
This renames variable 'size' to 'region_size' in virt_set_high_memmap().
Its counterpart ('region_base') will be introduced in next patch.
No functional change intended.
Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Tested-by: Zhenyu Zhang <zhenyzha@redhat.com>
Message-id: 20221029224307.138822-3-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: fa245799b9407fc7b561da185b3d889df5e16a88
https://github.com/qemu/qemu/commit/fa245799b9407fc7b561da185b3d889df5e16a88
Author: Gavin Shan <gshan@redhat.com>
Date: 2022-12-15 (Thu, 15 Dec 2022)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Introduce variable region_base in virt_set_high_memmap()
This introduces variable 'region_base' for the base address of the
specific high memory region. It's the preparatory work to optimize
high memory region address assignment.
No functional change intended.
Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Tested-by: Zhenyu Zhang <zhenyzha@redhat.com>
Message-id: 20221029224307.138822-4-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a5cb1350b19a5c2a58ab4edddf609ed429c13085
https://github.com/qemu/qemu/commit/a5cb1350b19a5c2a58ab4edddf609ed429c13085
Author: Gavin Shan <gshan@redhat.com>
Date: 2022-12-15 (Thu, 15 Dec 2022)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Introduce virt_get_high_memmap_enabled() helper
This introduces virt_get_high_memmap_enabled() helper, which returns
the pointer to vms->highmem_{redists, ecam, mmio}. The pointer will
be used in the subsequent patches.
No functional change intended.
Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Tested-by: Zhenyu Zhang <zhenyzha@redhat.com>
Message-id: 20221029224307.138822-5-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4a4ff9edc6a8fdc76082af5b41b059217138c09b
https://github.com/qemu/qemu/commit/4a4ff9edc6a8fdc76082af5b41b059217138c09b
Author: Gavin Shan <gshan@redhat.com>
Date: 2022-12-15 (Thu, 15 Dec 2022)
Changed paths:
M hw/arm/virt.c
M include/hw/arm/virt.h
Log Message:
-----------
hw/arm/virt: Improve high memory region address assignment
There are three high memory regions, which are VIRT_HIGH_REDIST2,
VIRT_HIGH_PCIE_ECAM and VIRT_HIGH_PCIE_MMIO. Their base addresses
are floating on highest RAM address. However, they can be disabled
in several cases.
(1) One specific high memory region is likely to be disabled by
code by toggling vms->highmem_{redists, ecam, mmio}.
(2) VIRT_HIGH_PCIE_ECAM region is disabled on machine, which is
'virt-2.12' or ealier than it.
(3) VIRT_HIGH_PCIE_ECAM region is disabled when firmware is loaded
on 32-bits system.
(4) One specific high memory region is disabled when it breaks the
PA space limit.
The current implementation of virt_set_{memmap, high_memmap}() isn't
optimized because the high memory region's PA space is always reserved,
regardless of whatever the actual state in the corresponding
vms->highmem_{redists, ecam, mmio} flag. In the code, 'base' and
'vms->highest_gpa' are always increased for case (1), (2) and (3).
It's unnecessary since the assigned PA space for the disabled high
memory region won't be used afterwards.
Improve the address assignment for those three high memory region by
skipping the address assignment for one specific high memory region if
it has been disabled in case (1), (2) and (3). The memory layout may
be changed after the improvement is applied, which leads to potential
migration breakage. So 'vms->highmem_compact' is added to control if
the improvement should be applied. For now, 'vms->highmem_compact' is
set to false, meaning that we don't have memory layout change until it
becomes configurable through property 'compact-highmem' in next patch.
Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Tested-by: Zhenyu Zhang <zhenyzha@redhat.com>
Message-id: 20221029224307.138822-6-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f40408a9fe5d1db70a75a33d2b26c8af8a5d57b0
https://github.com/qemu/qemu/commit/f40408a9fe5d1db70a75a33d2b26c8af8a5d57b0
Author: Gavin Shan <gshan@redhat.com>
Date: 2022-12-15 (Thu, 15 Dec 2022)
Changed paths:
M docs/system/arm/virt.rst
M hw/arm/virt.c
M include/hw/arm/virt.h
Log Message:
-----------
hw/arm/virt: Add 'compact-highmem' property
After the improvement to high memory region address assignment is
applied, the memory layout can be changed, introducing possible
migration breakage. For example, VIRT_HIGH_PCIE_MMIO memory region
is disabled or enabled when the optimization is applied or not, with
the following configuration. The configuration is only achievable by
modifying the source code until more properties are added to allow
users selectively disable those high memory regions.
pa_bits = 40;
vms->highmem_redists = false;
vms->highmem_ecam = false;
vms->highmem_mmio = true;
# qemu-system-aarch64 -accel kvm -cpu host \
-machine virt-7.2,compact-highmem={on, off} \
-m 4G,maxmem=511G -monitor stdio
Region compact-highmem=off compact-highmem=on
----------------------------------------------------------------
MEM [1GB 512GB] [1GB 512GB]
HIGH_GIC_REDISTS2 [512GB 512GB+64MB] [disabled]
HIGH_PCIE_ECAM [512GB+256MB 512GB+512MB] [disabled]
HIGH_PCIE_MMIO [disabled] [512GB 1TB]
In order to keep backwords compatibility, we need to disable the
optimization on machine, which is virt-7.1 or ealier than it. It
means the optimization is enabled by default from virt-7.2. Besides,
'compact-highmem' property is added so that the optimization can be
explicitly enabled or disabled on all machine types by users.
Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Tested-by: Zhenyu Zhang <zhenyzha@redhat.com>
Message-id: 20221029224307.138822-7-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 6a48c64eec355ab1aff694eb4522d07a8e461368
https://github.com/qemu/qemu/commit/6a48c64eec355ab1aff694eb4522d07a8e461368
Author: Gavin Shan <gshan@redhat.com>
Date: 2022-12-15 (Thu, 15 Dec 2022)
Changed paths:
M docs/system/arm/virt.rst
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Add properties to disable high memory regions
The 3 high memory regions are usually enabled by default, but they may
be not used. For example, VIRT_HIGH_GIC_REDIST2 isn't needed by GICv2.
This leads to waste in the PA space.
Add properties ("highmem-redists", "highmem-ecam", "highmem-mmio") to
allow users selectively disable them if needed. After that, the high
memory region for GICv3 or GICv4 redistributor can be disabled by user,
the number of maximal supported CPUs needs to be calculated based on
'vms->highmem_redists'. The follow-up error message is also improved
to indicate if the high memory region for GICv3 and GICv4 has been
enabled or not.
Suggested-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20221029224307.138822-8-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0a0044b181dbf0cd9920910559a891dc56e4faed
https://github.com/qemu/qemu/commit/0a0044b181dbf0cd9920910559a891dc56e4faed
Author: Mihai Carabas <mihai.carabas@oracle.com>
Date: 2022-12-15 (Thu, 15 Dec 2022)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: build SMBIOS 19 table
Use the base_memmap to build the SMBIOS 19 table which provides the address
mapping for a Physical Memory Array (from spec [1] chapter 7.20).
This was present on i386 from commit c97294ec1b9e36887e119589d456557d72ab37b5
("SMBIOS: Build aggregate smbios tables and entry point").
[1]
https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.5.0.pdf
The absence of this table is a breach of the specs and is
detected by the FirmwareTestSuite (FWTS), but it doesn't
cause any known problems for guest OSes.
Signed-off-by: Mihai Carabas <mihai.carabas@oracle.com>
Message-id: 1668789029-5432-1-git-send-email-mihai.carabas@oracle.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 94bc3b067ea2a57771a4621394c1ca362b605d81
https://github.com/qemu/qemu/commit/94bc3b067ea2a57771a4621394c1ca362b605d81
Author: Timofey Kutergin <tkutergin@gmail.com>
Date: 2022-12-15 (Thu, 15 Dec 2022)
Changed paths:
M docs/system/arm/virt.rst
M hw/arm/virt.c
M target/arm/cpu64.c
Log Message:
-----------
target/arm: Add Cortex-A55 CPU
The Cortex-A55 is one of the newer armv8.2+ CPUs; in particular
it supports the Privileged Access Never (PAN) feature. Add
a model of this CPU, so you can use a CPU type on the virt
board that models a specific real hardware CPU, rather than
having to use the QEMU-specific "max" CPU type.
Signed-off-by: Timofey Kutergin <tkutergin@gmail.com>
Message-id: 20221121150819.2782817-1-tkutergin@gmail.com
[PMM: tweaked commit message]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 58dff8f7ea7aadbfacf4416c4988ad7f0f88a4c8
https://github.com/qemu/qemu/commit/58dff8f7ea7aadbfacf4416c4988ad7f0f88a4c8
Author: Luke Starrett <lukes@xsightlabs.com>
Date: 2022-12-15 (Thu, 15 Dec 2022)
Changed paths:
M hw/intc/arm_gicv3_dist.c
Log Message:
-----------
hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement
The ARM GICv3 TRM describes that the ITLinesNumber field of GICD_TYPER
register:
"indicates the maximum SPI INTID that the GIC implementation supports"
As SPI #0 is absolute IRQ #32, the max SPI INTID should have accounted
for the internal 16x SGI's and 16x PPI's. However, the original GICv3
model subtracted off the SGI/PPI. Cosmetically this can be seen at OS
boot (Linux) showing 32 shy of what should be there, i.e.:
[ 0.000000] GICv3: 224 SPIs implemented
Though in hw/arm/virt.c, the machine is configured for 256 SPI's. ARM
virt machine likely doesn't have a problem with this because the upper
32 IRQ's don't actually have anything meaningful wired. But, this does
become a functional issue on a custom use case which wants to make use
of these IRQ's. Additionally, boot code (i.e. TF-A) will only init up
to the number (blocks of 32) that it believes to actually be there.
Signed-off-by: Luke Starrett <lukes@xsightlabs.com>
Message-id:
AM9P193MB168473D99B761E204E032095D40D9@AM9P193MB1684.EURP193.PROD.OUTLOOK.COM
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d2fd931362a693d988e3204ddc8068875dcf8fab
https://github.com/qemu/qemu/commit/d2fd931362a693d988e3204ddc8068875dcf8fab
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-12-15 (Thu, 15 Dec 2022)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Allow relevant HCR bits to be written for FEAT_EVT
FEAT_EVT adds five new bits to the HCR_EL2 register: TTLBIS, TTLBOS,
TICAB, TOCU and TID4. These allow the guest to enable trapping of
various EL1 instructions to EL2. In this commit, add the necessary
code to allow the guest to set these bits if the feature is present;
because the bit is always zero when the feature isn't present we
won't need to use explicit feature checks in the "trap on condition"
tests in the following commits.
Note that although full implementation of the feature (mandatory from
Armv8.5 onward) requires all five trap bits, the ID registers permit
a value indicating that only TICAB, TOCU and TID4 are implemented,
which might be the case for CPUs between Armv8.2 and Armv8.5.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 0f66d223e3b688a93ae02dc114d2891bbb0e09cc
https://github.com/qemu/qemu/commit/0f66d223e3b688a93ae02dc114d2891bbb0e09cc
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-12-15 (Thu, 15 Dec 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Implement HCR_EL2.TTLBIS traps
For FEAT_EVT, the HCR_EL2.TTLBIS bit allows trapping on EL1 use of
TLB maintenance instructions that operate on the inner shareable
domain:
AArch64:
TLBI VMALLE1IS, TLBI VAE1IS, TLBI ASIDE1IS, TLBI VAAE1IS,
TLBI VALE1IS, TLBI VAALE1IS, TLBI RVAE1IS, TLBI RVAAE1IS,
TLBI RVALE1IS, and TLBI RVAALE1IS.
AArch32:
TLBIALLIS, TLBIMVAIS, TLBIASIDIS, TLBIMVAAIS, TLBIMVALIS,
and TLBIMVAALIS.
Add the trapping support.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: fe3ca86c465428f738520de304e7a7a59bd0a6c2
https://github.com/qemu/qemu/commit/fe3ca86c465428f738520de304e7a7a59bd0a6c2
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-12-15 (Thu, 15 Dec 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Implement HCR_EL2.TTLBOS traps
For FEAT_EVT, the HCR_EL2.TTLBOS bit allows trapping on EL1
use of TLB maintenance instructions that operate on the
outer shareable domain:
TLBI VMALLE1OS, TLBI VAE1OS, TLBI ASIDE1OS,TLBI VAAE1OS,
TLBI VALE1OS, TLBI VAALE1OS, TLBI RVAE1OS, TLBI RVAAE1OS,
TLBI RVALE1OS, and TLBI RVAALE1OS.
(There are no AArch32 outer-shareable TLB maintenance ops.)
Implement the trapping.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 2d3ce4c6f3bc66234e384355cedc6e7aa40903ac
https://github.com/qemu/qemu/commit/2d3ce4c6f3bc66234e384355cedc6e7aa40903ac
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-12-15 (Thu, 15 Dec 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Implement HCR_EL2.TICAB,TOCU traps
For FEAT_EVT, the HCR_EL2.TICAB bit allows trapping of the ICIALLUIS
and IC IALLUIS cache maintenance instructions.
The HCR_EL2.TOCU bit traps all the other cache maintenance
instructions that operate to the point of unification:
AArch64 IC IVAU, IC IALLU, DC CVAU
AArch32 ICIMVAU, ICIALLU, DCCMVAU
The two trap bits between them cover all of the cache maintenance
instructions which must also check the HCR_TPU flag. Turn the old
aa64_cacheop_pou_access() function into a helper function which takes
the set of HCR_EL2 flags to check as an argument, and call it from
new access_ticab() and access_tocu() functions as appropriate for
each cache op.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: e2ce5fcde468c7316b6ba3c30a970c9e50bf7211
https://github.com/qemu/qemu/commit/e2ce5fcde468c7316b6ba3c30a970c9e50bf7211
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-12-15 (Thu, 15 Dec 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Implement HCR_EL2.TID4 traps
For FEAT_EVT, the HCR_EL2.TID4 trap allows trapping of the cache ID
registers CCSIDR_EL1, CCSIDR2_EL1, CLIDR_EL1 and CSSELR_EL1 (and
their AArch32 equivalents). This is a subset of the registers
trapped by HCR_EL2.TID2, which includes all of these and also the
CTR_EL0 register.
Our implementation already uses a separate access function for
CTR_EL0 (ctr_el0_access()), so all of the registers currently using
access_aa64_tid2() should also be checking TID4. Make that function
check both TID2 and TID4, and rename it appropriately.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 41654f120f535545baf91198699392376d995837
https://github.com/qemu/qemu/commit/41654f120f535545baf91198699392376d995837
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-12-15 (Thu, 15 Dec 2022)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/cpu64.c
M target/arm/cpu_tcg.c
Log Message:
-----------
target/arm: Report FEAT_EVT for TCG '-cpu max'
Update the ID registers for TCG's '-cpu max' to report the
FEAT_EVT Enhanced Virtualization Traps support.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 3c1a7c41972f92aa24cdb43e241f60e1d332bd26
https://github.com/qemu/qemu/commit/3c1a7c41972f92aa24cdb43e241f60e1d332bd26
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-12-15 (Thu, 15 Dec 2022)
Changed paths:
M hw/arm/smmu-common.c
Log Message:
-----------
hw/arm: Convert TYPE_ARM_SMMU to 3-phase reset
Convert the TYPE_ARM_SMMU device to 3-phase reset. The legacy method
doesn't do anything that's invalid in the hold phase, so the
conversion is simple and not a behaviour change.
Note that we must convert this base class before we can convert the
TYPE_ARM_SMMUV3 subclass -- transitional support in Resettable
handles "chain to parent class reset" when the base class is 3-phase
and the subclass is still using legacy reset, but not the other way
around.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20221109161444.3397405-2-peter.maydell@linaro.org
Commit: 503819a3479218f10fedbbae55686f719e47e04d
https://github.com/qemu/qemu/commit/503819a3479218f10fedbbae55686f719e47e04d
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-12-15 (Thu, 15 Dec 2022)
Changed paths:
M hw/arm/smmuv3.c
M include/hw/arm/smmuv3.h
Log Message:
-----------
hw/arm: Convert TYPE_ARM_SMMUV3 to 3-phase reset
Convert the TYPE_ARM_SMMUV3 device to 3-phase reset. The legacy
reset method doesn't do anything that's invalid in the hold phase, so
the conversion only requires changing it to a hold phase method, and
using the 3-phase versions of the "save the parent reset method and
chain to it" code.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20221109161444.3397405-3-peter.maydell@linaro.org
Commit: fe3c6174f24205db82ff19f5cb5d374e79394233
https://github.com/qemu/qemu/commit/fe3c6174f24205db82ff19f5cb5d374e79394233
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-12-15 (Thu, 15 Dec 2022)
Changed paths:
M hw/intc/arm_gic_common.c
Log Message:
-----------
hw/intc: Convert TYPE_ARM_GIC_COMMON to 3-phase reset
Convert the TYPE_ARM_GIC_COMMON device to 3-phase reset. This is a
simple no-behaviour-change conversion.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221109161444.3397405-4-peter.maydell@linaro.org
Commit: d39270b559e7f08f768e62b9a60d478be79eb03d
https://github.com/qemu/qemu/commit/d39270b559e7f08f768e62b9a60d478be79eb03d
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-12-15 (Thu, 15 Dec 2022)
Changed paths:
M hw/intc/arm_gic_kvm.c
Log Message:
-----------
hw/intc: Convert TYPE_ARM_GIC_KVM to 3-phase reset
Now we have converted TYPE_ARM_GIC_COMMON, we can convert the
TYPE_ARM_GIC_KVM subclass to 3-phase reset.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20221109161444.3397405-5-peter.maydell@linaro.org
Commit: 183cac319e783bc6b7fa57904d67d28b0500c855
https://github.com/qemu/qemu/commit/183cac319e783bc6b7fa57904d67d28b0500c855
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-12-15 (Thu, 15 Dec 2022)
Changed paths:
M hw/intc/arm_gicv3_common.c
Log Message:
-----------
hw/intc: Convert TYPE_ARM_GICV3_COMMON to 3-phase reset
Convert the TYPE_ARM_GICV3_COMMON parent class to 3-phase reset.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20221109161444.3397405-6-peter.maydell@linaro.org
Commit: 823300f0fc7d374a887a4bc65f340688738de71c
https://github.com/qemu/qemu/commit/823300f0fc7d374a887a4bc65f340688738de71c
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-12-15 (Thu, 15 Dec 2022)
Changed paths:
M hw/intc/arm_gicv3_kvm.c
Log Message:
-----------
hw/intc: Convert TYPE_KVM_ARM_GICV3 to 3-phase reset
Convert the TYPE_KVM_ARM_GICV3 device to 3-phase reset.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20221109161444.3397405-7-peter.maydell@linaro.org
Commit: 1f6887616f3ca60d8d1e4e33d0a423142afded12
https://github.com/qemu/qemu/commit/1f6887616f3ca60d8d1e4e33d0a423142afded12
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-12-15 (Thu, 15 Dec 2022)
Changed paths:
M hw/intc/arm_gicv3_its_common.c
Log Message:
-----------
hw/intc: Convert TYPE_ARM_GICV3_ITS_COMMON to 3-phase reset
Convert the TYPE_ARM_GICV3_ITS_COMMON parent class to 3-phase reset.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221109161444.3397405-8-peter.maydell@linaro.org
Commit: 1bcb90762b19c96ce1193524f1c8c97ba87e1b17
https://github.com/qemu/qemu/commit/1bcb90762b19c96ce1193524f1c8c97ba87e1b17
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-12-15 (Thu, 15 Dec 2022)
Changed paths:
M hw/intc/arm_gicv3_its.c
Log Message:
-----------
hw/intc: Convert TYPE_ARM_GICV3_ITS to 3-phase reset
Convert the TYPE_ARM_GICV3_ITS device to 3-phase reset.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20221109161444.3397405-9-peter.maydell@linaro.org
Commit: 227b5866c05168ea3539baa1fe60d5d5d67a6f5f
https://github.com/qemu/qemu/commit/227b5866c05168ea3539baa1fe60d5d5d67a6f5f
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-12-15 (Thu, 15 Dec 2022)
Changed paths:
M hw/intc/arm_gicv3_its_kvm.c
Log Message:
-----------
hw/intc: Convert TYPE_KVM_ARM_ITS to 3-phase reset
Convert the TYPE_KVM_ARM_ITS device to 3-phase reset.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20221109161444.3397405-10-peter.maydell@linaro.org
Commit: 990f49cfd700ff72933949769276dfa5a74ce36e
https://github.com/qemu/qemu/commit/990f49cfd700ff72933949769276dfa5a74ce36e
Author: Schspa Shi <schspa@gmail.com>
Date: 2022-12-15 (Thu, 15 Dec 2022)
Changed paths:
M hw/arm/boot.c
Log Message:
-----------
hw/arm/boot: set initrd with #address-cells type in fdt
We use 32bit value for linux,initrd-[start/end], when we have
loader_start > 4GB, there will be a wrong initrd_start passed
to the kernel, and the kernel will report the following warning.
[ 0.000000] ------------[ cut here ]------------
[ 0.000000] initrd not fully accessible via the linear mapping -- please
check your bootloader ...
[ 0.000000] WARNING: CPU: 0 PID: 0 at arch/arm64/mm/init.c:355
arm64_memblock_init+0x158/0x244
[ 0.000000] Modules linked in:
[ 0.000000] CPU: 0 PID: 0 Comm: swapper Tainted: G W
6.1.0-rc3-13250-g30a0b95b1335-dirty #28
[ 0.000000] Hardware name: Horizon Sigi Virtual development board (DT)
[ 0.000000] pstate: 600000c5 (nZCv daIF -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[ 0.000000] pc : arm64_memblock_init+0x158/0x244
[ 0.000000] lr : arm64_memblock_init+0x158/0x244
[ 0.000000] sp : ffff800009273df0
[ 0.000000] x29: ffff800009273df0 x28: 0000001000cc0010 x27: 0000800000000000
[ 0.000000] x26: 000000000050a3e2 x25: ffff800008b46000 x24: ffff800008b46000
[ 0.000000] x23: ffff800008a53000 x22: ffff800009420000 x21: ffff800008a53000
[ 0.000000] x20: 0000000004000000 x19: 0000000004000000 x18: 00000000ffff1020
[ 0.000000] x17: 6568632065736165 x16: 6c70202d2d20676e x15: 697070616d207261
[ 0.000000] x14: 656e696c20656874 x13: 0a2e2e2e20726564 x12: 0000000000000000
[ 0.000000] x11: 0000000000000000 x10: 00000000ffffffff x9 : 0000000000000000
[ 0.000000] x8 : 0000000000000000 x7 : 796c6c756620746f x6 : 6e20647274696e69
[ 0.000000] x5 : ffff8000093c7c47 x4 : ffff800008a2102f x3 : ffff800009273a88
[ 0.000000] x2 : 80000000fffff038 x1 : 00000000000000c0 x0 : 0000000000000056
[ 0.000000] Call trace:
[ 0.000000] arm64_memblock_init+0x158/0x244
[ 0.000000] setup_arch+0x164/0x1cc
[ 0.000000] start_kernel+0x94/0x4ac
[ 0.000000] __primary_switched+0xb4/0xbc
[ 0.000000] ---[ end trace 0000000000000000 ]---
[ 0.000000] Zone ranges:
[ 0.000000] DMA [mem 0x0000001000000000-0x0000001007ffffff]
This doesn't affect any machine types we currently support, because
for all of our machine types the RAM starts well below the 4GB
mark, but it does demonstrate that we're not currently writing
the device-tree properties quite as intended.
To fix it, we can change it to write these values to the dtb using a
type width matching #address-cells. This is the intended size for
these dtb properties, and is how u-boot, for instance, writes them,
although in practice the Linux kernel will cope with them being any
width as long as they're big enough to fit the value.
Signed-off-by: Schspa Shi <schspa@gmail.com>
Message-id: 20221129160724.75667-1-schspa@gmail.com
[PMM: tweaked commit message]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3d81e8cf0c81b8b63d7d7056c450dd94bfbfd038
https://github.com/qemu/qemu/commit/3d81e8cf0c81b8b63d7d7056c450dd94bfbfd038
Author: Thomas Huth <thuth@redhat.com>
Date: 2022-12-15 (Thu, 15 Dec 2022)
Changed paths:
M hw/misc/imx6_src.c
M hw/misc/iotkit-sysctl.c
M hw/misc/meson.build
M include/hw/misc/xlnx-zynqmp-apu-ctrl.h
M target/arm/kvm-consts.h
Log Message:
-----------
hw/misc: Move some arm-related files from specific_ss into softmmu_ss
The header target/arm/kvm-consts.h checks CONFIG_KVM which is marked as
poisoned in common code, so the files that include this header have to
be added to specific_ss and recompiled for each, qemu-system-arm and
qemu-system-aarch64. However, since the kvm headers are only optionally
used in kvm-constants.h for some sanity checks, we can additionally
check the NEED_CPU_H macro first to avoid the poisoned CONFIG_KVM macro,
so kvm-constants.h can also be used from "common" files (without the
sanity checks - which should be OK since they are still done from other
target-specific files instead). This way, and by adjusting some other
include statements in the related files here and there, we can move some
files from specific_ss into softmmu_ss, so that they only need to be
compiled once during the build process.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20221202154023.293614-1-thuth@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9e406eea309bbe44c7fb17f6af112d2b756854ad
https://github.com/qemu/qemu/commit/9e406eea309bbe44c7fb17f6af112d2b756854ad
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2022-12-15 (Thu, 15 Dec 2022)
Changed paths:
M target/arm/cpu.c
Log Message:
-----------
target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator
When building with --disable-tcg on Darwin we get:
target/arm/cpu.c:725:16: error: incomplete definition of type 'struct
TCGCPUOps'
cc->tcg_ops->do_interrupt(cs);
~~~~~~~~~~~^
Commit 083afd18a9 ("target/arm: Restrict cpu_exec_interrupt()
handler to sysemu") limited this block to system emulation,
but neglected to also limit it to TCG.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Message-id: 20221209110823.59495-1-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 29dc49f0310ad4439424eeaf179de46d15bd2d6b
https://github.com/qemu/qemu/commit/29dc49f0310ad4439424eeaf179de46d15bd2d6b
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-12-15 (Thu, 15 Dec 2022)
Changed paths:
M docs/system/arm/emulation.rst
M docs/system/arm/virt.rst
M hw/arm/boot.c
M hw/arm/smmu-common.c
M hw/arm/smmuv3.c
M hw/arm/virt.c
M hw/intc/arm_gic_common.c
M hw/intc/arm_gic_kvm.c
M hw/intc/arm_gicv3_common.c
M hw/intc/arm_gicv3_dist.c
M hw/intc/arm_gicv3_its.c
M hw/intc/arm_gicv3_its_common.c
M hw/intc/arm_gicv3_its_kvm.c
M hw/intc/arm_gicv3_kvm.c
M hw/misc/imx6_src.c
M hw/misc/iotkit-sysctl.c
M hw/misc/meson.build
M include/hw/arm/smmuv3.h
M include/hw/arm/virt.h
M include/hw/misc/xlnx-zynqmp-apu-ctrl.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/cpu_tcg.c
M target/arm/helper.c
M target/arm/kvm-consts.h
Log Message:
-----------
Merge tag 'pull-target-arm-20221215-1' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* hw/arm/virt: Add properties to allow more granular
configuration of use of highmem space
* target/arm: Add Cortex-A55 CPU
* hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement
* Implement FEAT_EVT
* Some 3-phase-reset conversions for Arm GIC, SMMU
* hw/arm/boot: set initrd with #address-cells type in fdt
* hw/misc: Move some arm-related files from specific_ss into softmmu_ss
* Restrict arm_cpu_exec_interrupt() to TCG accelerator
# gpg: Signature made Thu 15 Dec 2022 17:38:36 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[ultimate]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20221215-1' of
https://git.linaro.org/people/pmaydell/qemu-arm: (28 commits)
target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator
hw/misc: Move some arm-related files from specific_ss into softmmu_ss
hw/arm/boot: set initrd with #address-cells type in fdt
hw/intc: Convert TYPE_KVM_ARM_ITS to 3-phase reset
hw/intc: Convert TYPE_ARM_GICV3_ITS to 3-phase reset
hw/intc: Convert TYPE_ARM_GICV3_ITS_COMMON to 3-phase reset
hw/intc: Convert TYPE_KVM_ARM_GICV3 to 3-phase reset
hw/intc: Convert TYPE_ARM_GICV3_COMMON to 3-phase reset
hw/intc: Convert TYPE_ARM_GIC_KVM to 3-phase reset
hw/intc: Convert TYPE_ARM_GIC_COMMON to 3-phase reset
hw/arm: Convert TYPE_ARM_SMMUV3 to 3-phase reset
hw/arm: Convert TYPE_ARM_SMMU to 3-phase reset
target/arm: Report FEAT_EVT for TCG '-cpu max'
target/arm: Implement HCR_EL2.TID4 traps
target/arm: Implement HCR_EL2.TICAB,TOCU traps
target/arm: Implement HCR_EL2.TTLBOS traps
target/arm: Implement HCR_EL2.TTLBIS traps
target/arm: Allow relevant HCR bits to be written for FEAT_EVT
hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement
target/arm: Add Cortex-A55 CPU
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/928eac953918...29dc49f0310a