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[Qemu-commits] [qemu/qemu] d721cc: tcg/mips: Move TCG_AREG0 to S8
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] d721cc: tcg/mips: Move TCG_AREG0 to S8 |
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Date: |
Thu, 25 May 2023 12:32:39 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: d721cc94b25a100980c767beca9daae6c2cac6b0
https://github.com/qemu/qemu/commit/d721cc94b25a100980c767beca9daae6c2cac6b0
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-25 (Thu, 25 May 2023)
Changed paths:
M tcg/mips/tcg-target.c.inc
M tcg/mips/tcg-target.h
Log Message:
-----------
tcg/mips: Move TCG_AREG0 to S8
No functional change; just moving the saved reserved regs to the end.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 43b4cd97131f3e99e6bf397ed3874855fac9cdff
https://github.com/qemu/qemu/commit/43b4cd97131f3e99e6bf397ed3874855fac9cdff
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-25 (Thu, 25 May 2023)
Changed paths:
M tcg/mips/tcg-target.c.inc
Log Message:
-----------
tcg/mips: Move TCG_GUEST_BASE_REG to S7
No functional change; just moving the saved reserved regs to the end.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: f63eb2e59f45a2307f2e3f41e82e76f7abcd03f0
https://github.com/qemu/qemu/commit/f63eb2e59f45a2307f2e3f41e82e76f7abcd03f0
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-25 (Thu, 25 May 2023)
Changed paths:
M tcg/mips/tcg-target.c.inc
Log Message:
-----------
tcg/mips: Unify TCG_GUEST_BASE_REG tests
In tcg_out_qemu_ld/st, we already check for guest_base matching int16_t.
Mirror that when setting up TCG_GUEST_BASE_REG in the prologue.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 53c4fa2726629b2f34a23082e6f985bd36c3e1f7
https://github.com/qemu/qemu/commit/53c4fa2726629b2f34a23082e6f985bd36c3e1f7
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-25 (Thu, 25 May 2023)
Changed paths:
M tcg/mips/tcg-target.c.inc
Log Message:
-----------
tcg/mips: Create and use TCG_REG_TB
This vastly reduces the size of code generated for 64-bit addresses.
The code for exit_tb, for instance, where we load a (tagged) pointer
to the current TB, goes from
0x400aa9725c: li v0,64
0x400aa97260: dsll v0,v0,0x10
0x400aa97264: ori v0,v0,0xaa9
0x400aa97268: dsll v0,v0,0x10
0x400aa9726c: j 0x400aa9703c
0x400aa97270: ori v0,v0,0x7083
to
0x400aa97240: j 0x400aa97040
0x400aa97244: daddiu v0,s6,-189
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 47a572865ab8fc7772113ed15fb6e618b8d5763a
https://github.com/qemu/qemu/commit/47a572865ab8fc7772113ed15fb6e618b8d5763a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-25 (Thu, 25 May 2023)
Changed paths:
M tcg/mips/tcg-target.c.inc
Log Message:
-----------
tcg/mips: Split out tcg_out_movi_one
Emit all constants that can be loaded in exactly one insn.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 1d9c5b30846930fa29cd8cfe3b4f66396cc181a0
https://github.com/qemu/qemu/commit/1d9c5b30846930fa29cd8cfe3b4f66396cc181a0
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-25 (Thu, 25 May 2023)
Changed paths:
M tcg/mips/tcg-target.c.inc
Log Message:
-----------
tcg/mips: Split out tcg_out_movi_two
Emit all 32-bit signed constants, which can be loaded in two insns.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 48c12ba748bae9d8c5d20748226115f91fb88ad9
https://github.com/qemu/qemu/commit/48c12ba748bae9d8c5d20748226115f91fb88ad9
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-25 (Thu, 25 May 2023)
Changed paths:
M tcg/mips/tcg-target.c.inc
M tcg/mips/tcg-target.h
Log Message:
-----------
tcg/mips: Use the constant pool for 64-bit constants
During normal processing, the constant pool is accessible via
TCG_REG_TB. During the prologue, it is accessible via TCG_REG_T9.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 4316de32e71ae2626bbf8483a0265c61d3e3a05f
https://github.com/qemu/qemu/commit/4316de32e71ae2626bbf8483a0265c61d3e3a05f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-25 (Thu, 25 May 2023)
Changed paths:
M tcg/mips/tcg-target.c.inc
Log Message:
-----------
tcg/mips: Aggressively use the constant pool for n64 calls
Repeated calls to a single helper are common -- especially
the ones for softmmu memory access. Prefer the constant pool
to longer sequences to increase sharing.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 1d159e64cca6497565cdcbb0a8383fc8568b4983
https://github.com/qemu/qemu/commit/1d159e64cca6497565cdcbb0a8383fc8568b4983
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-25 (Thu, 25 May 2023)
Changed paths:
M tcg/mips/tcg-target.c.inc
Log Message:
-----------
tcg/mips: Try tb-relative addresses in tcg_out_movi
These addresses are often loaded by the qemu_ld/st slow path,
for loading the retaddr value.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 269e93ab76bc8b6239e12e427591fa46fb8c5be8
https://github.com/qemu/qemu/commit/269e93ab76bc8b6239e12e427591fa46fb8c5be8
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-25 (Thu, 25 May 2023)
Changed paths:
M tcg/mips/tcg-target.c.inc
Log Message:
-----------
tcg/mips: Try three insns with shift and add in tcg_out_movi
These sequences are inexpensive to test. Maxing out at three insns
results in the same space as a load plus the constant pool entry.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: c64ed451a9e9e5c8d27c4cf4c41940171a3b2afd
https://github.com/qemu/qemu/commit/c64ed451a9e9e5c8d27c4cf4c41940171a3b2afd
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-25 (Thu, 25 May 2023)
Changed paths:
M tcg/mips/tcg-target.c.inc
Log Message:
-----------
tcg/mips: Use qemu_build_not_reached for LO/HI_OFF
The new(ish) macro produces a compile-time error instead
of a link-time error.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: b56d5a8a4b0352bd499e026b8bdbdcf5f12753ac
https://github.com/qemu/qemu/commit/b56d5a8a4b0352bd499e026b8bdbdcf5f12753ac
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-25 (Thu, 25 May 2023)
Changed paths:
M tcg/mips/tcg-target.c.inc
Log Message:
-----------
tcg/mips: Replace MIPS_BE with HOST_BIG_ENDIAN
Since e03b56863d2b, which replaced HOST_WORDS_BIGENDIAN
with HOST_BIG_ENDIAN, there is no need to define a second
symbol which is [0,1].
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: d397be9a2256a7cc00a2b00355ad9c869ad61493
https://github.com/qemu/qemu/commit/d397be9a2256a7cc00a2b00355ad9c869ad61493
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-25 (Thu, 25 May 2023)
Changed paths:
M disas/riscv.c
Log Message:
-----------
disas/riscv: Decode czero.{eqz,nez}
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 9e3e0bc6ac38e339aa142afa23604382f9963ed1
https://github.com/qemu/qemu/commit/9e3e0bc6ac38e339aa142afa23604382f9963ed1
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-25 (Thu, 25 May 2023)
Changed paths:
M tcg/riscv/tcg-target.c.inc
M tcg/riscv/tcg-target.h
Log Message:
-----------
tcg/riscv: Probe for Zba, Zbb, Zicond extensions
Define a useful subset of the extensions. Probe for them
via compiler pre-processor feature macros and SIGILL.
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 99f4ec6eab2f1b818b4613ca041e73ef00add350
https://github.com/qemu/qemu/commit/99f4ec6eab2f1b818b4613ca041e73ef00add350
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-25 (Thu, 25 May 2023)
Changed paths:
M tcg/riscv/tcg-target-con-set.h
M tcg/riscv/tcg-target-con-str.h
M tcg/riscv/tcg-target.c.inc
M tcg/riscv/tcg-target.h
Log Message:
-----------
tcg/riscv: Support ANDN, ORN, XNOR from Zbb
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: d1c3f4e9ed160505c10b3d2acccf43e70e799ed3
https://github.com/qemu/qemu/commit/d1c3f4e9ed160505c10b3d2acccf43e70e799ed3
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-25 (Thu, 25 May 2023)
Changed paths:
M tcg/riscv/tcg-target.c.inc
Log Message:
-----------
tcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from Zba+Zbb
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: eda151599654e3981967052defd49945e7879596
https://github.com/qemu/qemu/commit/eda151599654e3981967052defd49945e7879596
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-25 (Thu, 25 May 2023)
Changed paths:
M tcg/riscv/tcg-target.c.inc
Log Message:
-----------
tcg/riscv: Use ADD.UW for guest address generation
The instruction is a combined zero-extend and add.
Use it for exactly that.
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 19d016ad9730dd9f04689a65c442b806d941f3a5
https://github.com/qemu/qemu/commit/19d016ad9730dd9f04689a65c442b806d941f3a5
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-25 (Thu, 25 May 2023)
Changed paths:
M tcg/riscv/tcg-target.c.inc
M tcg/riscv/tcg-target.h
Log Message:
-----------
tcg/riscv: Support rotates from Zbb
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 7b4d5274279dbca4b9a83a0a64bc7fb10d7e3970
https://github.com/qemu/qemu/commit/7b4d5274279dbca4b9a83a0a64bc7fb10d7e3970
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-25 (Thu, 25 May 2023)
Changed paths:
M tcg/riscv/tcg-target.c.inc
M tcg/riscv/tcg-target.h
Log Message:
-----------
tcg/riscv: Support REV8 from Zbb
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 0956ecda9fad9e81b8cbb1e5a05ae60bf6971f2d
https://github.com/qemu/qemu/commit/0956ecda9fad9e81b8cbb1e5a05ae60bf6971f2d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-25 (Thu, 25 May 2023)
Changed paths:
M tcg/riscv/tcg-target.c.inc
M tcg/riscv/tcg-target.h
Log Message:
-----------
tcg/riscv: Support CPOP from Zbb
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: f6453695f9f87ba1974eca13322864810c90b9f0
https://github.com/qemu/qemu/commit/f6453695f9f87ba1974eca13322864810c90b9f0
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-25 (Thu, 25 May 2023)
Changed paths:
M tcg/riscv/tcg-target.c.inc
Log Message:
-----------
tcg/riscv: Improve setcond expansion
Split out a helper function, tcg_out_setcond_int, which does not
always produce the complete boolean result, but returns a set of
flags to do so.
Based on 21af16198425, the same improvement for loongarch64.
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: a18d783e649d761a7556f6d964efa453bb4f3a06
https://github.com/qemu/qemu/commit/a18d783e649d761a7556f6d964efa453bb4f3a06
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-25 (Thu, 25 May 2023)
Changed paths:
M tcg/riscv/tcg-target-con-set.h
M tcg/riscv/tcg-target.c.inc
M tcg/riscv/tcg-target.h
Log Message:
-----------
tcg/riscv: Implement movcond
Implement with and without Zicond. Without Zicond, we were letting
the middle-end expand to a 5 insn sequence; better to use a branch
over a single insn.
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: a30498fcea5a8b9c544324ccfb0186090104b229
https://github.com/qemu/qemu/commit/a30498fcea5a8b9c544324ccfb0186090104b229
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-25 (Thu, 25 May 2023)
Changed paths:
M tcg/riscv/tcg-target-con-set.h
M tcg/riscv/tcg-target.c.inc
M tcg/riscv/tcg-target.h
Log Message:
-----------
tcg/riscv: Support CTZ, CLZ from Zbb
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: a3cb6d5004ff638aefe686ecd540718a793bd1b1
https://github.com/qemu/qemu/commit/a3cb6d5004ff638aefe686ecd540718a793bd1b1
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-25 (Thu, 25 May 2023)
Changed paths:
M disas/riscv.c
M tcg/mips/tcg-target.c.inc
M tcg/mips/tcg-target.h
M tcg/riscv/tcg-target-con-set.h
M tcg/riscv/tcg-target-con-str.h
M tcg/riscv/tcg-target.c.inc
M tcg/riscv/tcg-target.h
Log Message:
-----------
Merge tag 'pull-tcg-20230525' of https://gitlab.com/rth7680/qemu into staging
tcg/mips:
- Constant formation improvements
- Replace MIPS_BE with HOST_BIG_ENDIAN
- General cleanups
tcg/riscv:
- Improve setcond
- Support movcond
- Support Zbb, Zba
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[ultimate]
* tag 'pull-tcg-20230525' of https://gitlab.com/rth7680/qemu: (23 commits)
tcg/riscv: Support CTZ, CLZ from Zbb
tcg/riscv: Implement movcond
tcg/riscv: Improve setcond expansion
tcg/riscv: Support CPOP from Zbb
tcg/riscv: Support REV8 from Zbb
tcg/riscv: Support rotates from Zbb
tcg/riscv: Use ADD.UW for guest address generation
tcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from Zba+Zbb
tcg/riscv: Support ANDN, ORN, XNOR from Zbb
tcg/riscv: Probe for Zba, Zbb, Zicond extensions
disas/riscv: Decode czero.{eqz,nez}
tcg/mips: Replace MIPS_BE with HOST_BIG_ENDIAN
tcg/mips: Use qemu_build_not_reached for LO/HI_OFF
tcg/mips: Try three insns with shift and add in tcg_out_movi
tcg/mips: Try tb-relative addresses in tcg_out_movi
tcg/mips: Aggressively use the constant pool for n64 calls
tcg/mips: Use the constant pool for 64-bit constants
tcg/mips: Split out tcg_out_movi_two
tcg/mips: Split out tcg_out_movi_one
tcg/mips: Create and use TCG_REG_TB
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/6ad2c71c2381...a3cb6d5004ff