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[Qemu-commits] [qemu/qemu] 1f14c9: iothread: Set the GSource "name" fiel
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From: |
Alex Bennée |
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Subject: |
[Qemu-commits] [qemu/qemu] 1f14c9: iothread: Set the GSource "name" field |
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Date: |
Fri, 08 Sep 2023 03:37:45 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 1f14c9147c55149f2d631c8f661da53cd930c8c4
https://github.com/qemu/qemu/commit/1f14c9147c55149f2d631c8f661da53cd930c8c4
Author: Fabiano Rosas <farosas@suse.de>
Date: 2023-09-07 (Thu, 07 Sep 2023)
Changed paths:
M iothread.c
Log Message:
-----------
iothread: Set the GSource "name" field
Having a name in the source helps with debugging core dumps when one
might not have access to TLS data to cross-reference AioContexts with
their addresses.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230905180359.14083-1-farosas@suse.de
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: bc4e68d362ec4be9cd54fea181dca2b5b0435865
https://github.com/qemu/qemu/commit/bc4e68d362ec4be9cd54fea181dca2b5b0435865
Author: Jeuk Kim <jeuk20.kim@samsung.com>
Date: 2023-09-07 (Thu, 07 Sep 2023)
Changed paths:
M MAINTAINERS
M docs/specs/pci-ids.rst
M hw/Kconfig
M hw/meson.build
A hw/ufs/Kconfig
A hw/ufs/meson.build
A hw/ufs/trace-events
A hw/ufs/trace.h
A hw/ufs/ufs.c
A hw/ufs/ufs.h
A include/block/ufs.h
M include/hw/pci/pci.h
M include/hw/pci/pci_ids.h
M meson.build
Log Message:
-----------
hw/ufs: Initial commit for emulated Universal-Flash-Storage
Universal Flash Storage (UFS) is a high-performance mass storage device
with a serial interface. It is primarily used as a high-performance
data storage device for embedded applications.
This commit contains code for UFS device to be recognized
as a UFS PCI device.
Patches to handle UFS logical unit and Transfer Request will follow.
Signed-off-by: Jeuk Kim <jeuk20.kim@samsung.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-id:
10232660d462ee5cd10cf673f1a9a1205fc8276c.1693980783.git.jeuk20.kim@gmail.com
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 329f16624499cf7ee7640a7addb2dc51c1e6f030
https://github.com/qemu/qemu/commit/329f16624499cf7ee7640a7addb2dc51c1e6f030
Author: Jeuk Kim <jeuk20.kim@samsung.com>
Date: 2023-09-07 (Thu, 07 Sep 2023)
Changed paths:
M hw/ufs/trace-events
M hw/ufs/ufs.c
M hw/ufs/ufs.h
Log Message:
-----------
hw/ufs: Support for Query Transfer Requests
This commit makes the UFS device support query
and nop out transfer requests.
The next patch would be support for UFS logical
unit and scsi command transfer request.
Signed-off-by: Jeuk Kim <jeuk20.kim@samsung.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-id:
ff7a5f0fd26761936a553ffb89d3df0ba62844e9.1693980783.git.jeuk20.kim@gmail.com
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 2a8b36a4967db84b82ac248f60b981bcddb804b6
https://github.com/qemu/qemu/commit/2a8b36a4967db84b82ac248f60b981bcddb804b6
Author: Jeuk Kim <jeuk20.kim@samsung.com>
Date: 2023-09-07 (Thu, 07 Sep 2023)
Changed paths:
A hw/ufs/lu.c
M hw/ufs/meson.build
M hw/ufs/trace-events
M hw/ufs/ufs.c
M hw/ufs/ufs.h
M include/scsi/constants.h
Log Message:
-----------
hw/ufs: Support for UFS logical unit
This commit adds support for ufs logical unit.
The LU handles processing for the SCSI command,
unit descriptor query request.
This commit enables the UFS device to process
IO requests.
Signed-off-by: Jeuk Kim <jeuk20.kim@samsung.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-id:
beacc504376ab6a14b1a3830bb3c69382cf6aebc.1693980783.git.jeuk20.kim@gmail.com
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 631c872614aca91eaf947c1748f0f27f99635d92
https://github.com/qemu/qemu/commit/631c872614aca91eaf947c1748f0f27f99635d92
Author: Jeuk Kim <jeuk20.kim@samsung.com>
Date: 2023-09-07 (Thu, 07 Sep 2023)
Changed paths:
M MAINTAINERS
M tests/qtest/meson.build
A tests/qtest/ufs-test.c
Log Message:
-----------
tests/qtest: Introduce tests for UFS
This patch includes the following tests
Test mmio read
Test ufs device initialization and ufs-lu recognition
Test I/O (Performs a write followed by a read to verify)
Signed-off-by: Jeuk Kim <jeuk20.kim@samsung.com>
Acked-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-id:
9e9207f54505e9ba30931849f949ff6f474ac333.1693980783.git.jeuk20.kim@gmail.com
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: b87151a848b0019775bfddb16b79f5adcad3f36c
https://github.com/qemu/qemu/commit/b87151a848b0019775bfddb16b79f5adcad3f36c
Author: Andrey Drobyshev <andrey.drobyshev@virtuozzo.com>
Date: 2023-09-07 (Thu, 07 Sep 2023)
Changed paths:
M tests/qemu-iotests/197
M tests/qemu-iotests/197.out
Log Message:
-----------
qemu-iotests/197: use more generic commands for formats other than qcow2
In the previous commit e2f938265e0 ("tests/qemu-iotests/197: add
testcase for CoR with subclusters") we've introduced a new testcase for
copy-on-read with subclusters. Test 197 always forces qcow2 as the top
image, but allows backing image to be in any format. That last test
case didn't meet these requirements, so let's fix it by using more
generic "qemu-io -c map" command.
Signed-off-by: Andrey Drobyshev <andrey.drobyshev@virtuozzo.com>
Message-ID: <20230907220718.983430-1-andrey.drobyshev@virtuozzo.com>
Tested-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Eric Blake <eblake@redhat.com>
Commit: b84ca91ca28d044b2a7371a8ea797c9e75d8abb4
https://github.com/qemu/qemu/commit/b84ca91ca28d044b2a7371a8ea797c9e75d8abb4
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-09-07 (Thu, 07 Sep 2023)
Changed paths:
M include/block/nbd.h
M nbd/client-connection.c
M nbd/client.c
M qemu-nbd.c
Log Message:
-----------
nbd: drop unused nbd_receive_negotiate() aio_context argument
aio_context is always NULL, so drop it.
Suggested-by: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230830224802.493686-2-stefanha@redhat.com>
Signed-off-by: Eric Blake <eblake@redhat.com>
Commit: 078c8adaa61df4fe081660f0c14ce35ddd938de0
https://github.com/qemu/qemu/commit/078c8adaa61df4fe081660f0c14ce35ddd938de0
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-09-07 (Thu, 07 Sep 2023)
Changed paths:
M nbd/client.c
Log Message:
-----------
nbd: drop unused nbd_start_negotiate() aio_context argument
aio_context is always NULL, so drop it.
Suggested-by: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230830224802.493686-3-stefanha@redhat.com>
Signed-off-by: Eric Blake <eblake@redhat.com>
Commit: acd4be64b865e81094c690503b4f39804eb67a0b
https://github.com/qemu/qemu/commit/acd4be64b865e81094c690503b4f39804eb67a0b
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-09-07 (Thu, 07 Sep 2023)
Changed paths:
M io/channel.c
Log Message:
-----------
io: check there are no qio_channel_yield() coroutines during ->finalize()
Callers must clean up their coroutines before calling
object_unref(OBJECT(ioc)) to prevent an fd handler leak. Add an
assertion to check this.
This patch is preparation for the fd handler changes that follow.
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-ID: <20230830224802.493686-4-stefanha@redhat.com>
Signed-off-by: Eric Blake <eblake@redhat.com>
Commit: 06e0f098d612df79597de58121dadf6f5f375d04
https://github.com/qemu/qemu/commit/06e0f098d612df79597de58121dadf6f5f375d04
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-09-07 (Thu, 07 Sep 2023)
Changed paths:
M block/nbd.c
M include/io/channel-util.h
M include/io/channel.h
M include/qemu/vhost-user-server.h
M io/channel-command.c
M io/channel-file.c
M io/channel-null.c
M io/channel-socket.c
M io/channel-tls.c
M io/channel-util.c
M io/channel.c
M migration/channel-block.c
M migration/rdma.c
M nbd/server.c
M scsi/qemu-pr-helper.c
M util/vhost-user-server.c
Log Message:
-----------
io: follow coroutine AioContext in qio_channel_yield()
The ongoing QEMU multi-queue block layer effort makes it possible for multiple
threads to process I/O in parallel. The nbd block driver is not compatible with
the multi-queue block layer yet because QIOChannel cannot be used easily from
coroutines running in multiple threads. This series changes the QIOChannel API
to make that possible.
In the current API, calling qio_channel_attach_aio_context() sets the
AioContext where qio_channel_yield() installs an fd handler prior to yielding:
qio_channel_attach_aio_context(ioc, my_ctx);
...
qio_channel_yield(ioc); // my_ctx is used here
...
qio_channel_detach_aio_context(ioc);
This API design has limitations: reading and writing must be done in the same
AioContext and moving between AioContexts involves a cumbersome sequence of API
calls that is not suitable for doing on a per-request basis.
There is no fundamental reason why a QIOChannel needs to run within the
same AioContext every time qio_channel_yield() is called. QIOChannel
only uses the AioContext while inside qio_channel_yield(). The rest of
the time, QIOChannel is independent of any AioContext.
In the new API, qio_channel_yield() queries the AioContext from the current
coroutine using qemu_coroutine_get_aio_context(). There is no need to
explicitly attach/detach AioContexts anymore and
qio_channel_attach_aio_context() and qio_channel_detach_aio_context() are gone.
One coroutine can read from the QIOChannel while another coroutine writes from
a different AioContext.
This API change allows the nbd block driver to use QIOChannel from any thread.
It's important to keep in mind that the block driver already synchronizes
QIOChannel access and ensures that two coroutines never read simultaneously or
write simultaneously.
This patch updates all users of qio_channel_attach_aio_context() to the
new API. Most conversions are simple, but vhost-user-server requires a
new qemu_coroutine_yield() call to quiesce the vu_client_trip()
coroutine when not attached to any AioContext.
While the API is has become simpler, there is one wart: QIOChannel has a
special case for the iohandler AioContext (used for handlers that must not run
in nested event loops). I didn't find an elegant way preserve that behavior, so
I added a new API called qio_channel_set_follow_coroutine_ctx(ioc, true|false)
for opting in to the new AioContext model. By default QIOChannel uses the
iohandler AioHandler. Code that formerly called
qio_channel_attach_aio_context() now calls
qio_channel_set_follow_coroutine_ctx(ioc, true) once after the QIOChannel is
created.
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Acked-by: Daniel P. Berrangé <berrange@redhat.com>
Message-ID: <20230830224802.493686-5-stefanha@redhat.com>
[eblake: also fix migration/rdma.c]
Signed-off-by: Eric Blake <eblake@redhat.com>
Commit: 522a9b94e0f8a1f89f1660a46121ab0d0eae3593
https://github.com/qemu/qemu/commit/522a9b94e0f8a1f89f1660a46121ab0d0eae3593
Author: Philippe Mathieu-Daudé <philmd@redhat.com>
Date: 2023-09-07 (Thu, 07 Sep 2023)
Changed paths:
M util/iov.c
Log Message:
-----------
util/iov: Avoid dynamic stack allocation
Use autofree heap allocation instead of variable-length array on the
stack.
The codebase has very few VLAs, and if we can get rid of them all we
can make the compiler error on new additions. This is a defensive
measure against security bugs where an on-stack dynamic allocation
isn't correctly size-checked (e.g. CVE-2021-3527).
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-ID: <20230824164706.2652277-1-peter.maydell@linaro.org>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Eric Blake <eblake@redhat.com>
Commit: b4bbdf51e3af2ac7a8dd269bcdadd11523978dda
https://github.com/qemu/qemu/commit/b4bbdf51e3af2ac7a8dd269bcdadd11523978dda
Author: Denis V. Lunev <den@openvz.org>
Date: 2023-09-07 (Thu, 07 Sep 2023)
Changed paths:
M qemu-nbd.c
Log Message:
-----------
qemu-nbd: improve error message for dup2 error
This error happens if we are not able to close the pipe to the
parent (to trace errors in the child process) and assign stderr to
/dev/null as required by the daemonizing convention.
Signed-off-by: Denis V. Lunev <den@openvz.org>
Suggested-by: Eric Blake <eblake@redhat.com>
CC: Eric Blake <eblake@redhat.com>
CC: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
Message-ID: <20230906093210.339585-2-den@openvz.org>
Reviewed-by: Eric Blake <eblake@redhat.com>
[eblake: commit message grammar]
Signed-off-by: Eric Blake <eblake@redhat.com>
Commit: 3484f6769cbf9a2ebd47e316a6c39bf42fca0dcc
https://github.com/qemu/qemu/commit/3484f6769cbf9a2ebd47e316a6c39bf42fca0dcc
Author: Denis V. Lunev <den@openvz.org>
Date: 2023-09-07 (Thu, 07 Sep 2023)
Changed paths:
M qemu-nbd.c
Log Message:
-----------
qemu-nbd: define struct NbdClientOpts when HAVE_NBD_DEVICE is not defined
This patch also drops definition of some locals in main() to avoid
useless data copy.
Signed-off-by: Denis V. Lunev <den@openvz.org>
CC: Eric Blake <eblake@redhat.com>
CC: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
Message-ID: <20230906093210.339585-3-den@openvz.org>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Eric Blake <eblake@redhat.com>
Commit: b18d72d7230dcd18919af820b52f6c0f1b2512ca
https://github.com/qemu/qemu/commit/b18d72d7230dcd18919af820b52f6c0f1b2512ca
Author: Denis V. Lunev <den@openvz.org>
Date: 2023-09-07 (Thu, 07 Sep 2023)
Changed paths:
M qemu-nbd.c
Log Message:
-----------
qemu-nbd: move srcpath into struct NbdClientOpts
We pass other parameters into nbd_client_thread() in this way. This patch
makes the code more consistent.
Signed-off-by: Denis V. Lunev <den@openvz.org>
CC: Eric Blake <eblake@redhat.com>
CC: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
Message-ID: <20230906093210.339585-4-den@openvz.org>
Reviewed-by: Eric Blake <eblake@redhat.com>
[eblake: Note that this also cleans up a -Wshadow issue, first
introduced in e5b815b0]
Signed-off-by: Eric Blake <eblake@redhat.com>
Commit: b2cecdfee3e68297a4de26aa3188d4025bdef4ca
https://github.com/qemu/qemu/commit/b2cecdfee3e68297a4de26aa3188d4025bdef4ca
Author: Denis V. Lunev <den@openvz.org>
Date: 2023-09-07 (Thu, 07 Sep 2023)
Changed paths:
M qemu-nbd.c
Log Message:
-----------
qemu-nbd: put saddr into into struct NbdClientOpts
We pass other parameters into nbd_client_thread() in this way. This patch
makes the code more consistent.
Signed-off-by: Denis V. Lunev <den@openvz.org>
CC: Eric Blake <eblake@redhat.com>
CC: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
Message-ID: <20230906093210.339585-5-den@openvz.org>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Eric Blake <eblake@redhat.com>
Commit: 2eb7c2abe0b85a945549e91cb794d214c0905403
https://github.com/qemu/qemu/commit/2eb7c2abe0b85a945549e91cb794d214c0905403
Author: Denis V. Lunev <den@openvz.org>
Date: 2023-09-07 (Thu, 07 Sep 2023)
Changed paths:
M qemu-nbd.c
Log Message:
-----------
qemu-nbd: invent nbd_client_release_pipe() helper
Move the code from main() and nbd_client_thread() into the specific
helper. This code is going to be grown.
Signed-off-by: Denis V. Lunev <den@openvz.org>
CC: Eric Blake <eblake@redhat.com>
CC: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
Message-ID: <20230906093210.339585-6-den@openvz.org>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Eric Blake <eblake@redhat.com>
Commit: 5a5410e2eb12062d140e5a44afc589fd3f870757
https://github.com/qemu/qemu/commit/5a5410e2eb12062d140e5a44afc589fd3f870757
Author: Denis V. Lunev <den@openvz.org>
Date: 2023-09-07 (Thu, 07 Sep 2023)
Changed paths:
M qemu-nbd.c
Log Message:
-----------
qemu-nbd: Restore "qemu-nbd -v --fork" output
Closing stderr earlier is good for daemonized qemu-nbd under ssh
earlier, but breaks the case where -v is being used to track what is
happening in the server, as in iotest 233.
When we know we are verbose, we should preserve original stderr and
restore it once the setup stage is done. This commit restores the
original behavior with -v option. In this case original output
inside the test is kept intact.
Reported-by: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Denis V. Lunev <den@openvz.org>
CC: Eric Blake <eblake@redhat.com>
CC: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
CC: Hanna Reitz <hreitz@redhat.com>
CC: Mike Maslenkin <mike.maslenkin@gmail.com>
Fixes: 5c56dd27a2 ("qemu-nbd: fix regression with qemu-nbd --fork run over ssh")
Message-ID: <20230906093210.339585-7-den@openvz.org>
Reviewed-by: Eric Blake <eblake@redhat.com>
Tested-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Eric Blake <eblake@redhat.com>
Commit: 737ff1b137b7ce1d613c3851e0efaae9b820dbc0
https://github.com/qemu/qemu/commit/737ff1b137b7ce1d613c3851e0efaae9b820dbc0
Author: Denis V. Lunev <den@openvz.org>
Date: 2023-09-07 (Thu, 07 Sep 2023)
Changed paths:
M docs/tools/qemu-nbd.rst
Log Message:
-----------
qemu-nbd: document -v behavior in respect to --fork in man
Signed-off-by: Denis V. Lunev <den@openvz.org>
CC: Eric Blake <eblake@redhat.com>
CC: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
Message-ID: <20230906093210.339585-8-den@openvz.org>
Reviewed-by: Eric Blake <eblake@redhat.com>
[eblake: Wording improvement]
Signed-off-by: Eric Blake <eblake@redhat.com>
Commit: 38e0c21d74f8f070aab365c8e9884f8996554b45
https://github.com/qemu/qemu/commit/38e0c21d74f8f070aab365c8e9884f8996554b45
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: do not run 'host' CPU with TCG
The 'host' CPU is available in a CONFIG_KVM build and it's currently
available for all accels, but is a KVM only CPU. This means that in a
RISC-V KVM capable host we can do things like this:
$ ./build/qemu-system-riscv64 -M virt,accel=tcg -cpu host --nographic
qemu-system-riscv64: H extension requires priv spec 1.12.0
This CPU does not have a priv spec because we don't filter its extensions
via priv spec. We shouldn't be reaching riscv_cpu_realize_tcg() at all
with the 'host' CPU.
We don't have a way to filter the 'host' CPU out of the available CPU
options (-cpu help) if the build includes both KVM and TCG. What we can
do is to error out during riscv_cpu_realize_tcg() if the user chooses
the 'host' CPU with accel=tcg:
$ ./build/qemu-system-riscv64 -M virt,accel=tcg -cpu host --nographic
qemu-system-riscv64: 'host' CPU is not compatible with TCG acceleration
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230721133411.474105-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: fbe65c7d5fafc875a1aa035e2604bb8012f3900f
https://github.com/qemu/qemu/commit/fbe65c7d5fafc875a1aa035e2604bb8012f3900f
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M hw/char/riscv_htif.c
Log Message:
-----------
hw/char/riscv_htif: Fix printing of console characters on big endian hosts
The character that should be printed is stored in the 64 bit "payload"
variable. The code currently tries to print it by taking the address
of the variable and passing this pointer to qemu_chr_fe_write(). However,
this only works on little endian hosts where the least significant bits
are stored on the lowest address. To do this in a portable way, we have
to store the value in an uint8_t variable instead.
Fixes: 5033606780 ("RISC-V HTIF Console")
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230721094720.902454-2-thuth@redhat.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 5d231650f14636386f47a5c8005cff43b06a802f
https://github.com/qemu/qemu/commit/5d231650f14636386f47a5c8005cff43b06a802f
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M hw/char/riscv_htif.c
Log Message:
-----------
hw/char/riscv_htif: Fix the console syscall on big endian hosts
Values that have been read via cpu_physical_memory_read() from the
guest's memory have to be swapped in case the host endianess differs
from the guest.
Fixes: a6e13e31d5 ("riscv_htif: Support console output via proxy syscall")
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230721094720.902454-3-thuth@redhat.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b250aab322ff1fdff8a60c5362173372c3dc03b1
https://github.com/qemu/qemu/commit/b250aab322ff1fdff8a60c5362173372c3dc03b1
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: add zmmul isa string
zmmul was promoted from experimental to ratified in commit 6d00ffad4e95.
Add a riscv,isa string for it.
Fixes: 6d00ffad4e95 ("target/riscv: move zmmul out of the experimental
properties")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230720132424.371132-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 70157755eb22c670610caa3bb9c25cbc598200ae
https://github.com/qemu/qemu/commit/70157755eb22c670610caa3bb9c25cbc598200ae
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: add smepmp isa string
The cpu->cfg.epmp extension is still experimental, but it already has a
'smepmp' riscv,isa string. Add it.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230720132424.371132-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1d99aae6e0ddb356f6c05540bc713ed2151db953
https://github.com/qemu/qemu/commit/1d99aae6e0ddb356f6c05540bc713ed2151db953
Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: Fix page_check_range use in fault-only-first
Commit bef6f008b98(accel/tcg: Return bool from page_check_range) converts
integer return value to bool type. However, it wrongly converted the use
of the API in riscv fault-only-first, where page_check_range < = 0, should
be converted to !page_check_range.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230729031618.821-1-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e8d71e49faa281f0598d0aee44c1a45e6fa11312
https://github.com/qemu/qemu/commit/e8d71e49faa281f0598d0aee44c1a45e6fa11312
Author: Ard Biesheuvel <ardb@kernel.org>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M crypto/aes.c
M include/crypto/aes.h
M target/riscv/crypto_helper.c
Log Message:
-----------
target/riscv: Use existing lookup tables for MixColumns
The AES MixColumns and InvMixColumns operations are relatively
expensive 4x4 matrix multiplications in GF(2^8), which is why C
implementations usually rely on precomputed lookup tables rather than
performing the calculations on demand.
Given that we already carry those tables in QEMU, we can just grab the
right value in the implementation of the RISC-V AES32 instructions. Note
that the tables in question are permuted according to the respective
Sbox, so we can omit the Sbox lookup as well in this case.
Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Philippe Mathieu-Daudé <philmd@linaro.org>
Cc: Zewen Ye <lustrew@foxmail.com>
Cc: Weiwei Li <liweiwei@iscas.ac.cn>
Cc: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230731084043.1791984-1-ardb@kernel.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 27ca678c22abcfc6c04d62aa077003eb89fddb0f
https://github.com/qemu/qemu/commit/27ca678c22abcfc6c04d62aa077003eb89fddb0f
Author: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/meson.build
M target/riscv/vector_helper.c
A target/riscv/vector_internals.c
A target/riscv/vector_internals.h
Log Message:
-----------
target/riscv: Refactor some of the generic vector functionality
Take some functions/macros out of `vector_helper` and put them in a new
module called `vector_internals`. This ensures they can be used by both
vector and vector-crypto helpers (latter implemented in proceeding
commits).
Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Max Chou <max.chou@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230711165917.2629866-2-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: cbcb0cf9e2193dd9a7d1b9368a94e7e7300d875d
https://github.com/qemu/qemu/commit/cbcb0cf9e2193dd9a7d1b9368a94e7e7300d875d
Author: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: Refactor vector-vector translation macro
Refactor the non SEW-specific stuff out of `GEN_OPIVV_TRANS` into
function `opivv_trans` (similar to `opivi_trans`). `opivv_trans` will be
used in proceeding vector-crypto commits.
Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20230711165917.2629866-3-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 0cd508bfb4388eda3ef8a58e92f2b0871991f7c7
https://github.com/qemu/qemu/commit/0cd508bfb4388eda3ef8a58e92f2b0871991f7c7
Author: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: Remove redundant "cpu_vl == 0" checks
Remove the redundant "vl == 0" check which is already included within the
vstart >= vl check, when vl == 0.
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Max Chou <max.chou@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230711165917.2629866-4-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 87afa0788bf590811217e27a2dbac76437731c57
https://github.com/qemu/qemu/commit/87afa0788bf590811217e27a2dbac76437731c57
Author: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/helper.h
M target/riscv/insn32.decode
A target/riscv/insn_trans/trans_rvvk.c.inc
M target/riscv/meson.build
M target/riscv/translate.c
A target/riscv/vcrypto_helper.c
Log Message:
-----------
target/riscv: Add Zvbc ISA extension support
This commit adds support for the Zvbc vector-crypto extension, which
consists of the following instructions:
* vclmulh.[vx,vv]
* vclmul.[vx,vv]
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.
Co-authored-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Co-authored-by: Max Chou <max.chou@sifive.com>
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Signed-off-by: Max Chou <max.chou@sifive.com>
[max.chou@sifive.com: Exposed x-zvbc property]
Message-ID: <20230711165917.2629866-5-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 38d2323a3039f445c832d2317c3f4a374cc2302f
https://github.com/qemu/qemu/commit/38d2323a3039f445c832d2317c3f4a374cc2302f
Author: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: Move vector translation checks
Move the checks out of `do_opiv{v,x,i}_gvec{,_shift}` functions
and into the corresponding macros. This enables the functions to be
reused in proceeding commits without check duplication.
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20230711165917.2629866-6-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 083172d080318f659cd6694be1524e3932a45b81
https://github.com/qemu/qemu/commit/083172d080318f659cd6694be1524e3932a45b81
Author: Dickon Hood <dickon.hood@codethink.co.uk>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: Refactor translation of vector-widening instruction
Zvbb (implemented in later commit) has a widening instruction, which
requires an extra check on the enabled extensions. Refactor
GEN_OPIVX_WIDEN_TRANS() to take a check function to avoid reimplementing
it.
Signed-off-by: Dickon Hood <dickon.hood@codethink.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20230711165917.2629866-7-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: fe60a4f6e573afcfe822f40ea4edc2209d2aba3b
https://github.com/qemu/qemu/commit/fe60a4f6e573afcfe822f40ea4edc2209d2aba3b
Author: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/vector_helper.c
M target/riscv/vector_internals.h
Log Message:
-----------
target/riscv: Refactor some of the generic vector functionality
Move some macros out of `vector_helper` and into `vector_internals`.
This ensures they can be used by both vector and vector-crypto helpers
(latter implemented in proceeding commits).
Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20230711165917.2629866-8-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 7eccce83f9757cac04983a73b0ea9fc6492af470
https://github.com/qemu/qemu/commit/7eccce83f9757cac04983a73b0ea9fc6492af470
Author: Dickon Hood <dickon.hood@codethink.co.uk>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/helper.h
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvvk.c.inc
M target/riscv/vcrypto_helper.c
Log Message:
-----------
target/riscv: Add Zvbb ISA extension support
This commit adds support for the Zvbb vector-crypto extension, which
consists of the following instructions:
* vrol.[vv,vx]
* vror.[vv,vx,vi]
* vbrev8.v
* vrev8.v
* vandn.[vv,vx]
* vbrev.v
* vclz.v
* vctz.v
* vcpop.v
* vwsll.[vv,vx,vi]
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.
Co-authored-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Co-authored-by: William Salmon <will.salmon@codethink.co.uk>
Co-authored-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
[max.chou@sifive.com: Fix imm mode of vror.vi]
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Signed-off-by: William Salmon <will.salmon@codethink.co.uk>
Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Signed-off-by: Dickon Hood <dickon.hood@codethink.co.uk>
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
[max.chou@sifive.com: Exposed x-zvbb property]
Message-ID: <20230711165917.2629866-9-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 6abe84e935dcbb3e6cfb6e6e396b663b1cc44c03
https://github.com/qemu/qemu/commit/6abe84e935dcbb3e6cfb6e6e396b663b1cc44c03
Author: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/helper.h
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvvk.c.inc
M target/riscv/vcrypto_helper.c
Log Message:
-----------
target/riscv: Add Zvkned ISA extension support
This commit adds support for the Zvkned vector-crypto extension, which
consists of the following instructions:
* vaesef.[vv,vs]
* vaesdf.[vv,vs]
* vaesdm.[vv,vs]
* vaesz.vs
* vaesem.[vv,vs]
* vaeskf1.vi
* vaeskf2.vi
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.
Co-authored-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Co-authored-by: William Salmon <will.salmon@codethink.co.uk>
[max.chou@sifive.com: Replaced vstart checking by TCG op]
Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Signed-off-by: William Salmon <will.salmon@codethink.co.uk>
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
[max.chou@sifive.com: Imported aes-round.h and exposed x-zvkned
property]
[max.chou@sifive.com: Fixed endian issues and replaced the vstart & vl
egs checking by helper function]
[max.chou@sifive.com: Replaced bswap32 calls in aes key expanding]
Message-ID: <20230711165917.2629866-10-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 56a6200645980d2998580f89cfe7194a7a7df550
https://github.com/qemu/qemu/commit/56a6200645980d2998580f89cfe7194a7a7df550
Author: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/helper.h
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvvk.c.inc
M target/riscv/vcrypto_helper.c
Log Message:
-----------
target/riscv: Add Zvknh ISA extension support
This commit adds support for the Zvknh vector-crypto extension, which
consists of the following instructions:
* vsha2ms.vv
* vsha2c[hl].vv
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.
Co-authored-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Co-authored-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
[max.chou@sifive.com: Replaced vstart checking by TCG op]
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
[max.chou@sifive.com: Exposed x-zvknha & x-zvknhb properties]
[max.chou@sifive.com: Replaced SEW selection to happened during
translation]
Message-ID: <20230711165917.2629866-11-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 6de7248b797fc80adc30fa43339be3b12d35958b
https://github.com/qemu/qemu/commit/6de7248b797fc80adc30fa43339be3b12d35958b
Author: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/helper.h
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvvk.c.inc
M target/riscv/vcrypto_helper.c
Log Message:
-----------
target/riscv: Add Zvksh ISA extension support
This commit adds support for the Zvksh vector-crypto extension, which
consists of the following instructions:
* vsm3me.vv
* vsm3c.vi
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.
Co-authored-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
[max.chou@sifive.com: Replaced vstart checking by TCG op]
Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
[max.chou@sifive.com: Exposed x-zvksh property]
Message-ID: <20230711165917.2629866-12-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a2c781666c67bbbde3b8d72ba5ad6995913856a1
https://github.com/qemu/qemu/commit/a2c781666c67bbbde3b8d72ba5ad6995913856a1
Author: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/helper.h
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvvk.c.inc
M target/riscv/vcrypto_helper.c
Log Message:
-----------
target/riscv: Add Zvkg ISA extension support
This commit adds support for the Zvkg vector-crypto extension, which
consists of the following instructions:
* vgmul.vv
* vghsh.vv
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.
Co-authored-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
[max.chou@sifive.com: Replaced vstart checking by TCG op]
Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
[max.chou@sifive.com: Exposed x-zvkg property]
[max.chou@sifive.com: Replaced uint by int for cross win32 build]
Message-ID: <20230711165917.2629866-13-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: ce1503ccae245497ddd9cc2ce9e3f6f47f3e6bdf
https://github.com/qemu/qemu/commit/ce1503ccae245497ddd9cc2ce9e3f6f47f3e6bdf
Author: Max Chou <max.chou@sifive.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M include/crypto/sm4.h
M target/arm/tcg/crypto_helper.c
Log Message:
-----------
crypto: Create sm4_subword
Allows sharing of sm4_subword between different targets.
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20230711165917.2629866-14-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 70185f4f712f784239c2f88346b81df3217ecd9d
https://github.com/qemu/qemu/commit/70185f4f712f784239c2f88346b81df3217ecd9d
Author: Max Chou <max.chou@sifive.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M crypto/sm4.c
M include/crypto/sm4.h
Log Message:
-----------
crypto: Add SM4 constant parameter CK
Adds sm4_ck constant for use in sm4 cryptography across different targets.
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20230711165917.2629866-15-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 2a58019cca2d0c6b53eb6c0ecc293afcf293b7a2
https://github.com/qemu/qemu/commit/2a58019cca2d0c6b53eb6c0ecc293afcf293b7a2
Author: Max Chou <max.chou@sifive.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/helper.h
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvvk.c.inc
M target/riscv/vcrypto_helper.c
Log Message:
-----------
target/riscv: Add Zvksed ISA extension support
This commit adds support for the Zvksed vector-crypto extension, which
consists of the following instructions:
* vsm4k.vi
* vsm4r.[vv,vs]
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
[lawrence.hunter@codethink.co.uk: Moved SM4 functions from
crypto_helper.c to vcrypto_helper.c]
[nazar.kazakov@codethink.co.uk: Added alignment checks, refactored code to
use macros, and minor style changes]
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20230711165917.2629866-16-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e26953e5e084667025ad33406958d05a3a7651f7
https://github.com/qemu/qemu/commit/e26953e5e084667025ad33406958d05a3a7651f7
Author: Rob Bradford <rbradford@rivosinc.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren
These are WARL fields - zero out the bits for unavailable counters and
special case the TM bit in mcountinhibit which is hardwired to zero.
This patch achieves this by modifying the value written so that any use
of the field will see the correctly masked bits.
Tested by modifying OpenSBI to write max value to these CSRs and upon
subsequent read the appropriate number of bits for number of PMUs is
enabled and the TM bit is zero in mcountinhibit.
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Message-ID: <20230802124906.24197-1-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: cabee16657e085c9f948064a73439651809f06b0
https://github.com/qemu/qemu/commit/cabee16657e085c9f948064a73439651809f06b0
Author: Jason Chien <jason.chien@sifive.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
Log Message:
-----------
target/riscv: Add Zihintntl extension ISA string to DTS
RVA23 Profiles states:
The RVA23 profiles are intended to be used for 64-bit application
processors that will run rich OS stacks from standard binary OS
distributions and with a substantial number of third-party binary user
applications that will be supported over a considerable length of time
in the field.
The chapter 4 of the unprivileged spec introduces the Zihintntl extension
and Zihintntl is a mandatory extension presented in RVA23 Profiles, whose
purpose is to enable application and operating system portability across
different implementations. Thus the DTS should contain the Zihintntl ISA
string in order to pass to software.
The unprivileged spec states:
Like any HINTs, these instructions may be freely ignored. Hence, although
they are described in terms of cache-based memory hierarchies, they do not
mandate the provision of caches.
These instructions are encoded with non-used opcode, e.g. ADD x0, x0, x2,
which QEMU already supports, and QEMU does not emulate cache. Therefore
these instructions can be considered as a no-op, and we only need to add
a new property for the Zihintntl extension.
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Jason Chien <jason.chien@sifive.com>
Message-ID: <20230726074049.19505-2-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a274c1f189ed875d38884b832d7e94900dcca9bb
https://github.com/qemu/qemu/commit/a274c1f189ed875d38884b832d7e94900dcca9bb
Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/insn_trans/trans_rvzfa.c.inc
Log Message:
-----------
target/riscv: Fix zfa fleq.d and fltq.d
Commit a47842d ("riscv: Add support for the Zfa extension") implemented the zfa
extension.
However, it has some typos for fleq.d and fltq.d. Both of them misused the
fltq.s
helper function.
Fixes: a47842d ("riscv: Add support for the Zfa extension")
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230728003906.768-1-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a8b92582692723698cc4906219b0dc49c56f2f0e
https://github.com/qemu/qemu/commit/a8b92582692723698cc4906219b0dc49c56f2f0e
Author: Jason Chien <jason.chien@sifive.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M hw/intc/riscv_aclint.c
Log Message:
-----------
hw/intc: Fix upper/lower mtime write calculation
When writing the upper mtime, we should keep the original lower mtime
whose value is given by cpu_riscv_read_rtc() instead of
cpu_riscv_read_rtc_raw(). The same logic applies to writes to lower mtime.
Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230728082502.26439-1-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: fdf5c4e6cbb5a0e61c8135af2313cc88f3338795
https://github.com/qemu/qemu/commit/fdf5c4e6cbb5a0e61c8135af2313cc88f3338795
Author: Jason Chien <jason.chien@sifive.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M hw/intc/riscv_aclint.c
Log Message:
-----------
hw/intc: Make rtc variable names consistent
The variables whose values are given by cpu_riscv_read_rtc() should be named
"rtc". The variables whose value are given by cpu_riscv_read_rtc_raw()
should be named "rtc_r".
Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230728082502.26439-2-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a824aa762fd7b6f25fc290d3b9b2ccb67c6d3f5a
https://github.com/qemu/qemu/commit/a824aa762fd7b6f25fc290d3b9b2ccb67c6d3f5a
Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M linux-user/riscv/signal.c
Log Message:
-----------
linux-user/riscv: Use abi type for target_ucontext
We should not use types dependend on host arch for target_ucontext.
This bug is found when run rv32 applications.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230811055438.1945-1-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 6369c8d836c7e19f2ff1860fe2f15b9ced5a5f01
https://github.com/qemu/qemu/commit/6369c8d836c7e19f2ff1860fe2f15b9ced5a5f01
Author: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
target/riscv: support the AIA device emulation with KVM enabled
In this patch, we create the APLIC and IMSIC FDT helper functions and
remove M mode AIA devices when using KVM acceleration.
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230727102439.22554-2-yongxuan.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c9bf654162937d768dd29662b00e4b4af7256e1b
https://github.com/qemu/qemu/commit/c9bf654162937d768dd29662b00e4b4af7256e1b
Author: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/kvm.c
Log Message:
-----------
target/riscv: check the in-kernel irqchip support
We check the in-kernel irqchip support when using KVM acceleration.
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230727102439.22554-3-yongxuan.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: f93580e84e083ed6b57cc648259266f397b649e2
https://github.com/qemu/qemu/commit/f93580e84e083ed6b57cc648259266f397b649e2
Author: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/kvm.c
M target/riscv/kvm_riscv.h
Log Message:
-----------
target/riscv: Create an KVM AIA irqchip
We create a vAIA chip by using the KVM_DEV_TYPE_RISCV_AIA and then set up
the chip with the KVM_DEV_RISCV_AIA_GRP_* APIs.
We also extend KVM accelerator to specify the KVM AIA mode. The "riscv-aia"
parameter is passed along with --accel in QEMU command-line.
1) "riscv-aia=emul": IMSIC is emulated by hypervisor
2) "riscv-aia=hwaccel": use hardware guest IMSIC
3) "riscv-aia=auto": use the hardware guest IMSICs whenever available
otherwise we fallback to software emulation.
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230727102439.22554-4-yongxuan.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 97903d6236e221de3ab48ce037bc52cf5528d3b3
https://github.com/qemu/qemu/commit/97903d6236e221de3ab48ce037bc52cf5528d3b3
Author: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M hw/intc/riscv_aplic.c
M hw/intc/riscv_imsic.c
Log Message:
-----------
target/riscv: update APLIC and IMSIC to support KVM AIA
KVM AIA can't emulate APLIC only. When "aia=aplic" parameter is passed,
APLIC devices is emulated by QEMU. For "aia=aplic-imsic", remove the
mmio operations of APLIC when using KVM AIA and send wired interrupt
signal via KVM_IRQ_LINE API.
After KVM AIA enabled, MSI messages are delivered by KVM_SIGNAL_MSI API
when the IMSICs receive mmio write requests.
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230727102439.22554-5-yongxuan.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: f0a4d58e04b91b2613c9739668c7522916dc6a33
https://github.com/qemu/qemu/commit/f0a4d58e04b91b2613c9739668c7522916dc6a33
Author: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
target/riscv: select KVM AIA in riscv virt machine
Select KVM AIA when the host kernel has in-kernel AIA chip support.
Since KVM AIA only has one APLIC instance, we map the QEMU APLIC
devices to KVM APLIC.
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230727102439.22554-6-yongxuan.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 92b124a388d0380333f5a8cc284d2b47f3e12b16
https://github.com/qemu/qemu/commit/92b124a388d0380333f5a8cc284d2b47f3e12b16
Author: Conor Dooley <conor.dooley@microchip.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv: virt: Fix riscv,pmu DT node path
On a dtb dumped from the virt machine, dt-validate complains:
soc: pmu: {'riscv,event-to-mhpmcounters': [[1, 1, 524281], [2, 2, 524284],
[65561, 65561, 524280], [65563, 65563, 524280], [65569, 65569, 524280]],
'compatible': ['riscv,pmu']} should not be valid under {'type': 'object'}
from schema $id: http://devicetree.org/schemas/simple-bus.yaml#
That's pretty cryptic, but running the dtb back through dtc produces
something a lot more reasonable:
Warning (simple_bus_reg): /soc/pmu: missing or empty reg/ranges property
Moving the riscv,pmu node out of the soc bus solves the problem.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230727-groom-decline-2c57ce42841c@spud>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9fc4cbf9523f62935ffdc5e7db4365b1b4ca906d
https://github.com/qemu/qemu/commit/9fc4cbf9523f62935ffdc5e7db4365b1b4ca906d
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_bits.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Update CSR bits name for svadu extension
The Svadu specification updated the name of the *envcfg bit from
HADE to ADUE.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230816141916.66898-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: eb9b3a8f067d7a420d37292979492aa70dee1997
https://github.com/qemu/qemu/commit/eb9b3a8f067d7a420d37292979492aa70dee1997
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0
In the same emulated RISC-V host, the 'host' KVM CPU takes 4 times
longer to boot than the 'rv64' KVM CPU.
The reason is an unintended behavior of riscv_cpu_satp_mode_finalize()
when satp_mode.supported = 0, i.e. when cpu_init() does not set
satp_mode_max_supported(). satp_mode_max_from_map(map) does:
31 - __builtin_clz(map)
This means that, if satp_mode.supported = 0, satp_mode_supported_max
wil be '31 - 32'. But this is C, so satp_mode_supported_max will gladly
set it to UINT_MAX (4294967295). After that, if the user didn't set a
satp_mode, set_satp_mode_default_map(cpu) will make
cfg.satp_mode.map = cfg.satp_mode.supported
So satp_mode.map = 0. And then satp_mode_map_max will be set to
satp_mode_max_from_map(cpu->cfg.satp_mode.map), i.e. also UINT_MAX. The
guard "satp_mode_map_max > satp_mode_supported_max" doesn't protect us
here since both are UINT_MAX.
And finally we have 2 loops:
for (int i = satp_mode_map_max - 1; i >= 0; --i) {
Which are, in fact, 2 loops from UINT_MAX -1 to -1. This is where the
extra delay when booting the 'host' CPU is coming from.
Commit 43d1de32f8 already set a precedence for satp_mode.supported = 0
in a different manner. We're doing the same here. If supported == 0,
interpret as 'the CPU wants the OS to handle satp mode alone' and skip
satp_mode_finalize().
We'll also put a guard in satp_mode_max_from_map() to assert out if map
is 0 since the function is not ready to deal with it.
Cc: Alexandre Ghiti <alexghiti@rivosinc.com>
Fixes: 6f23aaeb9b ("riscv: Allow user to set the satp mode")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230817152903.694926-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c7c88f6ce85acc5b7a8f574325521828fdd7128a
https://github.com/qemu/qemu/commit/c7c88f6ce85acc5b7a8f574325521828fdd7128a
Author: Vineet Gupta <vineetg@rivosinc.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
riscv: zicond: make non-experimental
zicond is now codegen supported in both llvm and gcc.
This change allows seamless enabling/testing of zicond in downstream
projects. e.g. currently riscv-gnu-toolchain parses elf attributes
to create a cmdline for qemu but fails short of enabling it because of
the "x-" prefix.
Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
Message-ID: <20230808181715.436395-1-vineetg@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 385c3fecb2f9aa6732d3484afdd9e40738b1c18a
https://github.com/qemu/qemu/commit/385c3fecb2f9aa6732d3484afdd9e40738b1c18a
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt.c: fix non-KVM --enable-debug build
A build with --enable-debug and without KVM will fail as follows:
/usr/bin/ld: libqemu-riscv64-softmmu.fa.p/hw_riscv_virt.c.o: in function
`virt_machine_init':
./qemu/build/../hw/riscv/virt.c:1465: undefined reference to
`kvm_riscv_aia_create'
This happens because the code block with "if virt_use_kvm_aia(s)" isn't
being ignored by the debug build, resulting in an undefined reference to
a KVM only function.
Add a 'kvm_enabled()' conditional together with virt_use_kvm_aia() will
make the compiler crop the kvm_riscv_aia_create() call entirely from a
non-KVM build. Note that adding the 'kvm_enabled()' conditional inside
virt_use_kvm_aia() won't fix the build because this function would need
to be inlined multiple times to make the compiler zero out the entire
block.
While we're at it, use kvm_enabled() in all instances where
virt_use_kvm_aia() is checked to allow the compiler to elide these other
kvm-only instances as well.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Fixes: dbdb99948e ("target/riscv: select KVM AIA in riscv virt machine")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230830133503.711138-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 47052796b7509c4b34f30de39b2214d3ae7c9308
https://github.com/qemu/qemu/commit/47052796b7509c4b34f30de39b2214d3ae7c9308
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M hw/intc/riscv_aplic.c
M target/riscv/kvm.c
M target/riscv/kvm_riscv.h
Log Message:
-----------
hw/intc/riscv_aplic.c fix non-KVM --enable-debug build
Commit 6df0b37e2ab breaks a --enable-debug build in a non-KVM
environment with the following error:
/usr/bin/ld: libqemu-riscv64-softmmu.fa.p/hw_intc_riscv_aplic.c.o: in function
`riscv_kvm_aplic_request':
./qemu/build/../hw/intc/riscv_aplic.c:486: undefined reference to `kvm_set_irq'
collect2: error: ld returned 1 exit status
This happens because the debug build will poke into the
'if (is_kvm_aia(aplic->msimode))' block and fail to find a reference to
the KVM only function riscv_kvm_aplic_request().
There are multiple solutions to fix this. We'll go with the same
solution from the previous patch, i.e. add a kvm_enabled() conditional
to filter out the block. But there's a catch: riscv_kvm_aplic_request()
is a local function that would end up being used if the compiler crops
the block, and this won't work. Quoting Richard Henderson's explanation
in [1]:
"(...) the compiler won't eliminate entire unused functions with -O0"
We'll solve it by moving riscv_kvm_aplic_request() to kvm.c and add its
declaration in kvm_riscv.h, where all other KVM specific public
functions are already declared. Other archs handles KVM specific code in
this manner and we expect to do the same from now on.
[1]
https://lore.kernel.org/qemu-riscv/d2f1ad02-eb03-138f-9d08-db676deeed05@linaro.org/
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230830133503.711138-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 82f37e1d7e159e62234b75ae309b1aca03911125
https://github.com/qemu/qemu/commit/82f37e1d7e159e62234b75ae309b1aca03911125
Author: Robbin Ehn <rehn@rivosinc.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M linux-user/syscall.c
Log Message:
-----------
linux-user/riscv: Add new extensions to hwprobe
This patch adds the new extensions in
linux 6.5 to the hwprobe syscall.
And fixes RVC check to OR with correct value.
The previous variable contains 0 therefore it
did work.
Signed-off-by: Robbin Ehn <rehn@rivosinc.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <bc82203b72d7efb30f1b4a8f9eb3d94699799dc8.camel@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 38be208bfb3bf95c417be14fbda54db6a35e3f83
https://github.com/qemu/qemu/commit/38be208bfb3bf95c417be14fbda54db6a35e3f83
Author: Ard Biesheuvel <ardb@kernel.org>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/crypto_helper.c
Log Message:
-----------
target/riscv: Use accelerated helper for AES64KS1I
Use the accelerated SubBytes/ShiftRows/AddRoundKey AES helper to
implement the first half of the key schedule derivation. This does not
actually involve shifting rows, so clone the same value into all four
columns of the AES vector to counter that operation.
Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Philippe Mathieu-Daudé <philmd@linaro.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230831154118.138727-1-ardb@kernel.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 88cd506a60e7b1a183a1a919b587d5e84b01b9ca
https://github.com/qemu/qemu/commit/88cd506a60e7b1a183a1a919b587d5e84b01b9ca
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/debug.c
M target/riscv/debug.h
Log Message:
-----------
target/riscv: Allocate itrigger timers only once
riscv_trigger_init() had been called on reset events that can happen
several times for a CPU and it allocated timers for itrigger. If old
timers were present, they were simply overwritten by the new timers,
resulting in a memory leak.
Divide riscv_trigger_init() into two functions, namely
riscv_trigger_realize() and riscv_trigger_reset() and call them in
appropriate timing. The timer allocation will happen only once for a
CPU in riscv_trigger_realize().
Fixes: 5a4ae64cac ("target/riscv: Add itrigger support when icount is enabled")
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230818034059.9146-1-akihiko.odaki@daynix.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 35067ad0c012cd1703654e95bed2540d00e61c79
https://github.com/qemu/qemu/commit/35067ad0c012cd1703654e95bed2540d00e61c79
Author: Leon Schuermann <leons@opentitan.org>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/pmp.c
Log Message:
-----------
target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes
When the rule-lock bypass (RLB) bit is set in the mseccfg CSR, the PMP
configuration lock bits must not apply. While this behavior is
implemented for the pmpcfgX CSRs, this bit is not respected for
changes to the pmpaddrX CSRs. This patch ensures that pmpaddrX CSR
writes work even on locked regions when the global rule-lock bypass is
enabled.
Signed-off-by: Leon Schuermann <leons@opentitan.org>
Reviewed-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230829215046.1430463-1-leon@is.currently.online>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9141c3bcc21dc543da2045b3e798be800ed3eef3
https://github.com/qemu/qemu/commit/9141c3bcc21dc543da2045b3e798be800ed3eef3
Author: Tommy Wu <tommy.wu@sifive.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Align the AIA model to v1.0 ratified spec
According to the new spec, when vsiselect has a reserved value, attempts
from M-mode or HS-mode to access vsireg, or from VS-mode to access
sireg, should preferably raise an illegal instruction exception.
Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-ID: <20230816061647.600672-1-tommy.wu@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: f289a1e70c6b03caed98f7a550cb5d74a3225c8b
https://github.com/qemu/qemu/commit/f289a1e70c6b03caed98f7a550cb5d74a3225c8b
Author: Nikita Shubin <n.shubin@yadro.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: don't read CSR in riscv_csrrw_do64
As per ISA:
"For CSRRWI, if rd=x0, then the instruction shall not read the CSR and
shall not cause any of the side effects that might occur on a CSR read."
trans_csrrwi() and trans_csrrw() call do_csrw() if rd=x0, do_csrw() calls
riscv_csrrw_do64(), via helper_csrw() passing NULL as *ret_value.
Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230808090914.17634-1-nikita.shubin@maquefel.me>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 786d55011f39f27c7de9e8d895a401a865bd2a99
https://github.com/qemu/qemu/commit/786d55011f39f27c7de9e8d895a401a865bd2a99
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]
We'll add a new CPU type that will enable a considerable amount of
extensions. To make it easier for us we'll do a few cleanups in our
existing riscv_cpu_extensions[] array.
Start by splitting all CPU non-boolean options from it. Create a new
riscv_cpu_options[] array for them. Add all these properties in
riscv_cpu_add_user_properties() as it is already being done today.
'mmu' and 'pmp' aren't really extensions in the usual way we think about
RISC-V extensions. These are closer to CPU features/options, so move
both to riscv_cpu_options[] too. In the near future we'll need to match
all extensions with all entries in isa_edata_arr[], and so it happens
that both 'mmu' and 'pmp' do not have a riscv,isa string (thus, no priv
spec version restriction). This further emphasizes the point that these
are more a CPU option than an extension.
No functional changes made.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230901194627.1214811-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 34851d4d5d2f9bee7faffa31f4c352efbb3c2921
https://github.com/qemu/qemu/commit/34851d4d5d2f9bee7faffa31f4c352efbb3c2921
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: skip 'bool' check when filtering KVM props
After the introduction of riscv_cpu_options[] all properties in
riscv_cpu_extensions[] are booleans. This check is now obsolete.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230901194627.1214811-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 425d2caf4613c9a215f661e96500e89202ca54bf
https://github.com/qemu/qemu/commit/425d2caf4613c9a215f661e96500e89202ca54bf
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: split kvm prop handling to its own helper
Future patches will split the existing Property arrays even further, and
the existing code in riscv_cpu_add_user_properties() will start to scale
bad with it because it's dealing with KVM constraints mixed in with TCG
constraints. We're going to pay a high price to share a couple of common
lines of code between the two.
Create a new riscv_cpu_add_kvm_properties() that will be forked from
riscv_cpu_add_user_properties() if we're running KVM. The helper
includes all properties that a KVM CPU will add. The rest of
riscv_cpu_add_user_properties() body will then be relieved from having
to deal with KVM constraints.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230901194627.1214811-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 3ed0b541974114c66ff8b12d1a698c2b19df16f2
https://github.com/qemu/qemu/commit/3ed0b541974114c66ff8b12d1a698c2b19df16f2
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: add DEFINE_PROP_END_OF_LIST() to riscv_cpu_options[]
Add DEFINE_PROP_END_OF_LIST() and eliminate the ARRAY_SIZE() usage when
iterating in the riscv_cpu_options[] array, making it similar to what
we already do when working with riscv_cpu_extensions[].
We also have a more sophisticated motivation behind this change. In the
future we might need to export riscv_cpu_options[] to other files, and
ARRAY_LIST() doesn't work properly in that case because the array size
isn't exposed to the header file. Here's a future sight of what we would
deal with:
./target/riscv/kvm.c:1057:5: error: nested extern declaration of
'riscv_cpu_add_misa_properties' [-Werror=nested-externs]
n file included from ../target/riscv/kvm.c:19:
home/danielhb/work/qemu/include/qemu/osdep.h:473:31: error: invalid application
of 'sizeof' to incomplete type 'const RISCVCPUMultiExtConfig[]'
473 | #define ARRAY_SIZE(x) ((sizeof(x) / sizeof((x)[0])) + \
| ^
./target/riscv/kvm.c:1047:29: note: in expansion of macro 'ARRAY_SIZE'
1047 | for (int i = 0; i < ARRAY_SIZE(_array); i++) { \
| ^~~~~~~~~~
./target/riscv/kvm.c:1059:5: note: in expansion of macro
'ADD_UNAVAIL_KVM_PROP_ARRAY'
1059 | ADD_UNAVAIL_KVM_PROP_ARRAY(obj, riscv_cpu_extensions);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
home/danielhb/work/qemu/include/qemu/osdep.h:473:31: error: invalid application
of 'sizeof' to incomplete type 'const RISCVCPUMultiExtConfig[]'
473 | #define ARRAY_SIZE(x) ((sizeof(x) / sizeof((x)[0])) + \
| ^
./target/riscv/kvm.c:1047:29: note: in expansion of macro 'ARRAY_SIZE'
1047 | for (int i = 0; i < ARRAY_SIZE(_array); i++) { \
Homogenize the present and change the future by using
DEFINE_PROP_END_OF_LIST() in riscv_cpu_options[].
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230901194627.1214811-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4a56b260b99039b7195e0ef8d23d2d0623f57693
https://github.com/qemu/qemu/commit/4a56b260b99039b7195e0ef8d23d2d0623f57693
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[]
Create a new riscv_cpu_experimental_exts[] to store the non-ratified
extensions properties. Once they are ratified we'll move them back to
riscv_cpu_extensions[].
riscv_cpu_add_user_properties() and riscv_cpu_add_kvm_properties() are
changed to keep adding non-ratified properties to users.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230901194627.1214811-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1c69f856975185255e0058bbad946d7058f616c1
https://github.com/qemu/qemu/commit/1c69f856975185255e0058bbad946d7058f616c1
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[]
Our goal is to make riscv_cpu_extensions[] hold only ratified,
non-vendor extensions.
Create a new riscv_cpu_vendor_exts[] array for them, changing
riscv_cpu_add_user_properties() and riscv_cpu_add_kvm_properties()
accordingly.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230901194627.1214811-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4bbe8c9ed91e0f184daf11cd14bf38f720c121a3
https://github.com/qemu/qemu/commit/4bbe8c9ed91e0f184daf11cd14bf38f720c121a3
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: add riscv_cpu_add_qdev_prop_array()
The code inside riscv_cpu_add_user_properties() became quite repetitive
after recent changes. Add a helper to hide the repetition away.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230901194627.1214811-8-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 57fdd04e989ea8e3eeb265cd2e5475be6ba1dcb0
https://github.com/qemu/qemu/commit/57fdd04e989ea8e3eeb265cd2e5475be6ba1dcb0
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: add riscv_cpu_add_kvm_unavail_prop_array()
Use a helper in riscv_cpu_add_kvm_properties() to eliminate some of its
code repetition.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230901194627.1214811-9-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1d49b52a9bfa2ae6db456ffa403768810bcdaf11
https://github.com/qemu/qemu/commit/1d49b52a9bfa2ae6db456ffa403768810bcdaf11
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: limit cfg->vext_spec log message
Inside riscv_cpu_validate_v() we're always throwing a log message if the
user didn't set a vector version via 'vext_spec'.
We're going to include one case with the 'max' CPU where env->vext_ver
will be set in the cpu_init(). But that alone will not stop the "vector
version is not specified" message from appearing. The usefulness of this
log message is debatable for the generic CPUs, but for a 'max' CPU type,
where we are supposed to deliver a CPU model with all features possible,
it's strange to force users to set 'vext_spec' to get rid of this
message.
Change riscv_cpu_validate_v() to not throw this log message if
env->vext_ver is already set.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230901194627.1214811-10-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: d99e2a060c4d71485e1721ecd232d1a5324e49ca
https://github.com/qemu/qemu/commit/d99e2a060c4d71485e1721ecd232d1a5324e49ca
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/cpu-qom.h
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: add 'max' CPU type
The 'max' CPU type is used by tooling to determine what's the most
capable CPU a current QEMU version implements. Other archs such as ARM
implements this type. Let's add it to RISC-V.
What we consider "most capable CPU" in this context are related to
ratified, non-vendor extensions. This means that we want the 'max' CPU
to enable all (possible) ratified extensions by default. The reasoning
behind this design is (1) vendor extensions can conflict with each other
and we won't play favorities deciding which one is default or not and
(2) non-ratified extensions are always prone to changes, not being
stable enough to be enabled by default.
All this said, we're still not able to enable all ratified extensions
due to conflicts between them. Zfinx and all its dependencies aren't
enabled because of a conflict with RVF. zce, zcmp and zcmt are also
disabled due to RVD conflicts. When running with 64 bits we're also
disabling zcf.
MISA bits RVG, RVJ and RVV are also being set manually since they're
default disabled.
This is the resulting 'riscv,isa' DT for this new CPU:
rv64imafdcvh_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zfa_
zfh_zfhmin_zca_zcb_zcd_zba_zbb_zbc_zbkb_zbkc_zbkx_zbs_zk_zkn_zknd_
zkne_zknh_zkr_zks_zksed_zksh_zkt_zve32f_zve64f_zve64d_
smstateen_sscofpmf_sstc_svadu_svinval_svnapot_svpbmt
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230901194627.1214811-11-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 465d92514579639f681f135514a7a22d65344f25
https://github.com/qemu/qemu/commit/465d92514579639f681f135514a7a22d65344f25
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M tests/avocado/tuxrun_baselines.py
Log Message:
-----------
avocado, risc-v: add tuxboot tests for 'max' CPU
Add smoke tests to ensure that we'll not break the 'max' CPU type when
adding new frozen/ratified RISC-V extensions.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230901194627.1214811-12-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4a9422b284043089aa495ae60155e1e6e6a2d399
https://github.com/qemu/qemu/commit/4a9422b284043089aa495ae60155e1e6e6a2d399
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M docs/about/deprecated.rst
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: deprecate the 'any' CPU type
The 'any' CPU type was introduced in commit dc5bd18fa5725 ("RISC-V CPU
Core Definition"), being around since the beginning. It's not an easy
CPU to use: it's undocumented and its name doesn't tell users much about
what the CPU is supposed to bring. 'git log' doesn't help us either in
knowing what was the original design of this CPU type.
The closest we have is a comment from Alistair [1] where he recalls from
memory that the 'any' CPU is supposed to behave like the newly added
'max' CPU. He also suggested that the 'any' CPU should be removed.
The default CPUs are rv32 and rv64, so removing the 'any' CPU will have
impact only on users that might have a script that uses '-cpu any'.
And those users are better off using the default CPUs or the new 'max'
CPU.
We would love to just remove the code and be done with it, but one does
not simply remove a feature in QEMU. We'll put the CPU in quarantine
first, letting users know that we have the intent of removing it in the
future.
[1] https://lists.gnu.org/archive/html/qemu-devel/2023-07/msg02891.html
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230901194627.1214811-13-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 2cbe70aeeda73faf4e53c12259724e8ffbcd9756
https://github.com/qemu/qemu/commit/2cbe70aeeda73faf4e53c12259724e8ffbcd9756
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled
We'll have future usage for a function where, given an offset of the
struct RISCVCPUConfig, the flag is updated to a certain val.
Change all existing callers to use edata->ext_enable_offset instead of
'edata'.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230901194627.1214811-14-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c4a1fde0312e835fe158f5b166ce1cb8b90e4476
https://github.com/qemu/qemu/commit/c4a1fde0312e835fe158f5b166ce1cb8b90e4476
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/kvm.c
Log Message:
-----------
target/riscv: make CPUCFG() macro public
The RISC-V KVM driver uses a CPUCFG() macro that calculates the offset
of a certain field in the struct RISCVCPUConfig. We're going to use this
macro in target/riscv/cpu.c as well in the next patches. Make it public.
Rename it to CPU_CFG_OFFSET() for more clarity while we're at it.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230901194627.1214811-15-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e8fe93703dc9879b22c902470f60349d53569b1e
https://github.com/qemu/qemu/commit/e8fe93703dc9879b22c902470f60349d53569b1e
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update()
During realize() time we're activating a lot of extensions based on some
criteria, e.g.:
if (cpu->cfg.ext_zk) {
cpu->cfg.ext_zkn = true;
cpu->cfg.ext_zkr = true;
cpu->cfg.ext_zkt = true;
}
This practice resulted in at least one case where we ended up enabling
something we shouldn't: RVC enabling zca/zcd/zcf when using a CPU that
has priv_spec older than 1.12.0.
We're also not considering user choice. There's no way of doing it now
but this is about to change in the next few patches.
cpu_cfg_ext_auto_update() will check for priv version mismatches before
enabling extensions. If we have a mismatch between the current priv
version and the extension we want to enable, do not enable it. In the
near future, this same function will also consider user choice when
deciding if we're going to enable/disable an extension or not.
For now let's use it to handle zca/zcd/zcf enablement if RVC is enabled.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230901194627.1214811-16-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e7df41a33d8d581d7d1caf9b6492ef2bd599036f
https://github.com/qemu/qemu/commit/e7df41a33d8d581d7d1caf9b6492ef2bd599036f
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize()
Let's change the other instances in realize() where we're enabling an
extension based on a certain criteria (e.g. it's a dependency of another
extension).
We're leaving icsr and ifencei being enabled during RVG for later -
we'll want to error out in that case. Every other extension enablement
during realize is now done via cpu_cfg_ext_auto_update().
The end goal is that only cpu init() functions will handle extension
flags directly via "cpu->cfg.ext_N = true|false".
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230901194627.1214811-17-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 29a3f5b33f5f694b50a962924b7599728aede471
https://github.com/qemu/qemu/commit/29a3f5b33f5f694b50a962924b7599728aede471
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig
If we want to make better decisions when auto-enabling extensions during
realize() we need a way to tell if an user set an extension manually.
The RISC-V KVM driver has its own solution via a KVMCPUConfig struct
that has an 'user_set' flag that is set during the Property set()
callback. The set() callback also does init() time validations based on
the current KVM driver capabilities.
For TCG we would want a 'user_set' mechanic too, but we would look
ad-hoc via cpu_cfg_ext_auto_update() if a certain extension was user set
or not. If we copy what was made in the KVM side we would look for
'user_set' for one into 60+ extension structs spreaded in 3 arrays
(riscv_cpu_extensions, riscv_cpu_experimental_exts,
riscv_cpu_vendor_exts).
We'll still need an extension struct but we won't be using the
'user_set' flag:
- 'RISCVCPUMultiExtConfig' will be our specialized structure, similar to what
we're already doing with the MISA extensions in 'RISCVCPUMisaExtConfig'.
DEFINE_PROP_BOOL() for all 3 extensions arrays were replaced by
MULTI_EXT_CFG_BOOL(), a macro that will init our specialized struct;
- the 'multi_ext_user_opts' hash will be used to store the offset of each
extension that the user set via the set() callback, cpu_set_multi_ext_cfg().
For now we're just initializing and populating it - next patch will use
it to determine if a certain extension was user set;
- cpu_add_multi_ext_prop() is a new helper that will replace the
qdev_property_add_static() calls that our macros are doing to populate
user properties. The macro was renamed to ADD_CPU_MULTIEXT_PROPS_ARRAY()
for clarity. Note that the non-extension properties in
riscv_cpu_options[] still need to be declared via qdev().
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230901194627.1214811-18-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c41554fbfb6db06e7b57b6b125439c017958b3e4
https://github.com/qemu/qemu/commit/c41554fbfb6db06e7b57b6b125439c017958b3e4
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions()
Before adding support to detect if an extension was user set we need to
handle how we're enabling extensions in riscv_init_max_cpu_extensions().
object_property_set_bool() calls the set() callback for the property,
and we're going to use this callback to set the 'multi_ext_user_opts'
hash.
This means that, as is today, all extensions we're setting for the 'max'
CPU will be seen as user set in the future. Let's change set_bool() to
isa_ext_update_enabled() that will just enable/disable the flag on a
certain offset.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230901194627.1214811-19-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 5720e443a91c0aec3277882168d945736e139b03
https://github.com/qemu/qemu/commit/5720e443a91c0aec3277882168d945736e139b03
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update()
Add a new cpu_cfg_ext_is_user_set() helper to check if an extension was
set by the user in the command line. Use it inside
cpu_cfg_ext_auto_update() to verify if the user set a certain extension
and, if that's the case, do not change its value.
This will make us honor user choice instead of overwriting the values.
Users will then be informed whether they're using an incompatible set of
extensions instead of QEMU setting a magic value that works.
The reason why we're not implementing user choice for MISA extensions
right now is because, today, we do not silently change any MISA bit
during realize() time (we do warn when enabling bits if RVG is enabled).
We do that - a lot - with multi-letter extensions though, so we're
handling the most immediate concern first.
After this patch, we'll now error out if the user explicitly set 'zce' to true
and 'zca' to false:
$ ./build/qemu-system-riscv64 -M virt -cpu rv64,zce=true,zca=false -nographic
qemu-system-riscv64: Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca extension
This didn't happen before because we were enabling 'zca' if 'zce' was enabled
regardless if the user set 'zca' to false.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230901194627.1214811-20-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 69749970db9f1b05c8cd77a7bbb45e4e156f7d33
https://github.com/qemu/qemu/commit/69749970db9f1b05c8cd77a7bbb45e4e156f7d33
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: consider user option with RVG
Enabling RVG will enable a set of extensions that we're not checking if
the user was okay enabling or not. And in this case we want to error
out, instead of ignoring, otherwise we will be inconsistent enabling RVG
without all its extensions.
After this patch, disabling ifencei or icsr while enabling RVG will
result in error:
$ ./build/qemu-system-riscv64 -M virt -cpu rv64,g=true,Zifencei=false
--nographic
qemu-system-riscv64: RVG requires Zifencei but user set Zifencei to false
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230901194627.1214811-21-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: fa6be20a1f4a1070e44ee30b609ce4cbf659236e
https://github.com/qemu/qemu/commit/fa6be20a1f4a1070e44ee30b609ce4cbf659236e
Author: Andrew Melnychenko <andrew@daynix.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M hw/net/e1000e_core.c
M hw/net/igb_core.c
M hw/net/virtio-net.c
M hw/net/vmxnet3.c
M include/net/net.h
M net/net.c
M net/tap-bsd.c
M net/tap-linux.c
M net/tap-linux.h
M net/tap-solaris.c
M net/tap-stub.c
M net/tap-win32.c
M net/tap.c
M net/tap_int.h
Log Message:
-----------
tap: Add USO support to tap device.
Passing additional parameters (USOv4 and USOv6 offloads) when
setting TAP offloads
Signed-off-by: Yuri Benditovich <yuri.benditovich@daynix.com>
Signed-off-by: Andrew Melnychenko <andrew@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Commit: 49498bf27153b2446b1b3620a193a61888d2e2d5
https://github.com/qemu/qemu/commit/49498bf27153b2446b1b3620a193a61888d2e2d5
Author: Yuri Benditovich <yuri.benditovich@daynix.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M include/net/net.h
M net/net.c
M net/tap-bsd.c
M net/tap-linux.c
M net/tap-solaris.c
M net/tap-stub.c
M net/tap.c
M net/tap_int.h
Log Message:
-----------
tap: Add check for USO features
Tap indicates support for USO features according to
capabilities of current kernel module.
Signed-off-by: Yuri Benditovich <yuri.benditovich@daynix.com>
Signed-off-by: Andrew Melnychecnko <andrew@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Commit: 1220bffc38dc152e7de0f9d3c7d6bad1af42bdfc
https://github.com/qemu/qemu/commit/1220bffc38dc152e7de0f9d3c7d6bad1af42bdfc
Author: Andrew Melnychenko <andrew@daynix.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M hw/net/vhost_net.c
M net/vhost-vdpa.c
Log Message:
-----------
virtio-net: Add USO flags to vhost support.
New features are subject to check with vhost-user and vdpa.
Signed-off-by: Yuri Benditovich <yuri.benditovich@daynix.com>
Signed-off-by: Andrew Melnychenko <andrew@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Commit: cefdbbdd7dc087689f1ad6287393e308d475e1a5
https://github.com/qemu/qemu/commit/cefdbbdd7dc087689f1ad6287393e308d475e1a5
Author: Yuri Benditovich <yuri.benditovich@daynix.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M hw/core/machine.c
M hw/net/virtio-net.c
Log Message:
-----------
virtio-net: Add support for USO features
USO features of virtio-net device depend on kernel ability
to support them, for backward compatibility by default the
features are disabled on 8.0 and earlier.
Signed-off-by: Yuri Benditovich <yuri.benditovich@daynix.com>
Signed-off-by: Andrew Melnychecnko <andrew@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Commit: 3578f16739a1b6038b087ef65e1373e8bb630482
https://github.com/qemu/qemu/commit/3578f16739a1b6038b087ef65e1373e8bb630482
Author: Tomasz Dzieciol <t.dzieciol@partner.samsung.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M hw/net/igb_core.c
Log Message:
-----------
igb: remove TCP ACK detection
TCP ACK detection is no longer present in igb.
Signed-off-by: Tomasz Dzieciol <t.dzieciol@partner.samsung.com>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Tested-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Commit: 3339d3894e194f7a294428ee3868faa7857f5a6b
https://github.com/qemu/qemu/commit/3339d3894e194f7a294428ee3868faa7857f5a6b
Author: Tomasz Dzieciol <t.dzieciol@partner.samsung.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M hw/net/e1000e_core.c
M hw/net/igb_core.c
Log Message:
-----------
igb: rename E1000E_RingInfo_st
Rename E1000E_RingInfo_st and E1000E_RingInfo according to qemu typdefs guide.
Signed-off-by: Tomasz Dzieciol <t.dzieciol@partner.samsung.com>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Tested-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Commit: 791542f34f9d9e521ddab5f1c3c751d156f400c9
https://github.com/qemu/qemu/commit/791542f34f9d9e521ddab5f1c3c751d156f400c9
Author: Tomasz Dzieciol <t.dzieciol@partner.samsung.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M hw/net/igb_core.c
M hw/net/igb_regs.h
M hw/net/trace-events
Log Message:
-----------
igb: RX descriptors guest writting refactoring
Refactoring is done in preparation for support of multiple advanced
descriptors RX modes, especially packet-split modes.
Signed-off-by: Tomasz Dzieciol <t.dzieciol@partner.samsung.com>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Tested-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Commit: 7a4d0853ecbb7ec7f2346841893b9764d7219494
https://github.com/qemu/qemu/commit/7a4d0853ecbb7ec7f2346841893b9764d7219494
Author: Tomasz Dzieciol <t.dzieciol@partner.samsung.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M hw/net/e1000e_core.c
M hw/net/igb_core.c
M tests/qtest/libqos/igb.c
Log Message:
-----------
igb: RX payload guest writting refactoring
Refactoring is done in preparation for support of multiple advanced
descriptors RX modes, especially packet-split modes.
Signed-off-by: Tomasz Dzieciol <t.dzieciol@partner.samsung.com>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Tested-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Commit: 8548158bda7431b15d0a3db7392fd9166b27a6c8
https://github.com/qemu/qemu/commit/8548158bda7431b15d0a3db7392fd9166b27a6c8
Author: Tomasz Dzieciol <t.dzieciol@partner.samsung.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M hw/net/igb_core.c
M hw/net/igb_regs.h
Log Message:
-----------
igb: add IPv6 extended headers traffic detection
Signed-off-by: Tomasz Dzieciol <t.dzieciol@partner.samsung.com>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Tested-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Commit: da5fbe79732c946a92e0aba322e9ec3929e4d042
https://github.com/qemu/qemu/commit/da5fbe79732c946a92e0aba322e9ec3929e4d042
Author: Tomasz Dzieciol <t.dzieciol@partner.samsung.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M hw/net/igb_core.c
M hw/net/igb_regs.h
M hw/net/trace-events
Log Message:
-----------
igb: packet-split descriptors support
Packet-split descriptors are used by Linux VF driver for MTU values from 2048
Signed-off-by: Tomasz Dzieciol <t.dzieciol@partner.samsung.com>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Tested-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Commit: 3a4761087f27b2a3d477d7b162aace32940c8b45
https://github.com/qemu/qemu/commit/3a4761087f27b2a3d477d7b162aace32940c8b45
Author: Tomasz Dzieciol <t.dzieciol@partner.samsung.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M hw/net/e1000e_core.c
Log Message:
-----------
e1000e: rename e1000e_ba_state and e1000e_write_hdr_to_rx_buffers
Rename e1000e_ba_state according and e1000e_write_hdr_to_rx_buffers for
consistency with IGB.
Signed-off-by: Tomasz Dzieciol <t.dzieciol@partner.samsung.com>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Tested-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Commit: 34b2166cbd38ca314fe3c9843808786b5bfa849f
https://github.com/qemu/qemu/commit/34b2166cbd38ca314fe3c9843808786b5bfa849f
Author: Ilya Maximets <i.maximets@ovn.org>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M MAINTAINERS
M hmp-commands.hx
M meson.build
M meson_options.txt
A net/af-xdp.c
M net/clients.h
M net/meson.build
M net/net.c
M qapi/net.json
M qemu-options.hx
M scripts/ci/org.centos/stream/8/x86_64/configure
M scripts/meson-buildoptions.sh
M tests/docker/dockerfiles/debian-amd64.docker
Log Message:
-----------
net: add initial support for AF_XDP network backend
AF_XDP is a network socket family that allows communication directly
with the network device driver in the kernel, bypassing most or all
of the kernel networking stack. In the essence, the technology is
pretty similar to netmap. But, unlike netmap, AF_XDP is Linux-native
and works with any network interfaces without driver modifications.
Unlike vhost-based backends (kernel, user, vdpa), AF_XDP doesn't
require access to character devices or unix sockets. Only access to
the network interface itself is necessary.
This patch implements a network backend that communicates with the
kernel by creating an AF_XDP socket. A chunk of userspace memory
is shared between QEMU and the host kernel. 4 ring buffers (Tx, Rx,
Fill and Completion) are placed in that memory along with a pool of
memory buffers for the packet data. Data transmission is done by
allocating one of the buffers, copying packet data into it and
placing the pointer into Tx ring. After transmission, device will
return the buffer via Completion ring. On Rx, device will take
a buffer form a pre-populated Fill ring, write the packet data into
it and place the buffer into Rx ring.
AF_XDP network backend takes on the communication with the host
kernel and the network interface and forwards packets to/from the
peer device in QEMU.
Usage example:
-device virtio-net-pci,netdev=guest1,mac=00:16:35:AF:AA:5C
-netdev af-xdp,ifname=ens6f1np1,id=guest1,mode=native,queues=1
XDP program bridges the socket with a network interface. It can be
attached to the interface in 2 different modes:
1. skb - this mode should work for any interface and doesn't require
driver support. With a caveat of lower performance.
2. native - this does require support from the driver and allows to
bypass skb allocation in the kernel and potentially use
zero-copy while getting packets in/out userspace.
By default, QEMU will try to use native mode and fall back to skb.
Mode can be forced via 'mode' option. To force 'copy' even in native
mode, use 'force-copy=on' option. This might be useful if there is
some issue with the driver.
Option 'queues=N' allows to specify how many device queues should
be open. Note that all the queues that are not open are still
functional and can receive traffic, but it will not be delivered to
QEMU. So, the number of device queues should generally match the
QEMU configuration, unless the device is shared with something
else and the traffic re-direction to appropriate queues is correctly
configured on a device level (e.g. with ethtool -N).
'start-queue=M' option can be used to specify from which queue id
QEMU should start configuring 'N' queues. It might also be necessary
to use this option with certain NICs, e.g. MLX5 NICs. See the docs
for examples.
In a general case QEMU will need CAP_NET_ADMIN and CAP_SYS_ADMIN
or CAP_BPF capabilities in order to load default XSK/XDP programs to
the network interface and configure BPF maps. It is possible, however,
to run with no capabilities. For that to work, an external process
with enough capabilities will need to pre-load default XSK program,
create AF_XDP sockets and pass their file descriptors to QEMU process
on startup via 'sock-fds' option. Network backend will need to be
configured with 'inhibit=on' to avoid loading of the program.
QEMU will need 32 MB of locked memory (RLIMIT_MEMLOCK) per queue
or CAP_IPC_LOCK.
There are few performance challenges with the current network backends.
First is that they do not support IO threads. This means that data
path is handled by the main thread in QEMU and may slow down other
work or may be slowed down by some other work. This also means that
taking advantage of multi-queue is generally not possible today.
Another thing is that data path is going through the device emulation
code, which is not really optimized for performance. The fastest
"frontend" device is virtio-net. But it's not optimized for heavy
traffic either, because it expects such use-cases to be handled via
some implementation of vhost (user, kernel, vdpa). In practice, we
have virtio notifications and rcu lock/unlock on a per-packet basis
and not very efficient accesses to the guest memory. Communication
channels between backend and frontend devices do not allow passing
more than one packet at a time as well.
Some of these challenges can be avoided in the future by adding better
batching into device emulation or by implementing vhost-af-xdp variant.
There are also a few kernel limitations. AF_XDP sockets do not
support any kinds of checksum or segmentation offloading. Buffers
are limited to a page size (4K), i.e. MTU is limited. Multi-buffer
support implementation for AF_XDP is in progress, but not ready yet.
Also, transmission in all non-zero-copy modes is synchronous, i.e.
done in a syscall. That doesn't allow high packet rates on virtual
interfaces.
However, keeping in mind all of these challenges, current implementation
of the AF_XDP backend shows a decent performance while running on top
of a physical NIC with zero-copy support.
Test setup:
2 VMs running on 2 physical hosts connected via ConnectX6-Dx card.
Network backend is configured to open the NIC directly in native mode.
The driver supports zero-copy. NIC is configured to use 1 queue.
Inside a VM - iperf3 for basic TCP performance testing and dpdk-testpmd
for PPS testing.
iperf3 result:
TCP stream : 19.1 Gbps
dpdk-testpmd (single queue, single CPU core, 64 B packets) results:
Tx only : 3.4 Mpps
Rx only : 2.0 Mpps
L2 FWD Loopback : 1.5 Mpps
In skb mode the same setup shows much lower performance, similar to
the setup where pair of physical NICs is replaced with veth pair:
iperf3 result:
TCP stream : 9 Gbps
dpdk-testpmd (single queue, single CPU core, 64 B packets) results:
Tx only : 1.2 Mpps
Rx only : 1.0 Mpps
L2 FWD Loopback : 0.7 Mpps
Results in skb mode or over the veth are close to results of a tap
backend with vhost=on and disabled segmentation offloading bridged
with a NIC.
Signed-off-by: Ilya Maximets <i.maximets@ovn.org>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Commit: 0f4bc6d4527271c5dcdd6ccd72e077e046a8c310
https://github.com/qemu/qemu/commit/0f4bc6d4527271c5dcdd6ccd72e077e046a8c310
Author: Andrew Melnychenko <andrew@daynix.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M ebpf/ebpf_rss.c
M ebpf/ebpf_rss.h
Log Message:
-----------
ebpf: Added eBPF map update through mmap.
Changed eBPF map updates through mmaped array.
Mmaped arrays provide direct access to map data.
It should omit using bpf_map_update_elem() call,
which may require capabilities that are not present.
Signed-off-by: Andrew Melnychenko <andrew@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Commit: f2e208b9e406cb548f6eb6761a99288212a3fd43
https://github.com/qemu/qemu/commit/f2e208b9e406cb548f6eb6761a99288212a3fd43
Author: Andrew Melnychenko <andrew@daynix.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M ebpf/ebpf_rss-stub.c
M ebpf/ebpf_rss.c
M ebpf/ebpf_rss.h
Log Message:
-----------
ebpf: Added eBPF initialization by fds.
It allows using file descriptors of eBPF provided
outside of QEMU.
QEMU may be run without capabilities for eBPF and run
RSS program provided by management tool(g.e. libvirt).
Signed-off-by: Andrew Melnychenko <andrew@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Commit: e628ffac27f7ebc8c13baffe3c24e1e3fdeebd6d
https://github.com/qemu/qemu/commit/e628ffac27f7ebc8c13baffe3c24e1e3fdeebd6d
Author: Andrew Melnychenko <andrew@daynix.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M hw/net/virtio-net.c
M include/hw/virtio/virtio-net.h
Log Message:
-----------
virtio-net: Added property to load eBPF RSS with fds.
eBPF RSS program and maps may now be passed during initialization.
Initially was implemented for libvirt to launch qemu without permissions,
and initialized eBPF program through the helper.
Signed-off-by: Andrew Melnychenko <andrew@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Commit: 34ef7ae1001939adb3eaa7a6b8b0f8ae06228287
https://github.com/qemu/qemu/commit/34ef7ae1001939adb3eaa7a6b8b0f8ae06228287
Author: Andrew Melnychenko <andrew@daynix.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
A ebpf/ebpf.c
A ebpf/ebpf.h
M ebpf/ebpf_rss.c
M ebpf/meson.build
A qapi/ebpf.json
M qapi/meson.build
M qapi/qapi-schema.json
Log Message:
-----------
qmp: Added new command to retrieve eBPF blob.
Now, the binary objects may be retrieved by id.
It would require for future qmp commands that may require specific
eBPF blob.
Added command "request-ebpf". This command returns
eBPF program encoded base64. The program taken from the
skeleton and essentially is an ELF object that can be
loaded in the future with libbpf.
The reason to use the command to provide the eBPF object
instead of a separate artifact was to avoid issues related
to finding the eBPF itself. eBPF object is an ELF binary
that contains the eBPF program and eBPF map description(BTF).
Overall, eBPF object should contain the program and enough
metadata to create/load eBPF with libbpf. As the eBPF
maps/program should correspond to QEMU, the eBPF can't
be used from different QEMU build.
The first solution was a helper that comes with QEMU
and loads appropriate eBPF objects. And the issue is
to find a proper helper if the system has several
different QEMUs installed and/or built from the source,
which helpers may not be compatible.
Another issue is QEMU updating while there is a running
QEMU instance. With an updated helper, it may not be
possible to hotplug virtio-net device to the already
running QEMU. Overall, requesting the eBPF object from
QEMU itself solves possible failures with acceptable effort.
Links:
[PATCH 3/5] qmp: Added the helper stamp check.
https://lore.kernel.org/all/20230219162100.174318-4-andrew@daynix.com/
Signed-off-by: Andrew Melnychenko <andrew@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Commit: 049cfda145e96b2605cdf9739f1bcf9ebf3a83e1
https://github.com/qemu/qemu/commit/049cfda145e96b2605cdf9739f1bcf9ebf3a83e1
Author: Andrew Melnychenko <andrew@daynix.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M ebpf/rss.bpf.skeleton.h
M meson.build
M tools/ebpf/rss.bpf.c
Log Message:
-----------
ebpf: Updated eBPF program and skeleton.
Updated section name, so libbpf should init/gues proper
program type without specifications during open/load.
Also, added map_flags with explicitly declared BPF_F_MMAPABLE.
Added check for BPF_F_MMAPABLE flag to meson script and
requirements to libbpf version.
Signed-off-by: Andrew Melnychenko <andrew@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Commit: 3809a216ef60c783c39b71096ab095d7f3d50395
https://github.com/qemu/qemu/commit/3809a216ef60c783c39b71096ab095d7f3d50395
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M MAINTAINERS
M docs/specs/pci-ids.rst
M hw/Kconfig
M hw/meson.build
A hw/ufs/Kconfig
A hw/ufs/lu.c
A hw/ufs/meson.build
A hw/ufs/trace-events
A hw/ufs/trace.h
A hw/ufs/ufs.c
A hw/ufs/ufs.h
A include/block/ufs.h
M include/hw/pci/pci.h
M include/hw/pci/pci_ids.h
M include/scsi/constants.h
M iothread.c
M meson.build
M tests/qtest/meson.build
A tests/qtest/ufs-test.c
Log Message:
-----------
Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into
staging
Pull request
- Jeuk Kim's emulated UFS device
- Fabiano Rosas' IOThread GSource "name" debugging aid
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# gpg: Signature made Thu 07 Sep 2023 14:16:22 EDT
# gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8
# gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [ultimate]
# gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" [ultimate]
# Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8
* tag 'block-pull-request' of https://gitlab.com/stefanha/qemu:
tests/qtest: Introduce tests for UFS
hw/ufs: Support for UFS logical unit
hw/ufs: Support for Query Transfer Requests
hw/ufs: Initial commit for emulated Universal-Flash-Storage
iothread: Set the GSource "name" field
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: bc3a60174d65a90a5dc97c1517910b0180dff51e
https://github.com/qemu/qemu/commit/bc3a60174d65a90a5dc97c1517910b0180dff51e
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M block/nbd.c
M docs/tools/qemu-nbd.rst
M include/block/nbd.h
M include/io/channel-util.h
M include/io/channel.h
M include/qemu/vhost-user-server.h
M io/channel-command.c
M io/channel-file.c
M io/channel-null.c
M io/channel-socket.c
M io/channel-tls.c
M io/channel-util.c
M io/channel.c
M migration/channel-block.c
M migration/rdma.c
M nbd/client-connection.c
M nbd/client.c
M nbd/server.c
M qemu-nbd.c
M scsi/qemu-pr-helper.c
M tests/qemu-iotests/197
M tests/qemu-iotests/197.out
M util/iov.c
M util/vhost-user-server.c
Log Message:
-----------
Merge tag 'pull-nbd-2023-09-07' of https://repo.or.cz/qemu/ericb into staging
NBD patches for 2023-09-07
- Andrey Drobyshev - fix regression in iotest 197 under -nbd
- Stefan Hajnoczi - allow coroutine read and write context to split
across threads
- Philippe Mathieu-Daudé - remove a VLA allocation
- Denis V. Lunev - fix regression in iotest 233 with qemu-nbd -v --fork
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# gpg: Signature made Thu 07 Sep 2023 21:34:55 EDT
# gpg: using RSA key 71C2CC22B1C4602927D2F3AAA7A16B4A2527436A
# gpg: Good signature from "Eric Blake <eblake@redhat.com>" [full]
# gpg: aka "Eric Blake (Free Software Programmer)
<ebb9@byu.net>" [full]
# gpg: aka "[jpeg image of size 6874]" [full]
# Primary key fingerprint: 71C2 CC22 B1C4 6029 27D2 F3AA A7A1 6B4A 2527 436A
* tag 'pull-nbd-2023-09-07' of https://repo.or.cz/qemu/ericb:
qemu-nbd: document -v behavior in respect to --fork in man
qemu-nbd: Restore "qemu-nbd -v --fork" output
qemu-nbd: invent nbd_client_release_pipe() helper
qemu-nbd: put saddr into into struct NbdClientOpts
qemu-nbd: move srcpath into struct NbdClientOpts
qemu-nbd: define struct NbdClientOpts when HAVE_NBD_DEVICE is not defined
qemu-nbd: improve error message for dup2 error
util/iov: Avoid dynamic stack allocation
io: follow coroutine AioContext in qio_channel_yield()
io: check there are no qio_channel_yield() coroutines during ->finalize()
nbd: drop unused nbd_start_negotiate() aio_context argument
nbd: drop unused nbd_receive_negotiate() aio_context argument
qemu-iotests/197: use more generic commands for formats other than qcow2
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 759a86ba235a4609064ca3ba867646e2e1b479a0
https://github.com/qemu/qemu/commit/759a86ba235a4609064ca3ba867646e2e1b479a0
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M crypto/aes.c
M crypto/sm4.c
M docs/about/deprecated.rst
M hw/char/riscv_htif.c
M hw/intc/riscv_aclint.c
M hw/intc/riscv_aplic.c
M hw/intc/riscv_imsic.c
M hw/riscv/virt.c
M include/crypto/aes.h
M include/crypto/sm4.h
M linux-user/riscv/signal.c
M linux-user/syscall.c
M target/arm/tcg/crypto_helper.c
M target/riscv/cpu-qom.h
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
M target/riscv/cpu_cfg.h
M target/riscv/cpu_helper.c
M target/riscv/crypto_helper.c
M target/riscv/csr.c
M target/riscv/debug.c
M target/riscv/debug.h
M target/riscv/helper.h
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvv.c.inc
A target/riscv/insn_trans/trans_rvvk.c.inc
M target/riscv/insn_trans/trans_rvzfa.c.inc
M target/riscv/kvm.c
M target/riscv/kvm_riscv.h
M target/riscv/meson.build
M target/riscv/pmp.c
M target/riscv/translate.c
A target/riscv/vcrypto_helper.c
M target/riscv/vector_helper.c
A target/riscv/vector_internals.c
A target/riscv/vector_internals.h
M tests/avocado/tuxrun_baselines.py
Log Message:
-----------
Merge tag 'pull-riscv-to-apply-20230908' of
https://github.com/alistair23/qemu into staging
First RISC-V PR for 8.2
* Remove 'host' CPU from TCG
* riscv_htif Fixup printing on big endian hosts
* Add zmmul isa string
* Add smepmp isa string
* Fix page_check_range use in fault-only-first
* Use existing lookup tables for MixColumns
* Add RISC-V vector cryptographic instruction set support
* Implement WARL behaviour for mcountinhibit/mcounteren
* Add Zihintntl extension ISA string to DTS
* Fix zfa fleq.d and fltq.d
* Fix upper/lower mtime write calculation
* Make rtc variable names consistent
* Use abi type for linux-user target_ucontext
* Add RISC-V KVM AIA Support
* Fix riscv,pmu DT node path in the virt machine
* Update CSR bits name for svadu extension
* Mark zicond non-experimental
* Fix satp_mode_finalize() when satp_mode.supported = 0
* Fix non-KVM --enable-debug build
* Add new extensions to hwprobe
* Use accelerated helper for AES64KS1I
* Allocate itrigger timers only once
* Respect mseccfg.RLB for pmpaddrX changes
* Align the AIA model to v1.0 ratified spec
* Don't read the CSR in riscv_csrrw_do64
* Add the 'max' CPU, detect user choice in TCG
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# =JoBU
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 08 Sep 2023 02:00:23 EDT
# gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013
* tag 'pull-riscv-to-apply-20230908' of https://github.com/alistair23/qemu: (65
commits)
target/riscv/cpu.c: consider user option with RVG
target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update()
target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions()
target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig
target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize()
target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update()
target/riscv: make CPUCFG() macro public
target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled
target/riscv: deprecate the 'any' CPU type
avocado, risc-v: add tuxboot tests for 'max' CPU
target/riscv: add 'max' CPU type
target/riscv/cpu.c: limit cfg->vext_spec log message
target/riscv/cpu.c: add riscv_cpu_add_kvm_unavail_prop_array()
target/riscv/cpu.c: add riscv_cpu_add_qdev_prop_array()
target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[]
target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[]
target/riscv: add DEFINE_PROP_END_OF_LIST() to riscv_cpu_options[]
target/riscv/cpu.c: split kvm prop handling to its own helper
target/riscv/cpu.c: skip 'bool' check when filtering KVM props
target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 82e181ad65dab229cef41e626f2a2ee0ff2ceada
https://github.com/qemu/qemu/commit/82e181ad65dab229cef41e626f2a2ee0ff2ceada
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M MAINTAINERS
A ebpf/ebpf.c
A ebpf/ebpf.h
M ebpf/ebpf_rss-stub.c
M ebpf/ebpf_rss.c
M ebpf/ebpf_rss.h
M ebpf/meson.build
M ebpf/rss.bpf.skeleton.h
M hmp-commands.hx
M hw/core/machine.c
M hw/net/e1000e_core.c
M hw/net/igb_core.c
M hw/net/igb_regs.h
M hw/net/trace-events
M hw/net/vhost_net.c
M hw/net/virtio-net.c
M hw/net/vmxnet3.c
M include/hw/virtio/virtio-net.h
M include/net/net.h
M meson.build
M meson_options.txt
A net/af-xdp.c
M net/clients.h
M net/meson.build
M net/net.c
M net/tap-bsd.c
M net/tap-linux.c
M net/tap-linux.h
M net/tap-solaris.c
M net/tap-stub.c
M net/tap-win32.c
M net/tap.c
M net/tap_int.h
M net/vhost-vdpa.c
A qapi/ebpf.json
M qapi/meson.build
M qapi/net.json
M qapi/qapi-schema.json
M qemu-options.hx
M scripts/ci/org.centos/stream/8/x86_64/configure
M scripts/meson-buildoptions.sh
M tests/docker/dockerfiles/debian-amd64.docker
M tests/qtest/libqos/igb.c
M tools/ebpf/rss.bpf.c
Log Message:
-----------
Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging
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# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 08 Sep 2023 02:36:55 EDT
# gpg: using RSA key EF04965B398D6211
# gpg: Good signature from "Jason Wang (Jason Wang on RedHat)
<jasowang@redhat.com>" [full]
# Primary key fingerprint: 215D 46F4 8246 689E C77F 3562 EF04 965B 398D 6211
* tag 'net-pull-request' of https://github.com/jasowang/qemu:
ebpf: Updated eBPF program and skeleton.
qmp: Added new command to retrieve eBPF blob.
virtio-net: Added property to load eBPF RSS with fds.
ebpf: Added eBPF initialization by fds.
ebpf: Added eBPF map update through mmap.
net: add initial support for AF_XDP network backend
e1000e: rename e1000e_ba_state and e1000e_write_hdr_to_rx_buffers
igb: packet-split descriptors support
igb: add IPv6 extended headers traffic detection
igb: RX payload guest writting refactoring
igb: RX descriptors guest writting refactoring
igb: rename E1000E_RingInfo_st
igb: remove TCP ACK detection
virtio-net: Add support for USO features
virtio-net: Add USO flags to vhost support.
tap: Add check for USO features
tap: Add USO support to tap device.
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Compare: https://github.com/qemu/qemu/compare/03a3a62fbd0a...82e181ad65da
- [Qemu-commits] [qemu/qemu] 1f14c9: iothread: Set the GSource "name" field,
Alex Bennée <=