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[Qemu-commits] [qemu/qemu] 871a7f: tests/tcg/aarch64: Adjust pauth tests
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From: |
Alex Bennée |
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Subject: |
[Qemu-commits] [qemu/qemu] 871a7f: tests/tcg/aarch64: Adjust pauth tests for FEAT_FPAC |
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Date: |
Mon, 11 Sep 2023 08:19:23 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 871a7f6a9a62df2908f69b43fde4baff36305e34
https://github.com/qemu/qemu/commit/871a7f6a9a62df2908f69b43fde4baff36305e34
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M tests/tcg/aarch64/Makefile.target
M tests/tcg/aarch64/pauth-2.c
M tests/tcg/aarch64/pauth-4.c
M tests/tcg/aarch64/pauth-5.c
A tests/tcg/aarch64/pauth.h
Log Message:
-----------
tests/tcg/aarch64: Adjust pauth tests for FEAT_FPAC
With FEAT_FPAC, AUT* instructions that fail authentication
do not produce an error value but instead fault.
For pauth-2, install a signal handler and verify it gets called.
For pauth-4 and pauth-5, we are explicitly testing the error value,
so there's nothing to test with FEAT_FPAC, so exit early.
Adjust the makefile to use -cpu neoverse-v1, which has FEAT_EPAC
but not FEAT_FPAC.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230829232335.965414-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a969fe9755d9f6e6319b6eb308c8afeec1ccc969
https://github.com/qemu/qemu/commit/a969fe9755d9f6e6319b6eb308c8afeec1ccc969
Author: Aaron Lindsay <aaron@os.amperecomputing.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/hvf/hvf.c
M target/arm/kvm64.c
Log Message:
-----------
target/arm: Add ID_AA64ISAR2_EL1
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230829232335.965414-3-richard.henderson@linaro.org
[PMM: drop the HVF part of the patch and just comment that
we need to do something when the register appears in that API]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0274bd7be7daf0e9e6a8743e1daebda5246f155f
https://github.com/qemu/qemu/commit/0274bd7be7daf0e9e6a8743e1daebda5246f155f
Author: Aaron Lindsay <aaron@os.amperecomputing.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/arm/cpu.h
M target/arm/tcg/pauth_helper.c
Log Message:
-----------
target/arm: Add feature detection for FEAT_Pauth2 and extensions
Rename isar_feature_aa64_pauth_arch to isar_feature_aa64_pauth_qarma5
to distinguish the other architectural algorithm qarma3.
Add ARMPauthFeature and isar_feature_pauth_feature to cover the
other pauth conditions.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230829232335.965414-4-richard.henderson@linaro.org
Message-Id: <20230609172324.982888-3-aaron@os.amperecomputing.com>
[rth: Add ARMPauthFeature and eliminate most other predicates]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 6c3427eec532d534fae05d8aa740a9dcca5826e8
https://github.com/qemu/qemu/commit/6c3427eec532d534fae05d8aa740a9dcca5826e8
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/arm/cpu64.c
M target/arm/tcg/cpu64.c
Log Message:
-----------
target/arm: Don't change pauth features when changing algorithm
We have cpu properties to adjust the pauth algorithm for the
purpose of speed of emulation. Retain the set of pauth features
supported by the cpu even as the algorithm changes.
This already affects the neoverse-v1 cpu, which has FEAT_EPAC.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230829232335.965414-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 399e5e71253469630b4a41089ae5fde04d95ac68
https://github.com/qemu/qemu/commit/399e5e71253469630b4a41089ae5fde04d95ac68
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M docs/system/arm/cpu-features.rst
M docs/system/arm/emulation.rst
M target/arm/arm-qmp-cmds.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/tcg/pauth_helper.c
M tests/qtest/arm-cpu-features.c
Log Message:
-----------
target/arm: Implement FEAT_PACQARMA3
Implement the QARMA3 cryptographic algorithm for PAC calculation.
Implement a cpu feature to select the algorithm and document it.
Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230829232335.965414-6-richard.henderson@linaro.org
Message-Id: <20230609172324.982888-4-aaron@os.amperecomputing.com>
[rth: Merge cpu feature addition from another patch.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c3ccd5669e957d97b340a65295a8f072e218ca46
https://github.com/qemu/qemu/commit/c3ccd5669e957d97b340a65295a8f072e218ca46
Author: Aaron Lindsay <aaron@os.amperecomputing.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/tcg/cpu64.c
M target/arm/tcg/pauth_helper.c
Log Message:
-----------
target/arm: Implement FEAT_EPAC
Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230829232335.965414-7-richard.henderson@linaro.org
Message-Id: <20230609172324.982888-5-aaron@os.amperecomputing.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c7c807f6dd6dbc382225d3e0eb35545ca3f50f86
https://github.com/qemu/qemu/commit/c7c807f6dd6dbc382225d3e0eb35545ca3f50f86
Author: Aaron Lindsay <aaron@os.amperecomputing.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/tcg/cpu64.c
M target/arm/tcg/pauth_helper.c
Log Message:
-----------
target/arm: Implement FEAT_Pauth2
Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230829232335.965414-8-richard.henderson@linaro.org
Message-Id: <20230609172324.982888-6-aaron@os.amperecomputing.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 28b9dcb74bf709e4f18bc99da3e946849f9aef17
https://github.com/qemu/qemu/commit/28b9dcb74bf709e4f18bc99da3e946849f9aef17
Author: Aaron Lindsay <aaron@os.amperecomputing.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/arm/tcg/helper-a64.h
M target/arm/tcg/pauth_helper.c
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Inform helpers whether a PAC instruction is 'combined'
An instruction is a 'combined' Pointer Authentication instruction
if it does something in addition to PAC -- for instance, branching
to or loading an address from the authenticated pointer.
Knowing whether a PAC operation is 'combined' is needed to
implement FEAT_FPACCOMBINE.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230829232335.965414-9-richard.henderson@linaro.org
Message-Id: <20230609172324.982888-7-aaron@os.amperecomputing.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 8a69a42340a5f6b0d6d4b3b68de9919b3e59e712
https://github.com/qemu/qemu/commit/8a69a42340a5f6b0d6d4b3b68de9919b3e59e712
Author: Aaron Lindsay <aaron@os.amperecomputing.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/syndrome.h
M target/arm/tcg/cpu64.c
M target/arm/tcg/pauth_helper.c
Log Message:
-----------
target/arm: Implement FEAT_FPAC and FEAT_FPACCOMBINE
Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230829232335.965414-10-richard.henderson@linaro.org
Message-Id: <20230609172324.982888-8-aaron@os.amperecomputing.com>
[rth: Simplify fpac comparison, reusing cmp_mask]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3c2c599c79eea9cebd7280140a5901fe3734e94e
https://github.com/qemu/qemu/commit/3c2c599c79eea9cebd7280140a5901fe3734e94e
Author: Philippe Mathieu-Daudé <philmd@redhat.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M block/vpc.c
Log Message:
-----------
block/vpc: Avoid dynamic stack allocation
Use autofree heap allocation instead of variable-length array on the
stack. Here we don't expect the bitmap size to be enormous, and
since we're about to read/write it to disk the overhead of the
allocation should be fine.
The codebase has very few VLAs, and if we can get rid of them all we
can make the compiler error on new additions. This is a defensive
measure against security bugs where an on-stack dynamic allocation
isn't correctly size-checked (e.g. CVE-2021-3527).
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
[PMM: expanded commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-ID: <20230811175229.808139-1-peter.maydell@linaro.org>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: 65c23ef1e4197c53d3836906895062307e48a6c5
https://github.com/qemu/qemu/commit/65c23ef1e4197c53d3836906895062307e48a6c5
Author: Fiona Ebner <f.ebner@proxmox.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M tests/qemu-iotests/109.out
M tests/qemu-iotests/185
M tests/qemu-iotests/185.out
Log Message:
-----------
iotests: adapt test output for new qemu_cleanup() behavior
Since commit ca2a5e630d ("qemu_cleanup: begin drained section after
vm_shutdown()"), there will be an additional pause for jobs during
qemu_cleanup(). The reason is that the bdrv_drain_all() call in
do_vm_stop() is not inside the drained section used by qemu_cleanup()
anymore. I.e., there is a second drained section now that ends before
the final one in qemu_cleanup() starts. Thus, job_pause() is called
twice during cleanup (via child_job_drained_begin()).
Test 185 needs to be adapted directly too, because it waits for a
specific number of JOB_STATUS_CHANGE events before the
BLOCK_JOB_CANCELLED event.
Reported-by: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Fiona Ebner <f.ebner@proxmox.com>
Message-ID: <20230817112538.255111-1-f.ebner@proxmox.com>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: 3480ce69a9c7ee956323c45269d21b6905488904
https://github.com/qemu/qemu/commit/3480ce69a9c7ee956323c45269d21b6905488904
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M block/io.c
Log Message:
-----------
block: minimize bs->reqs_lock section in tracked_request_end()
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-ID: <20230808155852.2745350-2-stefanha@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: fa9185fcdfceeb1a02f61a003acd19509e146bde
https://github.com/qemu/qemu/commit/fa9185fcdfceeb1a02f61a003acd19509e146bde
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M block.c
M block/io.c
M include/block/block_int-common.h
Log Message:
-----------
block: change reqs_lock to QemuMutex
CoMutex has poor performance when lock contention is high. The tracked
requests list is accessed frequently and performance suffers in QEMU
multi-queue block layer scenarios.
It is not necessary to use CoMutex for the requests lock. The lock is
always released across coroutine yield operations. It is held for
relatively short periods of time and it is not beneficial to yield when
the lock is held by another coroutine.
Change the lock type from CoMutex to QemuMutex to improve multi-queue
block layer performance. fio randread bs=4k iodepth=64 with 4 IOThreads
handling a virtio-blk device with 8 virtqueues improves from 254k to
517k IOPS (+203%). Full benchmark results and configuration details are
available here:
https://gitlab.com/stefanha/virt-playbooks/-/commit/980c40845d540e3669add1528739503c2e817b57
In the future we may wish to introduce thread-local tracked requests
lists to avoid lock contention completely. That would be much more
involved though.
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-ID: <20230808155852.2745350-3-stefanha@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: b0a6620acfe4c2997935cb3a9baa0d429ab8d61a
https://github.com/qemu/qemu/commit/b0a6620acfe4c2997935cb3a9baa0d429ab8d61a
Author: Michael Tokarev <mjt@tls.msk.ru>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M qemu-img.c
M tests/qemu-iotests/080.out
M tests/qemu-iotests/112.out
M tests/qemu-iotests/244.out
Log Message:
-----------
qemu-img: omit errno value in error message
I'm getting io-qcow2-244 test failure on mips*
due to output mismatch:
Take an internal snapshot:
-qemu-img: Could not create snapshot 'test': -95 (Operation not supported)
+qemu-img: Could not create snapshot 'test': -122 (Operation not supported)
No errors were found on the image.
This is because errno values might be different across
different architectures.
This error message in qemu-img.c is the only one which
prints errno directly, all the rest print strerror(errno)
only. Fix this error message and the expected output
of the 3 test cases too.
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Message-ID: <20230811110946.2435067-1-mjt@tls.msk.ru>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: 7966a36c83132c5eebf04a60d9e475b0aa6e7f88
https://github.com/qemu/qemu/commit/7966a36c83132c5eebf04a60d9e475b0aa6e7f88
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M block/iscsi.c
Log Message:
-----------
block/iscsi: Document why we use raw malloc()
In block/iscsi.c we use a raw malloc() call, which is unusual
given the project standard is to use the glib memory allocation
functions. Document why we do so, to avoid it being converted
to g_malloc() by mistake.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-ID: <20230727150705.2664464-1-peter.maydell@linaro.org>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: 816248675a21d5b4d82f22a6a19ddd2a7fbfee18
https://github.com/qemu/qemu/commit/816248675a21d5b4d82f22a6a19ddd2a7fbfee18
Author: Hanna Czenczek <hreitz@redhat.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M block.c
Log Message:
-----------
block: Be more verbose in create fallback
For image creation code, we have central fallback code for protocols
that do not support creating new images (like NBD or iscsi). So for
them, you can only specify existing paths/exports that are overwritten
to make clean new images. In such a case, if the given path cannot be
opened (assuming a pre-existing image there), we print an error message
that tries to describe what is going on: That with this protocol, you
cannot create new images, but only overwrite existing ones; and the
given path could not be opened as a pre-existing image.
However, the current message is confusing, because it does not say that
the protocol in question does not support creating new images, but
instead that "image creation" is unsupported. This can be interpreted
to mean that `qemu-img create` will not work in principle, which is not
true. Be more verbose for clarity.
Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=2217204
Signed-off-by: Hanna Czenczek <hreitz@redhat.com>
Message-ID: <20230720140024.46836-1-hreitz@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: a675ca4c620e66c1d45d55037f8fc21286af58cd
https://github.com/qemu/qemu/commit/a675ca4c620e66c1d45d55037f8fc21286af58cd
Author: Kevin Wolf <kwolf@redhat.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M docs/tools/qemu-img.rst
Log Message:
-----------
qemu-img: Update documentation for compressed images
Document the 'compression_type' option for qcow2, and mention that
streamOptimized vmdk supports compression, too.
Reported-by: Richard W.M. Jones <rjones@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Message-ID: <20230901102430.23856-1-kwolf@redhat.com>
Reviewed-by: Richard W.M. Jones <rjones@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: a8d99c0e6c52191c8a3e01ed79b1a9f186a3a91e
https://github.com/qemu/qemu/commit/a8d99c0e6c52191c8a3e01ed79b1a9f186a3a91e
Author: Dmitry Frolov <frolov@swemel.ru>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M block/vmdk.c
Log Message:
-----------
vmdk: Clean up bdrv_open_child() return value check
bdrv_open_child() may return NULL.
Usually return value is checked for this function.
Check for return value is more reliable.
Fixes: 24bc15d1f6 ("vmdk: Use BdrvChild instead of BDS for references to
extents")
Signed-off-by: Dmitry Frolov <frolov@swemel.ru>
Message-ID: <20230831125926.796205-1-frolov@swemel.ru>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: be2e51c5034ffb2b8d9a4618e8f9b7ff82cb057c
https://github.com/qemu/qemu/commit/be2e51c5034ffb2b8d9a4618e8f9b7ff82cb057c
Author: Fabiano Rosas <farosas@suse.de>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M block/qapi.c
M include/block/qapi.h
Log Message:
-----------
block: Remove bdrv_query_block_node_info
The last call site of this function has been removed by commit
c04d0ab026 ("qemu-img: Let info print block graph").
Reviewed-by: Claudio Fontana <cfontana@suse.de>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Message-ID: <20230901184605.32260-2-farosas@suse.de>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: c3b29ae6b4e2bf70739e49154f24c8e850b34bf7
https://github.com/qemu/qemu/commit/c3b29ae6b4e2bf70739e49154f24c8e850b34bf7
Author: Fabiano Rosas <farosas@suse.de>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M block/qapi.c
Log Message:
-----------
block: Remove unnecessary variable in bdrv_block_device_info
The commit 5d8813593f ("block/qapi: Let bdrv_query_image_info()
recurse") removed the loop where we set the 'bs0' variable, so now it
is just the same as 'bs'.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230901184605.32260-3-farosas@suse.de>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: 9e03a5e195a20e7a342bcbf9e49e113e4b4dc23d
https://github.com/qemu/qemu/commit/9e03a5e195a20e7a342bcbf9e49e113e4b4dc23d
Author: Kevin Wolf <kwolf@redhat.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M block/meson.build
Log Message:
-----------
block/meson.build: Restore alphabetical order of files
When commit 5e5733e5999 created block/meson.build, the list of
unconditionally added files was in alphabetical order. Later commits
added new files in random places. Reorder the list to be alphabetical
again. (As for ordering foo.c against foo-*.c, there are both ways used
currently; standardise on having foo.c first, even though this is
different from the original commit 5e5733e5999.)
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Message-ID: <20230905130607.35134-2-kwolf@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: 9ea473fb7bd01d350a860044b3d8e46f8747e865
https://github.com/qemu/qemu/commit/9ea473fb7bd01d350a860044b3d8e46f8747e865
Author: Kevin Wolf <kwolf@redhat.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M block/copy-before-write.c
M block/preallocate.c
M block/snapshot-access.c
Log Message:
-----------
block: Make more BlockDriver definitions static
Most block driver implementations don't have any reason for their
BlockDriver to be public. The only exceptions are bdrv_file, bdrv_raw
and bdrv_qcow2, which are actually used in other source files.
Make all other BlockDriver definitions static if they aren't yet.
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Message-ID: <20230905130607.35134-3-kwolf@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: 8686a689e5bc205bdba0e647c269b86756cbc504
https://github.com/qemu/qemu/commit/8686a689e5bc205bdba0e647c269b86756cbc504
Author: Kevin Wolf <kwolf@redhat.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M include/migration/vmstate.h
Log Message:
-----------
vmstate: Mark VMStateInfo.get/put() coroutine_mixed_fn
Migration code can run both in coroutine context (the usual case) and
non-coroutine context (at least savevm/loadvm for snapshots). This also
affects the VMState callbacks, and devices must consider this. Change
the callback definition in VMStateInfo to be explicit about it.
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Message-ID: <20230905145002.46391-2-kwolf@redhat.com>
Acked-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: 92e2e6a867334a990f8d29f07ca34e3162fdd6ec
https://github.com/qemu/qemu/commit/92e2e6a867334a990f8d29f07ca34e3162fdd6ec
Author: Kevin Wolf <kwolf@redhat.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M hw/virtio/virtio.c
Log Message:
-----------
virtio: Drop out of coroutine context in virtio_load()
virtio_load() as a whole should run in coroutine context because it
reads from the migration stream and we don't want this to block.
However, it calls virtio_set_features_nocheck() and devices don't
expect their .set_features callback to run in a coroutine and therefore
call functions that may not be called in coroutine context. To fix this,
drop out of coroutine context for calling virtio_set_features_nocheck().
Without this fix, the following crash was reported:
#0 __pthread_kill_implementation (threadid=<optimized out>,
signo=signo@entry=6, no_tid=no_tid@entry=0) at pthread_kill.c:44
#1 0x00007efc738c05d3 in __pthread_kill_internal (signo=6,
threadid=<optimized out>) at pthread_kill.c:78
#2 0x00007efc73873d26 in __GI_raise (sig=sig@entry=6) at
../sysdeps/posix/raise.c:26
#3 0x00007efc738477f3 in __GI_abort () at abort.c:79
#4 0x00007efc7384771b in __assert_fail_base (fmt=0x7efc739dbcb8 "",
assertion=assertion@entry=0x560aebfbf5cf "!qemu_in_coroutine()",
file=file@entry=0x560aebfcd2d4 "../block/graph-lock.c",
line=line@entry=275, function=function@entry=0x560aebfcd34d "void
bdrv_graph_rdlock_main_loop(void)") at assert.c:92
#5 0x00007efc7386ccc6 in __assert_fail (assertion=0x560aebfbf5cf
"!qemu_in_coroutine()", file=0x560aebfcd2d4 "../block/graph-lock.c", line=275,
function=0x560aebfcd34d "void bdrv_graph_rdlock_main_loop(void)") at
assert.c:101
#6 0x0000560aebcd8dd6 in bdrv_register_buf ()
#7 0x0000560aeb97ed97 in ram_block_added.llvm ()
#8 0x0000560aebb8303f in ram_block_add.llvm ()
#9 0x0000560aebb834fa in qemu_ram_alloc_internal.llvm ()
#10 0x0000560aebb2ac98 in vfio_region_mmap ()
#11 0x0000560aebb3ea0f in vfio_bars_register ()
#12 0x0000560aebb3c628 in vfio_realize ()
#13 0x0000560aeb90f0c2 in pci_qdev_realize ()
#14 0x0000560aebc40305 in device_set_realized ()
#15 0x0000560aebc48e07 in property_set_bool.llvm ()
#16 0x0000560aebc46582 in object_property_set ()
#17 0x0000560aebc4cd58 in object_property_set_qobject ()
#18 0x0000560aebc46ba7 in object_property_set_bool ()
#19 0x0000560aeb98b3ca in qdev_device_add_from_qdict ()
#20 0x0000560aebb1fbaf in virtio_net_set_features ()
#21 0x0000560aebb46b51 in virtio_set_features_nocheck ()
#22 0x0000560aebb47107 in virtio_load ()
#23 0x0000560aeb9ae7ce in vmstate_load_state ()
#24 0x0000560aeb9d2ee9 in qemu_loadvm_state_main ()
#25 0x0000560aeb9d45e1 in qemu_loadvm_state ()
#26 0x0000560aeb9bc32c in process_incoming_migration_co.llvm ()
#27 0x0000560aebeace56 in coroutine_trampoline.llvm ()
Cc: qemu-stable@nongnu.org
Buglink: https://issues.redhat.com/browse/RHEL-832
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Message-ID: <20230905145002.46391-3-kwolf@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Commit: 0df11497c206666d21715e42cc765d96b4f3413b
https://github.com/qemu/qemu/commit/0df11497c206666d21715e42cc765d96b4f3413b
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M hw/intc/arm_gicv3_its.c
Log Message:
-----------
hw/intc/arm_gicv3_its: Avoid maybe-uninitialized error in get_vte()
Fix when using GCC v11.4 (Ubuntu 11.4.0-1ubuntu1~22.04) with CFLAGS=-Og:
[4/6] Compiling C object libcommon.fa.p/hw_intc_arm_gicv3_its.c.o
FAILED: libcommon.fa.p/hw_intc_arm_gicv3_its.c.o
inlined from ‘lookup_vte’ at hw/intc/arm_gicv3_its.c:453:9,
inlined from ‘vmovp_callback’ at hw/intc/arm_gicv3_its.c:1039:14:
hw/intc/arm_gicv3_its.c:347:9: error: ‘vte.rdbase’ may be used uninitialized
[-Werror=maybe-uninitialized]
347 | trace_gicv3_its_vte_read(vpeid, vte->valid, vte->vptsize,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
348 | vte->vptaddr, vte->rdbase);
| ~~~~~~~~~~~~~~~~~~~~~~~~~~
hw/intc/arm_gicv3_its.c: In function ‘vmovp_callback’:
hw/intc/arm_gicv3_its.c:1036:13: note: ‘vte’ declared here
1036 | VTEntry vte;
| ^~~
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20230831131348.69032-1-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5a8559e2cc07f56470be5709efd17e5514a6a217
https://github.com/qemu/qemu/commit/5a8559e2cc07f56470be5709efd17e5514a6a217
Author: Francisco Iglesias <francisco.iglesias@amd.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M MAINTAINERS
M hw/misc/meson.build
A hw/misc/xlnx-cfi-if.c
A include/hw/misc/xlnx-cfi-if.h
Log Message:
-----------
hw/misc: Introduce the Xilinx CFI interface
Introduce the Xilinx Configuration Frame Interface (CFI) for transmitting
CFI data packets between the Xilinx Configuration Frame Unit models
(CFU_APB, CFU_FDRO and CFU_SFR), the Xilinx CFRAME controller (CFRAME_REG)
and the Xilinx CFRAME broadcast controller (CFRAME_BCAST_REG) models (when
emulating bitstream programming and readback).
Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
Reviewed-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
Acked-by: Edgar E. Iglesias <edgar@zeroasic.com>
Message-id: 20230831165701.2016397-2-francisco.iglesias@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 86d916c62145168120ec97a71404d91c0aa72835
https://github.com/qemu/qemu/commit/86d916c62145168120ec97a71404d91c0aa72835
Author: Francisco Iglesias <francisco.iglesias@amd.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M MAINTAINERS
M hw/misc/meson.build
A hw/misc/xlnx-versal-cfu.c
A include/hw/misc/xlnx-versal-cfu.h
Log Message:
-----------
hw/misc: Introduce a model of Xilinx Versal's CFU_APB
Introduce a model of the software programming interface (CFU_APB) of
Xilinx Versal's Configuration Frame Unit.
Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230831165701.2016397-3-francisco.iglesias@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ebfdc4942810905c44a59ee92f3d3809f40ee253
https://github.com/qemu/qemu/commit/ebfdc4942810905c44a59ee92f3d3809f40ee253
Author: Francisco Iglesias <francisco.iglesias@amd.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M hw/misc/xlnx-versal-cfu.c
M include/hw/misc/xlnx-versal-cfu.h
Log Message:
-----------
hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal CFU_FDRO
Introduce a model of Xilinx Versal's Configuration Frame Unit's data out
port (CFU_FDRO).
Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230831165701.2016397-4-francisco.iglesias@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 975dd496b5255c14ea46cf7d51a95703eeb1a2e3
https://github.com/qemu/qemu/commit/975dd496b5255c14ea46cf7d51a95703eeb1a2e3
Author: Francisco Iglesias <francisco.iglesias@amd.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M hw/misc/xlnx-versal-cfu.c
M include/hw/misc/xlnx-versal-cfu.h
Log Message:
-----------
hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal's CFU_SFR
Introduce a model of Xilinx Versal's Configuration Frame Unit's Single
Frame Read port (CFU_SFR).
Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230831165701.2016397-5-francisco.iglesias@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c6766f5b751d042f03a4cfdbee145c97cf4eedb9
https://github.com/qemu/qemu/commit/c6766f5b751d042f03a4cfdbee145c97cf4eedb9
Author: Francisco Iglesias <francisco.iglesias@amd.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M MAINTAINERS
M hw/misc/meson.build
A hw/misc/xlnx-versal-cframe-reg.c
A include/hw/misc/xlnx-versal-cframe-reg.h
Log Message:
-----------
hw/misc: Introduce a model of Xilinx Versal's CFRAME_REG
Introduce a model of Xilinx Versal's Configuration Frame controller
(CFRAME_REG).
Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
Message-id: 20230831165701.2016397-6-francisco.iglesias@amd.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: eadd3343c494379e68c18545c160a9f50b7239d0
https://github.com/qemu/qemu/commit/eadd3343c494379e68c18545c160a9f50b7239d0
Author: Francisco Iglesias <francisco.iglesias@amd.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M hw/misc/xlnx-versal-cframe-reg.c
M include/hw/misc/xlnx-versal-cframe-reg.h
Log Message:
-----------
hw/misc: Introduce a model of Xilinx Versal's CFRAME_BCAST_REG
Introduce a model of Xilinx Versal's Configuration Frame broadcast
controller (CFRAME_BCAST_REG).
Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230831165701.2016397-7-francisco.iglesias@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b286d08aa113e0480a65b8cc6c1979547decc183
https://github.com/qemu/qemu/commit/b286d08aa113e0480a65b8cc6c1979547decc183
Author: Francisco Iglesias <francisco.iglesias@amd.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M hw/arm/xlnx-versal.c
M include/hw/arm/xlnx-versal.h
Log Message:
-----------
hw/arm/xlnx-versal: Connect the CFU_APB, CFU_FDRO and CFU_SFR
Connect the Configuration Frame Unit (CFU_APB, CFU_FDRO and CFU_SFR) to
the Versal machine.
Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
Acked-by: Edgar E. Iglesias <edgar@zeroasic.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230831165701.2016397-8-francisco.iglesias@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4a0244b4b297f4790cd7cb3ea0468f4abe34766f
https://github.com/qemu/qemu/commit/4a0244b4b297f4790cd7cb3ea0468f4abe34766f
Author: Francisco Iglesias <francisco.iglesias@amd.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M hw/arm/xlnx-versal.c
M include/hw/arm/xlnx-versal.h
Log Message:
-----------
hw/arm/versal: Connect the CFRAME_REG and CFRAME_BCAST_REG
Connect the Configuration Frame controller (CFRAME_REG) and the
Configuration Frame broadcast controller (CFRAME_BCAST_REG) to the
Versal machine.
Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230831165701.2016397-9-francisco.iglesias@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 44e0ddee8e18459d99173096e6f22fc64f35f8e4
https://github.com/qemu/qemu/commit/44e0ddee8e18459d99173096e6f22fc64f35f8e4
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Do not use gen_mte_checkN in trans_STGP
STGP writes to tag memory, it does not check it.
This happened to work because we wrote tag memory first
so that the check always succeeded.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230901203103.136408-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 682814e2a3c883b27f24b9e7cab47313c49acbd4
https://github.com/qemu/qemu/commit/682814e2a3c883b27f24b9e7cab47313c49acbd4
Author: Colton Lewis <coltonlewis@google.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/arm/kvm64.c
Log Message:
-----------
arm64: Restore trapless ptimer access
Due to recent KVM changes, QEMU is setting a ptimer offset resulting
in unintended trap and emulate access and a consequent performance
hit. Filter out the PTIMER_CNT register to restore trapless ptimer
access.
Quoting Andrew Jones:
Simply reading the CNT register and writing back the same value is
enough to set an offset, since the timer will have certainly moved
past whatever value was read by the time it's written. QEMU
frequently saves and restores all registers in the get-reg-list array,
unless they've been explicitly filtered out (with Linux commit
680232a94c12, KVM_REG_ARM_PTIMER_CNT is now in the array). So, to
restore trapless ptimer accesses, we need a QEMU patch to filter out
the register.
See
https://lore.kernel.org/kvmarm/gsntttsonus5.fsf@coltonlewis-kvm.c.googlers.com/T/#m0770023762a821db2a3f0dd0a7dc6aa54e0d0da9
for additional context.
Cc: qemu-stable@nongnu.org
Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
Signed-off-by: Colton Lewis <coltonlewis@google.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Colton Lewis <coltonlewis@google.com>
Message-id: 20230831190052.129045-1-coltonlewis@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 97198a7dd1379928a09f58dff8ac7ce11b8fb39e
https://github.com/qemu/qemu/commit/97198a7dd1379928a09f58dff8ac7ce11b8fb39e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Implement RMR_ELx
Provide a stub implementation, as a write is a "request".
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230831232441.66020-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e3d45c0a895764203f489184d361fe4c74b2cd57
https://github.com/qemu/qemu/commit/e3d45c0a895764203f489184d361fe4c74b2cd57
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M docs/system/arm/virt.rst
M hw/arm/virt.c
M target/arm/tcg/cpu64.c
Log Message:
-----------
target/arm: Implement cortex-a710
The cortex-a710 is a first generation ARMv9.0-A processor.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230831232441.66020-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 27920d3d1de2f2b0d5048030820eec4fa64b8b36
https://github.com/qemu/qemu/commit/27920d3d1de2f2b0d5048030820eec4fa64b8b36
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/arm/helper.h
M target/arm/tcg/op_helper.c
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate.c
Log Message:
-----------
target/arm: Implement HCR_EL2.TIDCP
Perform the check for EL2 enabled in the security space and the
TIDCP bit in an out-of-line helper.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230831232441.66020-4-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9cd0c0dec97be99c0b42b589e63fad6f8c6488b8
https://github.com/qemu/qemu/commit/9cd0c0dec97be99c0b42b589e63fad6f8c6488b8
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/cpu.h
M target/arm/helper.h
M target/arm/tcg/cpu64.c
M target/arm/tcg/op_helper.c
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate.c
Log Message:
-----------
target/arm: Implement FEAT_TIDCP1
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230831232441.66020-5-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d03396a8bb19b77d4d0fa2ad2143999510f0d44e
https://github.com/qemu/qemu/commit/d03396a8bb19b77d4d0fa2ad2143999510f0d44e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M target/arm/cpu.c
Log Message:
-----------
target/arm: Enable SCTLR_EL1.TIDCP for user-only
The linux kernel detects and enables this bit. Once trapped,
EC_SYSTEMREGISTERTRAP is treated like EC_UNCATEGORIZED, so
no changes required within linux-user/aarch64/cpu_loop.c.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230831232441.66020-6-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c8f2eb5d414b788420b938f2ffdde891aa6c3ae8
https://github.com/qemu/qemu/commit/c8f2eb5d414b788420b938f2ffdde891aa6c3ae8
Author: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Date: 2023-09-08 (Fri, 08 Sep 2023)
Changed paths:
M accel/kvm/kvm-all.c
M include/sysemu/kvm_int.h
M qemu-options.hx
M target/arm/kvm.c
Log Message:
-----------
arm/kvm: Enable support for KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE
Now that we have Eager Page Split support added for ARM in the kernel,
enable it in Qemu. This adds,
-eager-split-size to -accel sub-options to set the eager page split chunk size.
-enable KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE.
The chunk size specifies how many pages to break at a time, using a
single allocation. Bigger the chunk size, more pages need to be
allocated ahead of time.
Reviewed-by: Gavin Shan <gshan@redhat.com>
Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Message-id: 20230905091246.1931-1-shameerali.kolothum.thodi@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 782ee711be9390f3586e615be49585aefd7fcaac
https://github.com/qemu/qemu/commit/782ee711be9390f3586e615be49585aefd7fcaac
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: do not run 'host' CPU with TCG
The 'host' CPU is available in a CONFIG_KVM build and it's currently
available for all accels, but is a KVM only CPU. This means that in a
RISC-V KVM capable host we can do things like this:
$ ./build/qemu-system-riscv64 -M virt,accel=tcg -cpu host --nographic
qemu-system-riscv64: H extension requires priv spec 1.12.0
This CPU does not have a priv spec because we don't filter its extensions
via priv spec. We shouldn't be reaching riscv_cpu_realize_tcg() at all
with the 'host' CPU.
We don't have a way to filter the 'host' CPU out of the available CPU
options (-cpu help) if the build includes both KVM and TCG. What we can
do is to error out during riscv_cpu_realize_tcg() if the user chooses
the 'host' CPU with accel=tcg:
$ ./build/qemu-system-riscv64 -M virt,accel=tcg -cpu host --nographic
qemu-system-riscv64: 'host' CPU is not compatible with TCG acceleration
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230721133411.474105-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c255946e3df4d9660e4f468a456633c24393d468
https://github.com/qemu/qemu/commit/c255946e3df4d9660e4f468a456633c24393d468
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M hw/char/riscv_htif.c
Log Message:
-----------
hw/char/riscv_htif: Fix printing of console characters on big endian hosts
The character that should be printed is stored in the 64 bit "payload"
variable. The code currently tries to print it by taking the address
of the variable and passing this pointer to qemu_chr_fe_write(). However,
this only works on little endian hosts where the least significant bits
are stored on the lowest address. To do this in a portable way, we have
to store the value in an uint8_t variable instead.
Fixes: 5033606780 ("RISC-V HTIF Console")
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230721094720.902454-2-thuth@redhat.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 058096f1c55ab688db7e1d6814aaefc1bcd87f7a
https://github.com/qemu/qemu/commit/058096f1c55ab688db7e1d6814aaefc1bcd87f7a
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M hw/char/riscv_htif.c
Log Message:
-----------
hw/char/riscv_htif: Fix the console syscall on big endian hosts
Values that have been read via cpu_physical_memory_read() from the
guest's memory have to be swapped in case the host endianess differs
from the guest.
Fixes: a6e13e31d5 ("riscv_htif: Support console output via proxy syscall")
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230721094720.902454-3-thuth@redhat.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 50f9464962fb41f04fd5f42e7ee2cb60942aba89
https://github.com/qemu/qemu/commit/50f9464962fb41f04fd5f42e7ee2cb60942aba89
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: add zmmul isa string
zmmul was promoted from experimental to ratified in commit 6d00ffad4e95.
Add a riscv,isa string for it.
Fixes: 6d00ffad4e95 ("target/riscv: move zmmul out of the experimental
properties")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230720132424.371132-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 03d7bbfd04c2a68f6339adede99ceae10800dc91
https://github.com/qemu/qemu/commit/03d7bbfd04c2a68f6339adede99ceae10800dc91
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: add smepmp isa string
The cpu->cfg.epmp extension is still experimental, but it already has a
'smepmp' riscv,isa string. Add it.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230720132424.371132-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4cc9f284d5971ecd8055d26ef74c23ef0be8b8f5
https://github.com/qemu/qemu/commit/4cc9f284d5971ecd8055d26ef74c23ef0be8b8f5
Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: Fix page_check_range use in fault-only-first
Commit bef6f008b98(accel/tcg: Return bool from page_check_range) converts
integer return value to bool type. However, it wrongly converted the use
of the API in riscv fault-only-first, where page_check_range < = 0, should
be converted to !page_check_range.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230729031618.821-1-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9ea17007c4ae4420ccd917eb300c7db49483a5b8
https://github.com/qemu/qemu/commit/9ea17007c4ae4420ccd917eb300c7db49483a5b8
Author: Ard Biesheuvel <ardb@kernel.org>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M crypto/aes.c
M include/crypto/aes.h
M target/riscv/crypto_helper.c
Log Message:
-----------
target/riscv: Use existing lookup tables for MixColumns
The AES MixColumns and InvMixColumns operations are relatively
expensive 4x4 matrix multiplications in GF(2^8), which is why C
implementations usually rely on precomputed lookup tables rather than
performing the calculations on demand.
Given that we already carry those tables in QEMU, we can just grab the
right value in the implementation of the RISC-V AES32 instructions. Note
that the tables in question are permuted according to the respective
Sbox, so we can omit the Sbox lookup as well in this case.
Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Philippe Mathieu-Daudé <philmd@linaro.org>
Cc: Zewen Ye <lustrew@foxmail.com>
Cc: Weiwei Li <liweiwei@iscas.ac.cn>
Cc: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230731084043.1791984-1-ardb@kernel.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 98f40dd2edacc284abb75f9a8135513475ca95e8
https://github.com/qemu/qemu/commit/98f40dd2edacc284abb75f9a8135513475ca95e8
Author: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M target/riscv/meson.build
M target/riscv/vector_helper.c
A target/riscv/vector_internals.c
A target/riscv/vector_internals.h
Log Message:
-----------
target/riscv: Refactor some of the generic vector functionality
Take some functions/macros out of `vector_helper` and put them in a new
module called `vector_internals`. This ensures they can be used by both
vector and vector-crypto helpers (latter implemented in proceeding
commits).
Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Max Chou <max.chou@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230711165917.2629866-2-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a44f19f611ad6358189c58b3c39012f68613e6f9
https://github.com/qemu/qemu/commit/a44f19f611ad6358189c58b3c39012f68613e6f9
Author: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: Refactor vector-vector translation macro
Refactor the non SEW-specific stuff out of `GEN_OPIVV_TRANS` into
function `opivv_trans` (similar to `opivi_trans`). `opivv_trans` will be
used in proceeding vector-crypto commits.
Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20230711165917.2629866-3-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 922f87351101379e3c2487120c394e51cf53984f
https://github.com/qemu/qemu/commit/922f87351101379e3c2487120c394e51cf53984f
Author: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: Remove redundant "cpu_vl == 0" checks
Remove the redundant "vl == 0" check which is already included within the
vstart >= vl check, when vl == 0.
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Max Chou <max.chou@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230711165917.2629866-4-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e13c7d3b5bfd632b3a39217843b28e185c366fc2
https://github.com/qemu/qemu/commit/e13c7d3b5bfd632b3a39217843b28e185c366fc2
Author: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/helper.h
M target/riscv/insn32.decode
A target/riscv/insn_trans/trans_rvvk.c.inc
M target/riscv/meson.build
M target/riscv/translate.c
A target/riscv/vcrypto_helper.c
Log Message:
-----------
target/riscv: Add Zvbc ISA extension support
This commit adds support for the Zvbc vector-crypto extension, which
consists of the following instructions:
* vclmulh.[vx,vv]
* vclmul.[vx,vv]
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.
Co-authored-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Co-authored-by: Max Chou <max.chou@sifive.com>
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Signed-off-by: Max Chou <max.chou@sifive.com>
[max.chou@sifive.com: Exposed x-zvbc property]
Message-ID: <20230711165917.2629866-5-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1ac7a501f0630cf4293a892d884791278fdbb88b
https://github.com/qemu/qemu/commit/1ac7a501f0630cf4293a892d884791278fdbb88b
Author: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: Move vector translation checks
Move the checks out of `do_opiv{v,x,i}_gvec{,_shift}` functions
and into the corresponding macros. This enables the functions to be
reused in proceeding commits without check duplication.
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20230711165917.2629866-6-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 62cb3e8e887bf279c7af5af4c971a44d2fd8a516
https://github.com/qemu/qemu/commit/62cb3e8e887bf279c7af5af4c971a44d2fd8a516
Author: Dickon Hood <dickon.hood@codethink.co.uk>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: Refactor translation of vector-widening instruction
Zvbb (implemented in later commit) has a widening instruction, which
requires an extra check on the enabled extensions. Refactor
GEN_OPIVX_WIDEN_TRANS() to take a check function to avoid reimplementing
it.
Signed-off-by: Dickon Hood <dickon.hood@codethink.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20230711165917.2629866-7-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 2152e48b501de38fcd497ef0188238e46e320f5f
https://github.com/qemu/qemu/commit/2152e48b501de38fcd497ef0188238e46e320f5f
Author: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M target/riscv/vector_helper.c
M target/riscv/vector_internals.h
Log Message:
-----------
target/riscv: Refactor some of the generic vector functionality
Move some macros out of `vector_helper` and into `vector_internals`.
This ensures they can be used by both vector and vector-crypto helpers
(latter implemented in proceeding commits).
Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20230711165917.2629866-8-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 0602847289feed9c5abd25ebe5604596c9d4bdbe
https://github.com/qemu/qemu/commit/0602847289feed9c5abd25ebe5604596c9d4bdbe
Author: Dickon Hood <dickon.hood@codethink.co.uk>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/helper.h
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvvk.c.inc
M target/riscv/vcrypto_helper.c
Log Message:
-----------
target/riscv: Add Zvbb ISA extension support
This commit adds support for the Zvbb vector-crypto extension, which
consists of the following instructions:
* vrol.[vv,vx]
* vror.[vv,vx,vi]
* vbrev8.v
* vrev8.v
* vandn.[vv,vx]
* vbrev.v
* vclz.v
* vctz.v
* vcpop.v
* vwsll.[vv,vx,vi]
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.
Co-authored-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Co-authored-by: William Salmon <will.salmon@codethink.co.uk>
Co-authored-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
[max.chou@sifive.com: Fix imm mode of vror.vi]
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Signed-off-by: William Salmon <will.salmon@codethink.co.uk>
Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Signed-off-by: Dickon Hood <dickon.hood@codethink.co.uk>
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
[max.chou@sifive.com: Exposed x-zvbb property]
Message-ID: <20230711165917.2629866-9-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e972bf22f6f00a1a145a2e2285095aa180beb143
https://github.com/qemu/qemu/commit/e972bf22f6f00a1a145a2e2285095aa180beb143
Author: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/helper.h
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvvk.c.inc
M target/riscv/vcrypto_helper.c
Log Message:
-----------
target/riscv: Add Zvkned ISA extension support
This commit adds support for the Zvkned vector-crypto extension, which
consists of the following instructions:
* vaesef.[vv,vs]
* vaesdf.[vv,vs]
* vaesdm.[vv,vs]
* vaesz.vs
* vaesem.[vv,vs]
* vaeskf1.vi
* vaeskf2.vi
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.
Co-authored-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Co-authored-by: William Salmon <will.salmon@codethink.co.uk>
[max.chou@sifive.com: Replaced vstart checking by TCG op]
Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Signed-off-by: William Salmon <will.salmon@codethink.co.uk>
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
[max.chou@sifive.com: Imported aes-round.h and exposed x-zvkned
property]
[max.chou@sifive.com: Fixed endian issues and replaced the vstart & vl
egs checking by helper function]
[max.chou@sifive.com: Replaced bswap32 calls in aes key expanding]
Message-ID: <20230711165917.2629866-10-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: fcf1943376a50a26382143da5f886609c0619d44
https://github.com/qemu/qemu/commit/fcf1943376a50a26382143da5f886609c0619d44
Author: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/helper.h
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvvk.c.inc
M target/riscv/vcrypto_helper.c
Log Message:
-----------
target/riscv: Add Zvknh ISA extension support
This commit adds support for the Zvknh vector-crypto extension, which
consists of the following instructions:
* vsha2ms.vv
* vsha2c[hl].vv
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.
Co-authored-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Co-authored-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
[max.chou@sifive.com: Replaced vstart checking by TCG op]
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
[max.chou@sifive.com: Exposed x-zvknha & x-zvknhb properties]
[max.chou@sifive.com: Replaced SEW selection to happened during
translation]
Message-ID: <20230711165917.2629866-11-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 2350881c44bdc7c72de6525dbfadddb93ebfd146
https://github.com/qemu/qemu/commit/2350881c44bdc7c72de6525dbfadddb93ebfd146
Author: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/helper.h
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvvk.c.inc
M target/riscv/vcrypto_helper.c
Log Message:
-----------
target/riscv: Add Zvksh ISA extension support
This commit adds support for the Zvksh vector-crypto extension, which
consists of the following instructions:
* vsm3me.vv
* vsm3c.vi
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.
Co-authored-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
[max.chou@sifive.com: Replaced vstart checking by TCG op]
Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
[max.chou@sifive.com: Exposed x-zvksh property]
Message-ID: <20230711165917.2629866-12-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 767eb03548f75b1d7c446305dd5bdb074c0b6d8f
https://github.com/qemu/qemu/commit/767eb03548f75b1d7c446305dd5bdb074c0b6d8f
Author: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/helper.h
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvvk.c.inc
M target/riscv/vcrypto_helper.c
Log Message:
-----------
target/riscv: Add Zvkg ISA extension support
This commit adds support for the Zvkg vector-crypto extension, which
consists of the following instructions:
* vgmul.vv
* vghsh.vv
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.
Co-authored-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
[max.chou@sifive.com: Replaced vstart checking by TCG op]
Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
[max.chou@sifive.com: Exposed x-zvkg property]
[max.chou@sifive.com: Replaced uint by int for cross win32 build]
Message-ID: <20230711165917.2629866-13-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: f6ef550fe5c915d1d74ce9854280d16a8d71e230
https://github.com/qemu/qemu/commit/f6ef550fe5c915d1d74ce9854280d16a8d71e230
Author: Max Chou <max.chou@sifive.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M include/crypto/sm4.h
M target/arm/tcg/crypto_helper.c
Log Message:
-----------
crypto: Create sm4_subword
Allows sharing of sm4_subword between different targets.
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20230711165917.2629866-14-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: f5f3a9152ae1242f5d1113852aa97d13b382815b
https://github.com/qemu/qemu/commit/f5f3a9152ae1242f5d1113852aa97d13b382815b
Author: Max Chou <max.chou@sifive.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M crypto/sm4.c
M include/crypto/sm4.h
Log Message:
-----------
crypto: Add SM4 constant parameter CK
Adds sm4_ck constant for use in sm4 cryptography across different targets.
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20230711165917.2629866-15-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 8b045ff45420d12bdbd9868e83559ffaaf059144
https://github.com/qemu/qemu/commit/8b045ff45420d12bdbd9868e83559ffaaf059144
Author: Max Chou <max.chou@sifive.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/helper.h
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvvk.c.inc
M target/riscv/vcrypto_helper.c
Log Message:
-----------
target/riscv: Add Zvksed ISA extension support
This commit adds support for the Zvksed vector-crypto extension, which
consists of the following instructions:
* vsm4k.vi
* vsm4r.[vv,vs]
Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
[lawrence.hunter@codethink.co.uk: Moved SM4 functions from
crypto_helper.c to vcrypto_helper.c]
[nazar.kazakov@codethink.co.uk: Added alignment checks, refactored code to
use macros, and minor style changes]
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20230711165917.2629866-16-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: ebe16b90395c70a8edbb7a0e855a8de2d3cfb4f9
https://github.com/qemu/qemu/commit/ebe16b90395c70a8edbb7a0e855a8de2d3cfb4f9
Author: Rob Bradford <rbradford@rivosinc.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren
These are WARL fields - zero out the bits for unavailable counters and
special case the TM bit in mcountinhibit which is hardwired to zero.
This patch achieves this by modifying the value written so that any use
of the field will see the correctly masked bits.
Tested by modifying OpenSBI to write max value to these CSRs and upon
subsequent read the appropriate number of bits for number of PMUs is
enabled and the TM bit is zero in mcountinhibit.
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Message-ID: <20230802124906.24197-1-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 0228aca23a96d869a889822ed4ded9ea6ea44f98
https://github.com/qemu/qemu/commit/0228aca23a96d869a889822ed4ded9ea6ea44f98
Author: Jason Chien <jason.chien@sifive.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
Log Message:
-----------
target/riscv: Add Zihintntl extension ISA string to DTS
RVA23 Profiles states:
The RVA23 profiles are intended to be used for 64-bit application
processors that will run rich OS stacks from standard binary OS
distributions and with a substantial number of third-party binary user
applications that will be supported over a considerable length of time
in the field.
The chapter 4 of the unprivileged spec introduces the Zihintntl extension
and Zihintntl is a mandatory extension presented in RVA23 Profiles, whose
purpose is to enable application and operating system portability across
different implementations. Thus the DTS should contain the Zihintntl ISA
string in order to pass to software.
The unprivileged spec states:
Like any HINTs, these instructions may be freely ignored. Hence, although
they are described in terms of cache-based memory hierarchies, they do not
mandate the provision of caches.
These instructions are encoded with non-used opcode, e.g. ADD x0, x0, x2,
which QEMU already supports, and QEMU does not emulate cache. Therefore
these instructions can be considered as a no-op, and we only need to add
a new property for the Zihintntl extension.
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Jason Chien <jason.chien@sifive.com>
Message-ID: <20230726074049.19505-2-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: eda633a534f8af4abe3a88731bba6dacdb973993
https://github.com/qemu/qemu/commit/eda633a534f8af4abe3a88731bba6dacdb973993
Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M target/riscv/insn_trans/trans_rvzfa.c.inc
Log Message:
-----------
target/riscv: Fix zfa fleq.d and fltq.d
Commit a47842d ("riscv: Add support for the Zfa extension") implemented the zfa
extension.
However, it has some typos for fleq.d and fltq.d. Both of them misused the
fltq.s
helper function.
Fixes: a47842d ("riscv: Add support for the Zfa extension")
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230728003906.768-1-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e0922b73baf00c4c19d4ad30d09bb94f7ffea0f4
https://github.com/qemu/qemu/commit/e0922b73baf00c4c19d4ad30d09bb94f7ffea0f4
Author: Jason Chien <jason.chien@sifive.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M hw/intc/riscv_aclint.c
Log Message:
-----------
hw/intc: Fix upper/lower mtime write calculation
When writing the upper mtime, we should keep the original lower mtime
whose value is given by cpu_riscv_read_rtc() instead of
cpu_riscv_read_rtc_raw(). The same logic applies to writes to lower mtime.
Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230728082502.26439-1-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9382a9eafccad8dc6a487ea3a8d2bed03dc35db9
https://github.com/qemu/qemu/commit/9382a9eafccad8dc6a487ea3a8d2bed03dc35db9
Author: Jason Chien <jason.chien@sifive.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M hw/intc/riscv_aclint.c
Log Message:
-----------
hw/intc: Make rtc variable names consistent
The variables whose values are given by cpu_riscv_read_rtc() should be named
"rtc". The variables whose value are given by cpu_riscv_read_rtc_raw()
should be named "rtc_r".
Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230728082502.26439-2-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: ae7d4d625cab49657b9fc2be09d895afb9bcdaf0
https://github.com/qemu/qemu/commit/ae7d4d625cab49657b9fc2be09d895afb9bcdaf0
Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M linux-user/riscv/signal.c
Log Message:
-----------
linux-user/riscv: Use abi type for target_ucontext
We should not use types dependend on host arch for target_ucontext.
This bug is found when run rv32 applications.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230811055438.1945-1-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 59a07d3c619bec722e8522be2c26f892fbf0cbd4
https://github.com/qemu/qemu/commit/59a07d3c619bec722e8522be2c26f892fbf0cbd4
Author: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
target/riscv: support the AIA device emulation with KVM enabled
In this patch, we create the APLIC and IMSIC FDT helper functions and
remove M mode AIA devices when using KVM acceleration.
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230727102439.22554-2-yongxuan.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 97b9f5ef144151e2e8917ea64aca74a5751745ef
https://github.com/qemu/qemu/commit/97b9f5ef144151e2e8917ea64aca74a5751745ef
Author: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M target/riscv/kvm.c
Log Message:
-----------
target/riscv: check the in-kernel irqchip support
We check the in-kernel irqchip support when using KVM acceleration.
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230727102439.22554-3-yongxuan.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9634ef7eda5f5b57f03924351a213b776f6b8a23
https://github.com/qemu/qemu/commit/9634ef7eda5f5b57f03924351a213b776f6b8a23
Author: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M target/riscv/kvm.c
M target/riscv/kvm_riscv.h
Log Message:
-----------
target/riscv: Create an KVM AIA irqchip
We create a vAIA chip by using the KVM_DEV_TYPE_RISCV_AIA and then set up
the chip with the KVM_DEV_RISCV_AIA_GRP_* APIs.
We also extend KVM accelerator to specify the KVM AIA mode. The "riscv-aia"
parameter is passed along with --accel in QEMU command-line.
1) "riscv-aia=emul": IMSIC is emulated by hypervisor
2) "riscv-aia=hwaccel": use hardware guest IMSIC
3) "riscv-aia=auto": use the hardware guest IMSICs whenever available
otherwise we fallback to software emulation.
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230727102439.22554-4-yongxuan.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 95a97b3fd25ee1c73a6bbfe0d47ac31864a95a4c
https://github.com/qemu/qemu/commit/95a97b3fd25ee1c73a6bbfe0d47ac31864a95a4c
Author: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M hw/intc/riscv_aplic.c
M hw/intc/riscv_imsic.c
Log Message:
-----------
target/riscv: update APLIC and IMSIC to support KVM AIA
KVM AIA can't emulate APLIC only. When "aia=aplic" parameter is passed,
APLIC devices is emulated by QEMU. For "aia=aplic-imsic", remove the
mmio operations of APLIC when using KVM AIA and send wired interrupt
signal via KVM_IRQ_LINE API.
After KVM AIA enabled, MSI messages are delivered by KVM_SIGNAL_MSI API
when the IMSICs receive mmio write requests.
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230727102439.22554-5-yongxuan.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 48c2c33c52cd019f6e3c3c916b9777002905a4ef
https://github.com/qemu/qemu/commit/48c2c33c52cd019f6e3c3c916b9777002905a4ef
Author: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
target/riscv: select KVM AIA in riscv virt machine
Select KVM AIA when the host kernel has in-kernel AIA chip support.
Since KVM AIA only has one APLIC instance, we map the QEMU APLIC
devices to KVM APLIC.
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230727102439.22554-6-yongxuan.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9ff31406312500053ecb5f92df01dd9ce52e635d
https://github.com/qemu/qemu/commit/9ff31406312500053ecb5f92df01dd9ce52e635d
Author: Conor Dooley <conor.dooley@microchip.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv: virt: Fix riscv,pmu DT node path
On a dtb dumped from the virt machine, dt-validate complains:
soc: pmu: {'riscv,event-to-mhpmcounters': [[1, 1, 524281], [2, 2, 524284],
[65561, 65561, 524280], [65563, 65563, 524280], [65569, 65569, 524280]],
'compatible': ['riscv,pmu']} should not be valid under {'type': 'object'}
from schema $id: http://devicetree.org/schemas/simple-bus.yaml#
That's pretty cryptic, but running the dtb back through dtc produces
something a lot more reasonable:
Warning (simple_bus_reg): /soc/pmu: missing or empty reg/ranges property
Moving the riscv,pmu node out of the soc bus solves the problem.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230727-groom-decline-2c57ce42841c@spud>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: ed67d63798f2ff31a7541ed97ac671c8e1f79297
https://github.com/qemu/qemu/commit/ed67d63798f2ff31a7541ed97ac671c8e1f79297
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_bits.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Update CSR bits name for svadu extension
The Svadu specification updated the name of the *envcfg bit from
HADE to ADUE.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230816141916.66898-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 3a2fc23563885c219c73c8f24318921daf02f3f2
https://github.com/qemu/qemu/commit/3a2fc23563885c219c73c8f24318921daf02f3f2
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0
In the same emulated RISC-V host, the 'host' KVM CPU takes 4 times
longer to boot than the 'rv64' KVM CPU.
The reason is an unintended behavior of riscv_cpu_satp_mode_finalize()
when satp_mode.supported = 0, i.e. when cpu_init() does not set
satp_mode_max_supported(). satp_mode_max_from_map(map) does:
31 - __builtin_clz(map)
This means that, if satp_mode.supported = 0, satp_mode_supported_max
wil be '31 - 32'. But this is C, so satp_mode_supported_max will gladly
set it to UINT_MAX (4294967295). After that, if the user didn't set a
satp_mode, set_satp_mode_default_map(cpu) will make
cfg.satp_mode.map = cfg.satp_mode.supported
So satp_mode.map = 0. And then satp_mode_map_max will be set to
satp_mode_max_from_map(cpu->cfg.satp_mode.map), i.e. also UINT_MAX. The
guard "satp_mode_map_max > satp_mode_supported_max" doesn't protect us
here since both are UINT_MAX.
And finally we have 2 loops:
for (int i = satp_mode_map_max - 1; i >= 0; --i) {
Which are, in fact, 2 loops from UINT_MAX -1 to -1. This is where the
extra delay when booting the 'host' CPU is coming from.
Commit 43d1de32f8 already set a precedence for satp_mode.supported = 0
in a different manner. We're doing the same here. If supported == 0,
interpret as 'the CPU wants the OS to handle satp mode alone' and skip
satp_mode_finalize().
We'll also put a guard in satp_mode_max_from_map() to assert out if map
is 0 since the function is not ready to deal with it.
Cc: Alexandre Ghiti <alexghiti@rivosinc.com>
Fixes: 6f23aaeb9b ("riscv: Allow user to set the satp mode")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230817152903.694926-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c3443f8323638f566a503f67e3b38d55d1f692c5
https://github.com/qemu/qemu/commit/c3443f8323638f566a503f67e3b38d55d1f692c5
Author: Vineet Gupta <vineetg@rivosinc.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
riscv: zicond: make non-experimental
zicond is now codegen supported in both llvm and gcc.
This change allows seamless enabling/testing of zicond in downstream
projects. e.g. currently riscv-gnu-toolchain parses elf attributes
to create a cmdline for qemu but fails short of enabling it because of
the "x-" prefix.
Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
Message-ID: <20230808181715.436395-1-vineetg@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a51d46102844348b36d583705bdb631879df6fe3
https://github.com/qemu/qemu/commit/a51d46102844348b36d583705bdb631879df6fe3
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt.c: fix non-KVM --enable-debug build
A build with --enable-debug and without KVM will fail as follows:
/usr/bin/ld: libqemu-riscv64-softmmu.fa.p/hw_riscv_virt.c.o: in function
`virt_machine_init':
./qemu/build/../hw/riscv/virt.c:1465: undefined reference to
`kvm_riscv_aia_create'
This happens because the code block with "if virt_use_kvm_aia(s)" isn't
being ignored by the debug build, resulting in an undefined reference to
a KVM only function.
Add a 'kvm_enabled()' conditional together with virt_use_kvm_aia() will
make the compiler crop the kvm_riscv_aia_create() call entirely from a
non-KVM build. Note that adding the 'kvm_enabled()' conditional inside
virt_use_kvm_aia() won't fix the build because this function would need
to be inlined multiple times to make the compiler zero out the entire
block.
While we're at it, use kvm_enabled() in all instances where
virt_use_kvm_aia() is checked to allow the compiler to elide these other
kvm-only instances as well.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Fixes: dbdb99948e ("target/riscv: select KVM AIA in riscv virt machine")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230830133503.711138-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b815664091cced7ba89fce4e5b6544d16fed3d98
https://github.com/qemu/qemu/commit/b815664091cced7ba89fce4e5b6544d16fed3d98
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M hw/intc/riscv_aplic.c
M target/riscv/kvm.c
M target/riscv/kvm_riscv.h
Log Message:
-----------
hw/intc/riscv_aplic.c fix non-KVM --enable-debug build
Commit 6df0b37e2ab breaks a --enable-debug build in a non-KVM
environment with the following error:
/usr/bin/ld: libqemu-riscv64-softmmu.fa.p/hw_intc_riscv_aplic.c.o: in function
`riscv_kvm_aplic_request':
./qemu/build/../hw/intc/riscv_aplic.c:486: undefined reference to `kvm_set_irq'
collect2: error: ld returned 1 exit status
This happens because the debug build will poke into the
'if (is_kvm_aia(aplic->msimode))' block and fail to find a reference to
the KVM only function riscv_kvm_aplic_request().
There are multiple solutions to fix this. We'll go with the same
solution from the previous patch, i.e. add a kvm_enabled() conditional
to filter out the block. But there's a catch: riscv_kvm_aplic_request()
is a local function that would end up being used if the compiler crops
the block, and this won't work. Quoting Richard Henderson's explanation
in [1]:
"(...) the compiler won't eliminate entire unused functions with -O0"
We'll solve it by moving riscv_kvm_aplic_request() to kvm.c and add its
declaration in kvm_riscv.h, where all other KVM specific public
functions are already declared. Other archs handles KVM specific code in
this manner and we expect to do the same from now on.
[1]
https://lore.kernel.org/qemu-riscv/d2f1ad02-eb03-138f-9d08-db676deeed05@linaro.org/
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230830133503.711138-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: bb0a45e931967488949d293faa5ff4f4561fbdd4
https://github.com/qemu/qemu/commit/bb0a45e931967488949d293faa5ff4f4561fbdd4
Author: Robbin Ehn <rehn@rivosinc.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M linux-user/syscall.c
Log Message:
-----------
linux-user/riscv: Add new extensions to hwprobe
This patch adds the new extensions in
linux 6.5 to the hwprobe syscall.
And fixes RVC check to OR with correct value.
The previous variable contains 0 therefore it
did work.
Signed-off-by: Robbin Ehn <rehn@rivosinc.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <bc82203b72d7efb30f1b4a8f9eb3d94699799dc8.camel@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 7d496bb50233d861032fb22b4fae050b246c9197
https://github.com/qemu/qemu/commit/7d496bb50233d861032fb22b4fae050b246c9197
Author: Ard Biesheuvel <ardb@kernel.org>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M target/riscv/crypto_helper.c
Log Message:
-----------
target/riscv: Use accelerated helper for AES64KS1I
Use the accelerated SubBytes/ShiftRows/AddRoundKey AES helper to
implement the first half of the key schedule derivation. This does not
actually involve shifting rows, so clone the same value into all four
columns of the AES vector to counter that operation.
Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Philippe Mathieu-Daudé <philmd@linaro.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230831154118.138727-1-ardb@kernel.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a7c272df82af11c568ea83921b04334791dccd5e
https://github.com/qemu/qemu/commit/a7c272df82af11c568ea83921b04334791dccd5e
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/debug.c
M target/riscv/debug.h
Log Message:
-----------
target/riscv: Allocate itrigger timers only once
riscv_trigger_init() had been called on reset events that can happen
several times for a CPU and it allocated timers for itrigger. If old
timers were present, they were simply overwritten by the new timers,
resulting in a memory leak.
Divide riscv_trigger_init() into two functions, namely
riscv_trigger_realize() and riscv_trigger_reset() and call them in
appropriate timing. The timer allocation will happen only once for a
CPU in riscv_trigger_realize().
Fixes: 5a4ae64cac ("target/riscv: Add itrigger support when icount is enabled")
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230818034059.9146-1-akihiko.odaki@daynix.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4e3adce1244e1ca30ec05874c3eca14911dc0825
https://github.com/qemu/qemu/commit/4e3adce1244e1ca30ec05874c3eca14911dc0825
Author: Leon Schuermann <leons@opentitan.org>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M target/riscv/pmp.c
Log Message:
-----------
target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes
When the rule-lock bypass (RLB) bit is set in the mseccfg CSR, the PMP
configuration lock bits must not apply. While this behavior is
implemented for the pmpcfgX CSRs, this bit is not respected for
changes to the pmpaddrX CSRs. This patch ensures that pmpaddrX CSR
writes work even on locked regions when the global rule-lock bypass is
enabled.
Signed-off-by: Leon Schuermann <leons@opentitan.org>
Reviewed-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230829215046.1430463-1-leon@is.currently.online>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4df282335b3b13db30123fbcca050e4bf690a9d9
https://github.com/qemu/qemu/commit/4df282335b3b13db30123fbcca050e4bf690a9d9
Author: Tommy Wu <tommy.wu@sifive.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Align the AIA model to v1.0 ratified spec
According to the new spec, when vsiselect has a reserved value, attempts
from M-mode or HS-mode to access vsireg, or from VS-mode to access
sireg, should preferably raise an illegal instruction exception.
Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-ID: <20230816061647.600672-1-tommy.wu@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e7a03409f29e2da59297d55afbaec98c96e43e3a
https://github.com/qemu/qemu/commit/e7a03409f29e2da59297d55afbaec98c96e43e3a
Author: Nikita Shubin <n.shubin@yadro.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: don't read CSR in riscv_csrrw_do64
As per ISA:
"For CSRRWI, if rd=x0, then the instruction shall not read the CSR and
shall not cause any of the side effects that might occur on a CSR read."
trans_csrrwi() and trans_csrrw() call do_csrw() if rd=x0, do_csrw() calls
riscv_csrrw_do64(), via helper_csrw() passing NULL as *ret_value.
Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230808090914.17634-1-nikita.shubin@maquefel.me>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 5485298ce0978458839a9a7f0f227f7ed64a025f
https://github.com/qemu/qemu/commit/5485298ce0978458839a9a7f0f227f7ed64a025f
Author: Avihai Horon <avihaih@nvidia.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M hw/vfio/migration.c
Log Message:
-----------
vfio/migration: Move from STOP_COPY to STOP in vfio_save_cleanup()
Changing the device state from STOP_COPY to STOP can take time as the
device may need to free resources and do other operations as part of the
transition. Currently, this is done in vfio_save_complete_precopy() and
therefore it is counted in the migration downtime.
To avoid this, change the device state from STOP_COPY to STOP in
vfio_save_cleanup(), which is called after migration has completed and
thus is not part of migration downtime.
Signed-off-by: Avihai Horon <avihaih@nvidia.com>
Tested-by: YangHang Liu <yanghliu@redhat.com>
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Commit: 9d3103c81be307b3953f7e3f53ed0f742e9d786c
https://github.com/qemu/qemu/commit/9d3103c81be307b3953f7e3f53ed0f742e9d786c
Author: Avihai Horon <avihaih@nvidia.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M include/sysemu/runstate.h
M softmmu/runstate.c
Log Message:
-----------
sysemu: Add prepare callback to struct VMChangeStateEntry
Add prepare callback to struct VMChangeStateEntry.
The prepare callback is optional and can be set by the new function
qemu_add_vm_change_state_handler_prio_full() that allows setting this
callback in addition to the main callback.
The prepare callbacks and main callbacks are called in two separate
phases: First all prepare callbacks are called and only then all main
callbacks are called.
The purpose of the new prepare callback is to allow all devices to run a
preliminary task before calling the devices' main callbacks.
This will facilitate adding P2P support for VFIO migration where all
VFIO devices need to be put in an intermediate P2P quiescent state
before being stopped or started by the main callback.
Signed-off-by: Avihai Horon <avihaih@nvidia.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Tested-by: YangHang Liu <yanghliu@redhat.com>
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Commit: 02b2e25360ea1f10a337ddaf686eb770eebf59de
https://github.com/qemu/qemu/commit/02b2e25360ea1f10a337ddaf686eb770eebf59de
Author: Avihai Horon <avihaih@nvidia.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M hw/core/vm-change-state-handler.c
M include/sysemu/runstate.h
Log Message:
-----------
qdev: Add qdev_add_vm_change_state_handler_full()
Add qdev_add_vm_change_state_handler_full() variant that allows setting
a prepare callback in addition to the main callback.
This will facilitate adding P2P support for VFIO migration in the
following patches.
Signed-off-by: Avihai Horon <avihaih@nvidia.com>
Signed-off-by: Joao Martins <joao.m.martins@oracle.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Tested-by: YangHang Liu <yanghliu@redhat.com>
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Commit: 3d4d0f0e06630d0098e7940323fe0f96ff87f34f
https://github.com/qemu/qemu/commit/3d4d0f0e06630d0098e7940323fe0f96ff87f34f
Author: Joao Martins <joao.m.martins@oracle.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M hw/vfio/common.c
M hw/vfio/migration.c
M include/hw/vfio/vfio-common.h
Log Message:
-----------
vfio/migration: Refactor PRE_COPY and RUNNING state checks
Move the PRE_COPY and RUNNING state checks to helper functions.
This is in preparation for adding P2P VFIO migration support, where
these helpers will also test for PRE_COPY_P2P and RUNNING_P2P states.
Signed-off-by: Joao Martins <joao.m.martins@oracle.com>
Signed-off-by: Avihai Horon <avihaih@nvidia.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Tested-by: YangHang Liu <yanghliu@redhat.com>
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Commit: 94f775e428f8057ee66425f421b68fe8c94cebcc
https://github.com/qemu/qemu/commit/94f775e428f8057ee66425f421b68fe8c94cebcc
Author: Avihai Horon <avihaih@nvidia.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M docs/devel/vfio-migration.rst
M hw/vfio/common.c
M hw/vfio/migration.c
M hw/vfio/trace-events
Log Message:
-----------
vfio/migration: Add P2P support for VFIO migration
VFIO migration uAPI defines an optional intermediate P2P quiescent
state. While in the P2P quiescent state, P2P DMA transactions cannot be
initiated by the device, but the device can respond to incoming ones.
Additionally, all outstanding P2P transactions are guaranteed to have
been completed by the time the device enters this state.
The purpose of this state is to support migration of multiple devices
that might do P2P transactions between themselves.
Add support for P2P migration by transitioning all the devices to the
P2P quiescent state before stopping or starting the devices. Use the new
VMChangeStateHandler prepare_cb to achieve that behavior.
This will allow migration of multiple VFIO devices if all of them
support P2P migration.
Signed-off-by: Avihai Horon <avihaih@nvidia.com>
Tested-by: YangHang Liu <yanghliu@redhat.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Commit: 5c7a4b60350e509109bea4b86cdcf1d034cd4d5c
https://github.com/qemu/qemu/commit/5c7a4b60350e509109bea4b86cdcf1d034cd4d5c
Author: Avihai Horon <avihaih@nvidia.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M hw/vfio/common.c
Log Message:
-----------
vfio/migration: Allow migration of multiple P2P supporting devices
Now that P2P support has been added to VFIO migration, allow migration
of multiple devices if all of them support P2P migration.
Single device migration is allowed regardless of P2P migration support.
Signed-off-by: Avihai Horon <avihaih@nvidia.com>
Signed-off-by: Joao Martins <joao.m.martins@oracle.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Tested-by: YangHang Liu <yanghliu@redhat.com>
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Commit: 38c482b4778595ee337761f73ec0730d6c47b404
https://github.com/qemu/qemu/commit/38c482b4778595ee337761f73ec0730d6c47b404
Author: Avihai Horon <avihaih@nvidia.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M migration/migration.c
M migration/migration.h
M migration/savevm.c
M migration/target.c
Log Message:
-----------
migration: Add migration prefix to functions in target.c
The functions in target.c are not static, yet they don't have a proper
migration prefix. Add such prefix.
Signed-off-by: Avihai Horon <avihaih@nvidia.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Commit: 8118349b1bc5c12e4017ddd7eb563fce752a5a9c
https://github.com/qemu/qemu/commit/8118349b1bc5c12e4017ddd7eb563fce752a5a9c
Author: Avihai Horon <avihaih@nvidia.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M hw/vfio/common.c
Log Message:
-----------
vfio/migration: Fail adding device with enable-migration=on and existing
blocker
If a device with enable-migration=on is added and it causes a migration
blocker, adding the device should fail with a proper error.
This is not the case with multiple device migration blocker when the
blocker already exists. If the blocker already exists and a device with
enable-migration=on is added which causes a migration blocker, adding
the device will succeed.
Fix it by failing adding the device in such case.
Fixes: 8bbcb64a71d8 ("vfio/migration: Make VFIO migration non-experimental")
Signed-off-by: Avihai Horon <avihaih@nvidia.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Commit: f543aa222da183ac37424d1ea3a65e5fb6202732
https://github.com/qemu/qemu/commit/f543aa222da183ac37424d1ea3a65e5fb6202732
Author: Avihai Horon <avihaih@nvidia.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M migration/migration.c
M migration/savevm.c
Log Message:
-----------
migration: Move more initializations to migrate_init()
Initialization of mig_stats, compression_counters and VFIO bytes
transferred is hard-coded in migration code path and snapshot code path.
Make the code cleaner by initializing them in migrate_init().
Suggested-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Avihai Horon <avihaih@nvidia.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Commit: 08fc4cb51774f763dcc6fd74637aa9e00eb6a0ba
https://github.com/qemu/qemu/commit/08fc4cb51774f763dcc6fd74637aa9e00eb6a0ba
Author: Avihai Horon <avihaih@nvidia.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M include/migration/register.h
M migration/migration.c
M migration/migration.h
M migration/savevm.c
M migration/savevm.h
Log Message:
-----------
migration: Add .save_prepare() handler to struct SaveVMHandlers
Add a new .save_prepare() handler to struct SaveVMHandlers. This handler
is called early, even before migration starts, and can be used by
devices to perform early checks.
Refactor migrate_init() to be able to return errors and call
.save_prepare() from there.
Suggested-by: Peter Xu <peterx@redhat.com>
Signed-off-by: Avihai Horon <avihaih@nvidia.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Commit: bf7ef7a2da3e61dc104f26c679c9465e3fbe7dde
https://github.com/qemu/qemu/commit/bf7ef7a2da3e61dc104f26c679c9465e3fbe7dde
Author: Avihai Horon <avihaih@nvidia.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M hw/vfio/migration.c
Log Message:
-----------
vfio/migration: Block VFIO migration with postcopy migration
VFIO migration is not compatible with postcopy migration. A VFIO device
in the destination can't handle page faults for pages that have not been
sent yet.
Doing such migration will cause the VM to crash in the destination:
qemu-system-x86_64: VFIO_MAP_DMA failed: Bad address
qemu-system-x86_64: vfio_dma_map(0x55a28c7659d0, 0xc0000, 0xb000,
0x7f1b11a00000) = -14 (Bad address)
qemu: hardware error: vfio: DMA mapping failed, unable to continue
To prevent this, block VFIO migration with postcopy migration.
Reported-by: Yanghang Liu <yanghliu@redhat.com>
Signed-off-by: Avihai Horon <avihaih@nvidia.com>
Tested-by: Yanghang Liu <yanghliu@redhat.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Commit: 615379764ae67f30a0fcbffeb20d6645f010091c
https://github.com/qemu/qemu/commit/615379764ae67f30a0fcbffeb20d6645f010091c
Author: Avihai Horon <avihaih@nvidia.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M hw/vfio/migration.c
Log Message:
-----------
vfio/migration: Block VFIO migration with background snapshot
Background snapshot allows creating a snapshot of the VM while it's
running and keeping it small by not including dirty RAM pages.
The way it works is by first stopping the VM, saving the non-iterable
devices' state and then starting the VM and saving the RAM while write
protecting it with UFFD. The resulting snapshot represents the VM state
at snapshot start.
VFIO migration is not compatible with background snapshot.
First of all, VFIO device state is not even saved in background snapshot
because only non-iterable device state is saved. But even if it was
saved, after starting the VM, a VFIO device could dirty pages without it
being detected by UFFD write protection. This would corrupt the
snapshot, as the RAM in it would not represent the RAM at snapshot
start.
To prevent this, block VFIO migration with background snapshot.
Signed-off-by: Avihai Horon <avihaih@nvidia.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Commit: a31fe5daeaa230556145bfc04af1bd4e68f377fa
https://github.com/qemu/qemu/commit/a31fe5daeaa230556145bfc04af1bd4e68f377fa
Author: Joao Martins <joao.m.martins@oracle.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M hw/vfio/common.c
M hw/vfio/trace-events
Log Message:
-----------
vfio/common: Separate vfio-pci ranges
QEMU computes the DMA logging ranges for two predefined ranges: 32-bit
and 64-bit. In the OVMF case, when the dynamic MMIO window is enabled,
QEMU includes in the 64-bit range the RAM regions at the lower part
and vfio-pci device RAM regions which are at the top of the address
space. This range contains a large gap and the size can be bigger than
the dirty tracking HW limits of some devices (MLX5 has a 2^42 limit).
To avoid such large ranges, introduce a new PCI range covering the
vfio-pci device RAM regions, this only if the addresses are above 4GB
to avoid breaking potential SeaBIOS guests.
[ clg: - wrote commit log
- fixed overlapping 32-bit and PCI ranges when using SeaBIOS ]
Signed-off-by: Joao Martins <joao.m.martins@oracle.com>
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Fixes: 5255bbf4ec16 ("vfio/common: Add device dirty page tracking start/stop")
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Commit: a7e8e30e7ca071c8fbf8920a7a4ee9976a0e7544
https://github.com/qemu/qemu/commit/a7e8e30e7ca071c8fbf8920a7a4ee9976a0e7544
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M MAINTAINERS
M accel/kvm/kvm-all.c
M docs/system/arm/cpu-features.rst
M docs/system/arm/emulation.rst
M docs/system/arm/virt.rst
M hw/arm/virt.c
M hw/arm/xlnx-versal.c
M hw/intc/arm_gicv3_its.c
M hw/misc/meson.build
A hw/misc/xlnx-cfi-if.c
A hw/misc/xlnx-versal-cframe-reg.c
A hw/misc/xlnx-versal-cfu.c
M include/hw/arm/xlnx-versal.h
A include/hw/misc/xlnx-cfi-if.h
A include/hw/misc/xlnx-versal-cframe-reg.h
A include/hw/misc/xlnx-versal-cfu.h
M include/sysemu/kvm_int.h
M qemu-options.hx
M target/arm/arm-qmp-cmds.c
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper.c
M target/arm/helper.h
M target/arm/hvf/hvf.c
M target/arm/kvm.c
M target/arm/kvm64.c
M target/arm/syndrome.h
M target/arm/tcg/cpu64.c
M target/arm/tcg/helper-a64.h
M target/arm/tcg/op_helper.c
M target/arm/tcg/pauth_helper.c
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate.c
M tests/qtest/arm-cpu-features.c
M tests/tcg/aarch64/Makefile.target
M tests/tcg/aarch64/pauth-2.c
M tests/tcg/aarch64/pauth-4.c
M tests/tcg/aarch64/pauth-5.c
A tests/tcg/aarch64/pauth.h
Log Message:
-----------
Merge tag 'pull-target-arm-20230908' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* New CPU type: cortex-a710
* Implement new architectural features:
- FEAT_PACQARMA3
- FEAT_EPAC
- FEAT_Pauth2
- FEAT_FPAC
- FEAT_FPACCOMBINE
- FEAT_TIDCP1
* Xilinx Versal: Model the CFU/CFI
* Implement RMR_ELx registers
* Implement handling of HCR_EL2.TIDCP trap bit
* arm/kvm: Enable support for KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE
* hw/intc/arm_gicv3_its: Avoid maybe-uninitialized error in get_vte()
* target/arm: Do not use gen_mte_checkN in trans_STGP
* arm64: Restore trapless ptimer access
# -----BEGIN PGP SIGNATURE-----
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# kh+aFEdKajPp56UseJiKBQ==
# =5Shq
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 08 Sep 2023 13:05:13 EDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20230908' of
https://git.linaro.org/people/pmaydell/qemu-arm: (26 commits)
arm/kvm: Enable support for KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE
target/arm: Enable SCTLR_EL1.TIDCP for user-only
target/arm: Implement FEAT_TIDCP1
target/arm: Implement HCR_EL2.TIDCP
target/arm: Implement cortex-a710
target/arm: Implement RMR_ELx
arm64: Restore trapless ptimer access
target/arm: Do not use gen_mte_checkN in trans_STGP
hw/arm/versal: Connect the CFRAME_REG and CFRAME_BCAST_REG
hw/arm/xlnx-versal: Connect the CFU_APB, CFU_FDRO and CFU_SFR
hw/misc: Introduce a model of Xilinx Versal's CFRAME_BCAST_REG
hw/misc: Introduce a model of Xilinx Versal's CFRAME_REG
hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal's CFU_SFR
hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal CFU_FDRO
hw/misc: Introduce a model of Xilinx Versal's CFU_APB
hw/misc: Introduce the Xilinx CFI interface
hw/intc/arm_gicv3_its: Avoid maybe-uninitialized error in get_vte()
target/arm: Implement FEAT_FPAC and FEAT_FPACCOMBINE
target/arm: Inform helpers whether a PAC instruction is 'combined'
target/arm: Implement FEAT_Pauth2
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 78f8b6d9c88740d7e6ec8300a936f17460e41008
https://github.com/qemu/qemu/commit/78f8b6d9c88740d7e6ec8300a936f17460e41008
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M block.c
M block/copy-before-write.c
M block/io.c
M block/iscsi.c
M block/meson.build
M block/preallocate.c
M block/qapi.c
M block/snapshot-access.c
M block/vmdk.c
M block/vpc.c
M docs/tools/qemu-img.rst
M hw/virtio/virtio.c
M include/block/block_int-common.h
M include/block/qapi.h
M include/migration/vmstate.h
M qemu-img.c
M tests/qemu-iotests/080.out
M tests/qemu-iotests/109.out
M tests/qemu-iotests/112.out
M tests/qemu-iotests/185
M tests/qemu-iotests/185.out
M tests/qemu-iotests/244.out
Log Message:
-----------
Merge tag 'for-upstream' of https://repo.or.cz/qemu/kevin into staging
Block layer patches
- Optimise reqs_lock to make multiqueue actually scale
- virtio: Drop out of coroutine context in virtio_load()
- iotests: Fix reference output for some tests after recent changes
- vpc: Avoid dynamic stack allocation
- Code cleanup, improved documentation
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# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 08 Sep 2023 13:10:32 EDT
# gpg: using RSA key DC3DEB159A9AF95D3D7456FE7F09B272C88F2FD6
# gpg: issuer "kwolf@redhat.com"
# gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" [full]
# Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6
* tag 'for-upstream' of https://repo.or.cz/qemu/kevin:
virtio: Drop out of coroutine context in virtio_load()
vmstate: Mark VMStateInfo.get/put() coroutine_mixed_fn
block: Make more BlockDriver definitions static
block/meson.build: Restore alphabetical order of files
block: Remove unnecessary variable in bdrv_block_device_info
block: Remove bdrv_query_block_node_info
vmdk: Clean up bdrv_open_child() return value check
qemu-img: Update documentation for compressed images
block: Be more verbose in create fallback
block/iscsi: Document why we use raw malloc()
qemu-img: omit errno value in error message
block: change reqs_lock to QemuMutex
block: minimize bs->reqs_lock section in tracked_request_end()
iotests: adapt test output for new qemu_cleanup() behavior
block/vpc: Avoid dynamic stack allocation
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: cb6c406e26e3cbe394f244d8ac42fd6497eaf129
https://github.com/qemu/qemu/commit/cb6c406e26e3cbe394f244d8ac42fd6497eaf129
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M crypto/aes.c
M crypto/sm4.c
M hw/char/riscv_htif.c
M hw/intc/riscv_aclint.c
M hw/intc/riscv_aplic.c
M hw/intc/riscv_imsic.c
M hw/riscv/virt.c
M include/crypto/aes.h
M include/crypto/sm4.h
M linux-user/riscv/signal.c
M linux-user/syscall.c
M target/arm/tcg/crypto_helper.c
M target/riscv/cpu.c
M target/riscv/cpu_bits.h
M target/riscv/cpu_cfg.h
M target/riscv/cpu_helper.c
M target/riscv/crypto_helper.c
M target/riscv/csr.c
M target/riscv/debug.c
M target/riscv/debug.h
M target/riscv/helper.h
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvv.c.inc
A target/riscv/insn_trans/trans_rvvk.c.inc
M target/riscv/insn_trans/trans_rvzfa.c.inc
M target/riscv/kvm.c
M target/riscv/kvm_riscv.h
M target/riscv/meson.build
M target/riscv/pmp.c
M target/riscv/translate.c
A target/riscv/vcrypto_helper.c
M target/riscv/vector_helper.c
A target/riscv/vector_internals.c
A target/riscv/vector_internals.h
Log Message:
-----------
Merge tag 'pull-riscv-to-apply-20230911' of
https://github.com/alistair23/qemu into staging
First RISC-V PR for 8.2
* Remove 'host' CPU from TCG
* riscv_htif Fixup printing on big endian hosts
* Add zmmul isa string
* Add smepmp isa string
* Fix page_check_range use in fault-only-first
* Use existing lookup tables for MixColumns
* Add RISC-V vector cryptographic instruction set support
* Implement WARL behaviour for mcountinhibit/mcounteren
* Add Zihintntl extension ISA string to DTS
* Fix zfa fleq.d and fltq.d
* Fix upper/lower mtime write calculation
* Make rtc variable names consistent
* Use abi type for linux-user target_ucontext
* Add RISC-V KVM AIA Support
* Fix riscv,pmu DT node path in the virt machine
* Update CSR bits name for svadu extension
* Mark zicond non-experimental
* Fix satp_mode_finalize() when satp_mode.supported = 0
* Fix non-KVM --enable-debug build
* Add new extensions to hwprobe
* Use accelerated helper for AES64KS1I
* Allocate itrigger timers only once
* Respect mseccfg.RLB for pmpaddrX changes
* Align the AIA model to v1.0 ratified spec
* Don't read the CSR in riscv_csrrw_do64
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# gpg: Signature made Mon 11 Sep 2023 02:42:27 EDT
# gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013
* tag 'pull-riscv-to-apply-20230911' of https://github.com/alistair23/qemu: (45
commits)
target/riscv: don't read CSR in riscv_csrrw_do64
target/riscv: Align the AIA model to v1.0 ratified spec
target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes
target/riscv: Allocate itrigger timers only once
target/riscv: Use accelerated helper for AES64KS1I
linux-user/riscv: Add new extensions to hwprobe
hw/intc/riscv_aplic.c fix non-KVM --enable-debug build
hw/riscv/virt.c: fix non-KVM --enable-debug build
riscv: zicond: make non-experimental
target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0
target/riscv: Update CSR bits name for svadu extension
hw/riscv: virt: Fix riscv,pmu DT node path
target/riscv: select KVM AIA in riscv virt machine
target/riscv: update APLIC and IMSIC to support KVM AIA
target/riscv: Create an KVM AIA irqchip
target/riscv: check the in-kernel irqchip support
target/riscv: support the AIA device emulation with KVM enabled
linux-user/riscv: Use abi type for target_ucontext
hw/intc: Make rtc variable names consistent
hw/intc: Fix upper/lower mtime write calculation
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 9ef497755afc252fb8e060c9ea6b0987abfd20b6
https://github.com/qemu/qemu/commit/9ef497755afc252fb8e060c9ea6b0987abfd20b6
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-09-11 (Mon, 11 Sep 2023)
Changed paths:
M docs/devel/vfio-migration.rst
M hw/core/vm-change-state-handler.c
M hw/vfio/common.c
M hw/vfio/migration.c
M hw/vfio/trace-events
M include/hw/vfio/vfio-common.h
M include/migration/register.h
M include/sysemu/runstate.h
M migration/migration.c
M migration/migration.h
M migration/savevm.c
M migration/savevm.h
M migration/target.c
M softmmu/runstate.c
Log Message:
-----------
Merge tag 'pull-vfio-20230911' of https://github.com/legoater/qemu into
staging
vfio queue:
* Small downtime optimisation for VFIO migration
* P2P support for VFIO migration
* Introduction of a save_prepare() handler to fail VFIO migration
* Fix on DMA logging ranges calculation for OVMF enabling dynamic window
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# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 11 Sep 2023 02:54:12 EDT
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [unknown]
# gpg: aka "Cédric Le Goater <clg@kaod.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* tag 'pull-vfio-20230911' of https://github.com/legoater/qemu:
vfio/common: Separate vfio-pci ranges
vfio/migration: Block VFIO migration with background snapshot
vfio/migration: Block VFIO migration with postcopy migration
migration: Add .save_prepare() handler to struct SaveVMHandlers
migration: Move more initializations to migrate_init()
vfio/migration: Fail adding device with enable-migration=on and existing
blocker
migration: Add migration prefix to functions in target.c
vfio/migration: Allow migration of multiple P2P supporting devices
vfio/migration: Add P2P support for VFIO migration
vfio/migration: Refactor PRE_COPY and RUNNING state checks
qdev: Add qdev_add_vm_change_state_handler_full()
sysemu: Add prepare callback to struct VMChangeStateEntry
vfio/migration: Move from STOP_COPY to STOP in vfio_save_cleanup()
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Compare: https://github.com/qemu/qemu/compare/c5ea91da443b...9ef497755afc