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[Qemu-commits] [qemu/qemu] 565f85: ui/gtk: force realization of drawing
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From: |
Alex Bennée |
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Subject: |
[Qemu-commits] [qemu/qemu] 565f85: ui/gtk: force realization of drawing area |
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Date: |
Tue, 07 Nov 2023 03:02:15 -0800 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 565f85a9c293818a91a3d3414311303de7e00cec
https://github.com/qemu/qemu/commit/565f85a9c293818a91a3d3414311303de7e00cec
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M ui/gtk.c
Log Message:
-----------
ui/gtk: force realization of drawing area
Fixes the GL context creation from a widget that isn't yet realized (in
a hidden tab for example).
Resolves:
https://gitlab.com/qemu-project/qemu/-/issues/1727
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Antonio Caggiano <quic_acaggian@quicinc.com>
Message-Id: <20231017111642.1155545-1-marcandre.lureau@redhat.com>
Commit: 6f189a08c1b0085808af1bfbf4567f0da193ecc1
https://github.com/qemu/qemu/commit/6f189a08c1b0085808af1bfbf4567f0da193ecc1
Author: Antonio Caggiano <quic_acaggian@quicinc.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M ui/gtk-egl.c
Log Message:
-----------
ui/gtk-egl: Check EGLSurface before doing scanout
The first time gd_egl_scanout_texture() is called, there's a possibility
that the GTK drawing area might not be realized yet, in which case its
associated GdkWindow is NULL. This means gd_egl_init() was also skipped
and the EGLContext and EGLSurface stored in the VirtualGfxConsole are
not valid yet.
Continuing with the scanout in this conditions would result in hitting
an assert in libepoxy: "Couldn't find current GLX or EGL context".
A possible workaround is to just ignore the scanout request, giving the
the GTK drawing area some time to finish its realization. At that point,
the gd_egl_init() will succeed and the EGLContext and EGLSurface stored
in the VirtualGfxConsole will be valid.
Signed-off-by: Antonio Caggiano <quic_acaggian@quicinc.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20231016123215.2699269-1-quic_acaggian@quicinc.com>
Commit: 47fd6ab1e334962890bc3e8d2e32857f6594e1c1
https://github.com/qemu/qemu/commit/47fd6ab1e334962890bc3e8d2e32857f6594e1c1
Author: Dongwon Kim <dongwon.kim@intel.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M ui/gtk-egl.c
Log Message:
-----------
ui/gtk-egl: apply scale factor when calculating window's dimension
Scale factor needs to be applied when calculating width/height of the
GTK windows.
Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20231012222643.13996-1-dongwon.kim@intel.com>
Commit: 5ec0898b057971f0e03d2ecc8b62c58b50f4cb99
https://github.com/qemu/qemu/commit/5ec0898b057971f0e03d2ecc8b62c58b50f4cb99
Author: Carwyn Ellis <carwynellis@gmail.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M qapi/ui.json
M ui/cocoa.m
Log Message:
-----------
ui/cocoa: add zoom-to-fit display option
Provides a display option, zoom-to-fit, that enables scaling of the
display when full-screen mode is enabled.
Also ensures that the corresponding menu item is marked as enabled when
the option is set to on.
Signed-off-by: Carwyn Ellis <carwynellis@gmail.com>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-Id: <20231027154920.80626-2-carwynellis@gmail.com>
Commit: fb93569e422d4f4b5953dd953c92ba7838309972
https://github.com/qemu/qemu/commit/fb93569e422d4f4b5953dd953c92ba7838309972
Author: Sergey Mironov <mironov@fintech.ru>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M ui/gtk.c
Log Message:
-----------
ui: Replacing pointer in function
At the end of the first if we see 'vc->gfx.surface = NULL;',
further checking of it is pointless. In the second if, ectx is taken.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Co-developed-by: Linux Verification Center <sdl.qemu@linuxtesting.org>
Signed-off-by: Sergey Mironov <mironov@fintech.ru>
Message-ID: <20231012104448.1251039-1-mironov@fintech.ru>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Commit: c7f21816612879efdae3d9b67f024a6671494c62
https://github.com/qemu/qemu/commit/c7f21816612879efdae3d9b67f024a6671494c62
Author: Hanna Czenczek <hreitz@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M docs/interop/vhost-user.rst
Log Message:
-----------
vhost-user.rst: Improve [GS]ET_VRING_BASE doc
GET_VRING_BASE does not mention that it stops the respective ring. Fix
that.
Furthermore, it is not fully clear what the "base offset" these
commands' documentation refers to is; an offset could be many things.
Be more precise and verbose about it, especially given that these
commands use different payload structures depending on whether the vring
is split or packed.
Signed-off-by: Hanna Czenczek <hreitz@redhat.com>
Message-Id: <20231016134243.68248-2-hreitz@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: eae69cc36b278a3e84bb013909135e138b37855d
https://github.com/qemu/qemu/commit/eae69cc36b278a3e84bb013909135e138b37855d
Author: Hanna Czenczek <hreitz@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M docs/interop/vhost-user.rst
Log Message:
-----------
vhost-user.rst: Clarify enabling/disabling vrings
Currently, the vhost-user documentation says that rings are to be
initialized in a disabled state when VHOST_USER_F_PROTOCOL_FEATURES is
negotiated. However, by the time of feature negotiation, all rings have
already been initialized, so it is not entirely clear what this means.
At least the vhost-user-backend Rust crate's implementation interpreted
it to mean that whenever this feature is negotiated, all rings are to
put into a disabled state, which means that every SET_FEATURES call
would disable all rings, effectively halting the device. This is
problematic because the VHOST_F_LOG_ALL feature is also set or cleared
this way, which happens during migration. Doing so should not halt the
device.
Other implementations have interpreted this to mean that the device is
to be initialized with all rings disabled, and a subsequent SET_FEATURES
call that does not set VHOST_USER_F_PROTOCOL_FEATURES will enable all of
them. Here, SET_FEATURES will never disable any ring.
This interpretation does not suffer the problem of unintentionally
halting the device whenever features are set or cleared, so it seems
better and more reasonable.
We can clarify this in the documentation by making it explicit that the
enabled/disabled state is tracked even while the vring is stopped.
Every vring is initialized in a disabled state, and SET_FEATURES without
VHOST_USER_F_PROTOCOL_FEATURES simply becomes one way to enable all
vrings.
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Hanna Czenczek <hreitz@redhat.com>
Message-Id: <20231016134243.68248-3-hreitz@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: a6e76dd3c3b98db86802b4b08984f2ac5ec1faea
https://github.com/qemu/qemu/commit/a6e76dd3c3b98db86802b4b08984f2ac5ec1faea
Author: Hanna Czenczek <hreitz@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M docs/interop/vhost-user.rst
Log Message:
-----------
vhost-user.rst: Introduce suspended state
In vDPA, GET_VRING_BASE does not stop the queried vring, which is why
SUSPEND was introduced so that the returned index would be stable. In
vhost-user, it does stop the vring, so under the same reasoning, it can
get away without SUSPEND.
Still, we do want to clarify that if the device is completely stopped,
i.e. all vrings are stopped, the back-end should cease to modify any
state relating to the guest. Do this by calling it "suspended".
Suggested-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Hanna Czenczek <hreitz@redhat.com>
Message-Id: <20231016134243.68248-4-hreitz@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 019233096c03b826e0e677115b6e3c550a54a48d
https://github.com/qemu/qemu/commit/019233096c03b826e0e677115b6e3c550a54a48d
Author: Hanna Czenczek <hreitz@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M docs/interop/vhost-user.rst
Log Message:
-----------
vhost-user.rst: Migrating back-end-internal state
For vhost-user devices, qemu can migrate the virtio state, but not the
back-end's internal state. To do so, we need to be able to transfer
this internal state between front-end (qemu) and back-end.
At this point, this new feature is added for the purpose of virtio-fs
migration. Because virtiofsd's internal state will not be too large, we
believe it is best to transfer it as a single binary blob after the
streaming phase.
These are the additions to the protocol:
- New vhost-user protocol feature VHOST_USER_PROTOCOL_F_DEVICE_STATE
- SET_DEVICE_STATE_FD function: Front-end and back-end negotiate a file
descriptor over which to transfer the state.
- CHECK_DEVICE_STATE: After the state has been transferred through the
file descriptor, the front-end invokes this function to verify
success. There is no in-band way (through the file descriptor) to
indicate failure, so we need to check explicitly.
Once the transfer FD has been established via SET_DEVICE_STATE_FD
(which includes establishing the direction of transfer and migration
phase), the sending side writes its data into it, and the reading side
reads it until it sees an EOF. Then, the front-end will check for
success via CHECK_DEVICE_STATE, which on the destination side includes
checking for integrity (i.e. errors during deserialization).
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Hanna Czenczek <hreitz@redhat.com>
Message-Id: <20231016134243.68248-5-hreitz@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: cda83adc62b6108afc8a82d0f54d9a9a861e7aa8
https://github.com/qemu/qemu/commit/cda83adc62b6108afc8a82d0f54d9a9a861e7aa8
Author: Hanna Czenczek <hreitz@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/virtio/vhost-user.c
M hw/virtio/vhost.c
M include/hw/virtio/vhost-backend.h
M include/hw/virtio/vhost-user.h
M include/hw/virtio/vhost.h
Log Message:
-----------
vhost-user: Interface for migration state transfer
Add the interface for transferring the back-end's state during migration
as defined previously in vhost-user.rst.
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Hanna Czenczek <hreitz@redhat.com>
Message-Id: <20231016134243.68248-6-hreitz@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 4a00d5d7f4b65ba99b33d5a0d6f8c563895839ea
https://github.com/qemu/qemu/commit/4a00d5d7f4b65ba99b33d5a0d6f8c563895839ea
Author: Hanna Czenczek <hreitz@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/virtio/vhost.c
M include/hw/virtio/vhost.h
Log Message:
-----------
vhost: Add high-level state save/load functions
vhost_save_backend_state() and vhost_load_backend_state() can be used by
vhost front-ends to easily save and load the back-end's state to/from
the migration stream.
Because we do not know the full state size ahead of time,
vhost_save_backend_state() simply reads the data in 1 MB chunks, and
writes each chunk consecutively into the migration stream, prefixed by
its length. EOF is indicated by a 0-length chunk.
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Hanna Czenczek <hreitz@redhat.com>
Message-Id: <20231016134243.68248-7-hreitz@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: bca3e2a13814253b4ed878a3313688554edd1b66
https://github.com/qemu/qemu/commit/bca3e2a13814253b4ed878a3313688554edd1b66
Author: Hanna Czenczek <hreitz@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/virtio/vhost-user-fs.c
Log Message:
-----------
vhost-user-fs: Implement internal migration
A virtio-fs device's VM state consists of:
- the virtio device (vring) state (VMSTATE_VIRTIO_DEVICE)
- the back-end's (virtiofsd's) internal state
We get/set the latter via the new vhost operations to transfer migratory
state. It is its own dedicated subsection, so that for external
migration, it can be disabled.
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Hanna Czenczek <hreitz@redhat.com>
Message-Id: <20231016134243.68248-8-hreitz@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 2880e676c000a62828d3d9ece7b2ec7a513560a2
https://github.com/qemu/qemu/commit/2880e676c000a62828d3d9ece7b2ec7a513560a2
Author: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M MAINTAINERS
M hw/audio/Kconfig
M hw/audio/meson.build
M hw/audio/trace-events
A hw/audio/virtio-snd.c
A include/hw/audio/virtio-snd.h
M system/qdev-monitor.c
Log Message:
-----------
Add virtio-sound device stub
Add a new VIRTIO device for the virtio sound device id. Functionality
will be added in the following commits.
Based-on:
https://github.com/OpenSynergy/qemu/commit/5a2f350eec5d157b90d9c7b40a8e603f4da92471
Signed-off-by: Igor Skalkin <Igor.Skalkin@opensynergy.com>
Signed-off-by: Anton Yakovlev <Anton.Yakovlev@opensynergy.com>
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id:
<f9678a41fe97b5886c1b04795f1be046509de866.1698062525.git.manos.pitsidianakis@linaro.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 2426908590c1d8d9ffb741c5552ad45d9d3ba9f8
https://github.com/qemu/qemu/commit/2426908590c1d8d9ffb741c5552ad45d9d3ba9f8
Author: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M MAINTAINERS
M hw/audio/meson.build
A hw/audio/virtio-snd-pci.c
M system/qdev-monitor.c
Log Message:
-----------
Add virtio-sound-pci device
This patch adds a PCI wrapper device for the virtio-sound device.
It is necessary to instantiate a virtio-snd device in a guest.
All sound logic will be added to the virtio-snd device in the following
commits.
To add this device with a guest, you'll need a >=5.13 kernel compiled
with CONFIG_SND_VIRTIO=y, which at the time of writing most distros have
off by default.
Use with following flags in the invocation:
Pulseaudio:
-audio driver=pa,model=virtio
or
-audio driver=pa,model=virtio,server=/run/user/1000/pulse/native
sdl:
-audio driver=sdl,model=virtio
coreaudio (macos/darwin):
-audio driver=coreaudio,model=virtio
etc.
Based-on:
https://github.com/OpenSynergy/qemu/commit/5a2f350eec5d157b90d9c7b40a8e603f4da92471
Signed-off-by: Igor Skalkin <Igor.Skalkin@opensynergy.com>
Signed-off-by: Anton Yakovlev <Anton.Yakovlev@opensynergy.com>
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id:
<b223598d59f56ead6a6d8d9bb6801e17489ddaa4.1698062525.git.manos.pitsidianakis@linaro.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: eb9ad377bb94d2d98d18cfccc431a028361385c6
https://github.com/qemu/qemu/commit/eb9ad377bb94d2d98d18cfccc431a028361385c6
Author: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/audio/trace-events
M hw/audio/virtio-snd.c
M include/hw/audio/virtio-snd.h
Log Message:
-----------
virtio-sound: handle control messages and streams
Receive guest requests in the control (CTRL) queue of the virtio sound
device and reply with a NOT SUPPORTED error to all control commands.
The receiving handler is virtio_snd_handle_ctrl(). It stores all control
messages in the queue in the device's command queue. Then it calls
virtio_snd_process_cmdq() to handle each message.
The handler is process_cmd() which replies with VIRTIO_SND_S_NOT_SUPP.
Based-on:
https://github.com/OpenSynergy/qemu/commit/5a2f350eec5d157b90d9c7b40a8e603f4da92471
Signed-off-by: Igor Skalkin <Igor.Skalkin@opensynergy.com>
Signed-off-by: Anton Yakovlev <Anton.Yakovlev@opensynergy.com>
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id:
<3224aff87e7c4f2777bfe1bbbbca93b72525992c.1698062525.git.manos.pitsidianakis@linaro.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 0ff05dd209f153f037a48e4039a033885b9ab5e3
https://github.com/qemu/qemu/commit/0ff05dd209f153f037a48e4039a033885b9ab5e3
Author: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/audio/trace-events
M hw/audio/virtio-snd.c
Log Message:
-----------
virtio-sound: handle VIRTIO_SND_R_PCM_INFO request
Respond to the VIRTIO_SND_R_PCM_INFO control request with the parameters
of each requested PCM stream.
Based-on:
https://github.com/OpenSynergy/qemu/commit/5a2f350eec5d157b90d9c7b40a8e603f4da92471
Signed-off-by: Igor Skalkin <Igor.Skalkin@opensynergy.com>
Signed-off-by: Anton Yakovlev <Anton.Yakovlev@opensynergy.com>
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id:
<5ecea6ba2fb0e3957d7d90bc4dbac521a3d1f678.1698062525.git.manos.pitsidianakis@linaro.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: fa131d4a8277ef3522384d33d3b6b7963b5e7de9
https://github.com/qemu/qemu/commit/fa131d4a8277ef3522384d33d3b6b7963b5e7de9
Author: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/audio/trace-events
M hw/audio/virtio-snd.c
Log Message:
-----------
virtio-sound: handle VIRTIO_SND_R_PCM_{START,STOP}
Handle the start and stop control messages for a stream_id. This request
does nothing at the moment except for replying to it. Audio playback
or capture will be started/stopped here in follow-up commits.
Based-on:
https://github.com/OpenSynergy/qemu/commit/5a2f350eec5d157b90d9c7b40a8e603f4da92471
Signed-off-by: Igor Skalkin <Igor.Skalkin@opensynergy.com>
Signed-off-by: Anton Yakovlev <Anton.Yakovlev@opensynergy.com>
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id:
<9657dbfe3cb4a48ceb033ceb5977dc08669dfefd.1698062525.git.manos.pitsidianakis@linaro.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 64704ce04b0a62184d49f899e7f300f67480a2a6
https://github.com/qemu/qemu/commit/64704ce04b0a62184d49f899e7f300f67480a2a6
Author: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/audio/trace-events
M hw/audio/virtio-snd.c
Log Message:
-----------
virtio-sound: handle VIRTIO_SND_R_PCM_SET_PARAMS
Handle the set parameters control request. It reconfigures a stream
based on a guest's preference if the values are valid and supported.
Based-on:
https://github.com/OpenSynergy/qemu/commit/5a2f350eec5d157b90d9c7b40a8e603f4da92471
Signed-off-by: Igor Skalkin <Igor.Skalkin@opensynergy.com>
Signed-off-by: Anton Yakovlev <Anton.Yakovlev@opensynergy.com>
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id:
<d0d19928691f9375bfd83388806786cb7b161301.1698062525.git.manos.pitsidianakis@linaro.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: e5788b8fbf9361c978eb8347471d8f855580777f
https://github.com/qemu/qemu/commit/e5788b8fbf9361c978eb8347471d8f855580777f
Author: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/audio/virtio-snd.c
Log Message:
-----------
virtio-sound: handle VIRTIO_SND_R_PCM_PREPARE
Handles the PCM prepare control request. It initializes a PCM stream
when the guests asks for it.
Based-on:
https://github.com/OpenSynergy/qemu/commit/5a2f350eec5d157b90d9c7b40a8e603f4da92471
Signed-off-by: Igor Skalkin <Igor.Skalkin@opensynergy.com>
Signed-off-by: Anton Yakovlev <Anton.Yakovlev@opensynergy.com>
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id:
<c6a9c437ef48e45f083fc957dcf7fe18a028e657.1698062525.git.manos.pitsidianakis@linaro.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: d48800d740d1eaea5be65accbf37d82f0effcfb5
https://github.com/qemu/qemu/commit/d48800d740d1eaea5be65accbf37d82f0effcfb5
Author: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/audio/trace-events
M hw/audio/virtio-snd.c
Log Message:
-----------
virtio-sound: handle VIRTIO_SND_R_PCM_RELEASE
Handle the PCM release control request, which is necessary for flushing
pending sound IO. No IO is handled yet so currently it only replies to
the request.
Based-on:
https://github.com/OpenSynergy/qemu/commit/5a2f350eec5d157b90d9c7b40a8e603f4da92471
Signed-off-by: Igor Skalkin <Igor.Skalkin@opensynergy.com>
Signed-off-by: Anton Yakovlev <Anton.Yakovlev@opensynergy.com>
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id:
<ae0afa16461429df1a2f268313d5bfcca27479ec.1698062525.git.manos.pitsidianakis@linaro.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 18a752810f04e3f1933682addd0a6c978efc5cdf
https://github.com/qemu/qemu/commit/18a752810f04e3f1933682addd0a6c978efc5cdf
Author: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/audio/trace-events
M hw/audio/virtio-snd.c
M include/hw/audio/virtio-snd.h
Log Message:
-----------
virtio-sound: implement audio output (TX)
Handle output IO messages in the transmit (TX) virtqueue.
It allocates a VirtIOSoundPCMBuffer for each IO message and copies the
data buffer to it. When the IO buffer is written to the host's sound
card, the guest will be notified that it has been consumed.
The lifetime of an IO message is:
1. Guest sends IO message to TX virtqueue.
2. QEMU adds it to the appropriate stream's IO buffer queue.
3. Sometime later, the host audio backend calls the output callback,
virtio_snd_pcm_out_cb(), which is defined with an AUD_open_out()
call. The callback gets an available number of bytes the backend can
receive. Then it writes data from the IO buffer queue to the backend.
If at any time a buffer is exhausted, it is returned to the guest as
completed.
4. If the guest releases the stream, its buffer queue is flushed by
attempting to write any leftover data to the audio backend and
releasing all IO messages back to the guest. This is how according to
the spec the guest knows the release was successful.
Based-on:
https://github.com/OpenSynergy/qemu/commit/5a2f350eec5d157b90d9c7b40a8e603f4da92471
Signed-off-by: Igor Skalkin <Igor.Skalkin@opensynergy.com>
Signed-off-by: Anton Yakovlev <Anton.Yakovlev@opensynergy.com>
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id:
<b7c6fc458c763d09a4abbcb620ae9b220afa5b8f.1698062525.git.manos.pitsidianakis@linaro.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: d8d64acbecfa131153e5b96fb24b4f95f55be881
https://github.com/qemu/qemu/commit/d8d64acbecfa131153e5b96fb24b4f95f55be881
Author: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/audio/trace-events
M hw/audio/virtio-snd.c
Log Message:
-----------
virtio-sound: implement audio capture (RX)
To perform audio capture we duplicate the TX logic of the previous
commit with the following difference: we receive data from the QEMU
audio backend and write it in the virt queue IO buffers the guest sends
to QEMU. When they are full (i.e. they have `period_bytes` amount of
data) or when recording stops in QEMU's audio backend, the buffer is
returned to the guest by notifying it.
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id:
<e56a17741a24ccadfbbea19d3c60c9406b795b23.1698062525.git.manos.pitsidianakis@linaro.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: f54fea113cc48000836b95681f3b9fdbe43c7d96
https://github.com/qemu/qemu/commit/f54fea113cc48000836b95681f3b9fdbe43c7d96
Author: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M MAINTAINERS
M docs/system/device-emulation.rst
A docs/system/devices/virtio-snd.rst
Log Message:
-----------
docs/system: add basic virtio-snd documentation
This commit adds basic documentation for using virtio-snd.
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id:
<e7fb941cf7636fdff40cbdcdcd660dec5f15ca3c.1698062525.git.manos.pitsidianakis@linaro.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 8b98c15f22fca34f23846e70752a70e4a2469317
https://github.com/qemu/qemu/commit/8b98c15f22fca34f23846e70752a70e4a2469317
Author: Hawkins Jiawei <yin31149@gmail.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M net/vhost-vdpa.c
Log Message:
-----------
vdpa: Restore hash calculation state
This patch introduces vhost_vdpa_net_load_rss() to restore
the hash calculation state at device's startup.
Signed-off-by: Hawkins Jiawei <yin31149@gmail.com>
Message-Id:
<dbf699acff8c226596136a55a6abe35ebfeac8b0.1698194366.git.yin31149@gmail.com>
Acked-by: Eugenio Pérez <eperezma@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 556b67d413a699431eadb71642033864649ea934
https://github.com/qemu/qemu/commit/556b67d413a699431eadb71642033864649ea934
Author: Hawkins Jiawei <yin31149@gmail.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M net/vhost-vdpa.c
Log Message:
-----------
vdpa: Allow VIRTIO_NET_F_HASH_REPORT in SVQ
Enable SVQ with VIRTIO_NET_F_HASH_REPORT feature.
Signed-off-by: Hawkins Jiawei <yin31149@gmail.com>
Message-Id:
<d66b0aee501cdad7954231900c35a11cad1e13db.1698194366.git.yin31149@gmail.com>
Acked-by: Eugenio Pérez <eperezma@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: d1fd2d3118a42f36d86efae7ffbdce79f7024584
https://github.com/qemu/qemu/commit/d1fd2d3118a42f36d86efae7ffbdce79f7024584
Author: Hawkins Jiawei <yin31149@gmail.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M net/vhost-vdpa.c
Log Message:
-----------
vdpa: Add SetSteeringEBPF method for NetClientState
At present, to enable the VIRTIO_NET_F_RSS feature, eBPF must
be loaded for the vhost backend.
Given that vhost-vdpa is one of the vhost backend, we need to
implement the SetSteeringEBPF method to support RSS for vhost-vdpa,
even if vhost-vdpa calculates the rss hash in the hardware device
instead of in the kernel by eBPF.
Although this requires QEMU to be compiled with `--enable-bpf`
configuration even if the vdpa device does not use eBPF to
calculate the rss hash, this can avoid adding the specific
conditional statements for vDPA case to enable the VIRTIO_NET_F_RSS
feature, which reduces code maintainbility.
Suggested-by: Eugenio Pérez <eperezma@redhat.com>
Signed-off-by: Hawkins Jiawei <yin31149@gmail.com>
Message-Id:
<280e20ddce55b6de60f1552ba0865bffffe909b2.1698195059.git.yin31149@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: b3c09106559f9d84a940d2a27c4cfc81c9e15347
https://github.com/qemu/qemu/commit/b3c09106559f9d84a940d2a27c4cfc81c9e15347
Author: Hawkins Jiawei <yin31149@gmail.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M net/vhost-vdpa.c
Log Message:
-----------
vdpa: Restore receive-side scaling state
This patch reuses vhost_vdpa_net_load_rss() with some
refactorings to restore the receive-side scaling state
at device's startup.
Signed-off-by: Hawkins Jiawei <yin31149@gmail.com>
Message-Id:
<cf5b78a16ed0318982ceffb195f2227f6aad4ac1.1698195059.git.yin31149@gmail.com>
Acked-by: Eugenio Pérez <eperezma@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 07eba9493d14b3ba371e64392effc384246892ea
https://github.com/qemu/qemu/commit/07eba9493d14b3ba371e64392effc384246892ea
Author: Hawkins Jiawei <yin31149@gmail.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M net/vhost-vdpa.c
Log Message:
-----------
vdpa: Allow VIRTIO_NET_F_RSS in SVQ
Enable SVQ with VIRTIO_NET_F_RSS feature.
Signed-off-by: Hawkins Jiawei <yin31149@gmail.com>
Message-Id:
<626449eb303207de408126b3dc7c155cd72b028b.1698195059.git.yin31149@gmail.com>
Acked-by: Eugenio Pérez <eperezma@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 7d5936791ea349d9cef856babcce28470966bfa4
https://github.com/qemu/qemu/commit/7d5936791ea349d9cef856babcce28470966bfa4
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M tests/unit/test-smp-parse.c
Log Message:
-----------
tests: test-smp-parse: Add the test for cores/threads per socket helpers
Use the different ways to calculate cores/threads per socket, so that
the new CPU topology levels won't be missed in these 2 helpes:
* machine_topo_get_cores_per_socket()
* machine_topo_get_threads_per_socket()
Test the commit a1d027be95bc3 ("machine: Add helpers to get cores/
threads per socket").
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231023094635.1588282-2-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 6c7937ece909d3df0d2b4e94909f57388f5ed666
https://github.com/qemu/qemu/commit/6c7937ece909d3df0d2b4e94909f57388f5ed666
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
A tests/data/acpi/q35/APIC.type4-count
A tests/data/acpi/q35/DSDT.type4-count
A tests/data/acpi/q35/FACP.type4-count
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: bios-tables-test: Prepare the ACPI table change for smbios type4 count
test
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 1 - 3.
List the ACPI tables that will be added to test the type 4 count.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231023094635.1588282-3-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: df210963a10e5ca884908addeb07aa081c5b7ad2
https://github.com/qemu/qemu/commit/df210963a10e5ca884908addeb07aa081c5b7ad2
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M tests/qtest/bios-tables-test.c
Log Message:
-----------
tests: bios-tables-test: Add test for smbios type4 count
This tests the commit d79a284a44bb7 ("hw/smbios: Fix smbios_smp_sockets
calculation").
In smbios_get_tables() (hw/smbios/smbios.c), smbios type4 table is built
for each socket, so the count of type4 tables should be equal to the
number of sockets.
Thus for the topology in this case, there're the following considerations:
1. The topology should include multiple sockets to ensure smbios could
create type4 tables for each socket.
2. In addition to sockets, for the more general topology, we should also
configure as many topology levels as possible (multiple dies, no
module since x86 hasn't supported it), to ensure that smbios is able
to exclude the effect of other topology levels to create the type4
tables only for sockets.
3. The original miscalculation bug also misused "smp.cpus", so it's
necessary to configure "cpus" (presented threads for machine) and
"maxcpus" (total threads for machine) as well to make sure that
configuring unpluged CPUs in smp (cpus < maxcpus) does not affect
the correctness of the count of type4 tables.
Based on these considerations, select the topology as the follow:
-smp cpus=100,maxcpus=120,sockets=5,dies=2,cores=4,threads=3
The expected count of type4 tables = sockets (5).
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231023094635.1588282-4-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: c1cd1d360db857d6f76071e8de6af97cdab2bdfe
https://github.com/qemu/qemu/commit/c1cd1d360db857d6f76071e8de6af97cdab2bdfe
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M tests/data/acpi/q35/APIC.type4-count
M tests/data/acpi/q35/DSDT.type4-count
M tests/data/acpi/q35/FACP.type4-count
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: bios-tables-test: Add ACPI table binaries for smbios type4 count test
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
FACP:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-W37791, Wed Aug 23 10:36:32 2023
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI
Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : B3
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0002
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 1
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000484A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 1
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
+
...
APIC:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-687791, Wed Aug 23 10:36:32 2023
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC
Description Table (MADT)]
+[004h 0004 4] Table Length : 00000430
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : C5
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 00 [Processor Local APIC]
+[035h 0053 1] Length : 08
+[036h 0054 1] Processor ID : 01
+[037h 0055 1] Local Apic ID : 01
+[038h 0056 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
[snip]
+[3E4h 0996 1] Subtable Type : 00 [Processor Local APIC]
+[3E5h 0997 1] Length : 08
+[3E6h 0998 1] Processor ID : 77
+[3E7h 0999 1] Local Apic ID : 9E
+[3E8h 1000 4] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+ Runtime Online Capable : 0
+
+[3ECh 1004 1] Subtable Type : 01 [I/O APIC]
+[3EDh 1005 1] Length : 0C
+[3EEh 1006 1] I/O Apic ID : 00
+[3EFh 1007 1] Reserved : 00
+[3F0h 1008 4] Address : FEC00000
+[3F4h 1012 4] Interrupt : 00000000
+
+[3F8h 1016 1] Subtable Type : 02 [Interrupt Source Override]
+[3F9h 1017 1] Length : 0A
+[3FAh 1018 1] Bus : 00
+[3FBh 1019 1] Source : 00
+[3FCh 1020 4] Interrupt : 00000002
+[400h 1024 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[402h 1026 1] Subtable Type : 02 [Interrupt Source Override]
+[403h 1027 1] Length : 0A
+[404h 1028 1] Bus : 00
+[405h 1029 1] Source : 05
+[406h 1030 4] Interrupt : 00000005
+[40Ah 1034 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[40Ch 1036 1] Subtable Type : 02 [Interrupt Source Override]
+[40Dh 1037 1] Length : 0A
+[40Eh 1038 1] Bus : 00
+[40Fh 1039 1] Source : 09
+[410h 1040 4] Interrupt : 00000009
+[414h 1044 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[416h 1046 1] Subtable Type : 02 [Interrupt Source Override]
+[417h 1047 1] Length : 0A
+[418h 1048 1] Bus : 00
+[419h 1049 1] Source : 0A
+[41Ah 1050 4] Interrupt : 0000000A
+[41Eh 1054 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[420h 1056 1] Subtable Type : 02 [Interrupt Source Override]
+[421h 1057 1] Length : 0A
+[422h 1058 1] Bus : 00
+[423h 1059 1] Source : 0B
+[424h 1060 4] Interrupt : 0000000B
+[428h 1064 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[42Ah 1066 1] Subtable Type : 04 [Local APIC NMI]
+[42Bh 1067 1] Length : 06
+[42Ch 1068 1] Processor ID : FF
+[42Dh 1069 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[42Fh 1071 1] Interrupt Input LINT : 01
+
...
DSDT:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of /tmp/aml-8G8791, Wed Aug 23 10:36:32 2023
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x0000489D (18589)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0xDB
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPC "
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
+
[snip]
+
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 //
........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+ }
+
+ Processor (C001, 0x01, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (One))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 //
........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (One)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (One, Arg0, Arg1, Arg2)
+ }
+ }
[snip]
+ Processor (C077, 0x77, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x77))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x77, 0x9E, 0x01, 0x00, 0x00, 0x00 //
..w.....
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x77)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x77, Arg0, Arg1, Arg2)
+ }
+ }
+ }
+ }
+
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231023094635.1588282-5-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 623d26ad9affaeca03633880623961434e60e77b
https://github.com/qemu/qemu/commit/623d26ad9affaeca03633880623961434e60e77b
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
A tests/data/acpi/q35/APIC.core-count
A tests/data/acpi/q35/DSDT.core-count
A tests/data/acpi/q35/FACP.core-count
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: bios-tables-test: Prepare the ACPI table change for smbios type4 core
count test
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 1 - 3.
List the ACPI tables that will be added to test the type 4 core count
field.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231023094635.1588282-6-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 148a8a1d5fdbdb0ba2a9883c6182e3135cb417b2
https://github.com/qemu/qemu/commit/148a8a1d5fdbdb0ba2a9883c6182e3135cb417b2
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M tests/qtest/bios-tables-test.c
Log Message:
-----------
tests: bios-tables-test: Add test for smbios type4 core count
This tests the commit 196ea60a734c3 ("hw/smbios: Fix core count in
type4").
In smbios_build_type_4_table() (hw/smbios/smbios.c), if the number of
cores in the socket is not more than 255, then smbios type4 table
encodes cores per socket into the core count field.
So for the topology in this case, there're the following considerations:
1. cores per socket should be not more than 255 to ensure we could cover
the core count field.
2. The original bug was that cores per socket was miscalculated, so now
we should include as many topology levels as possible (mutiple
sockets & dies, no module since x86 hasn't supported it) to cover
more general topology scenarios, to ensure that the cores per socket
encoded in the core count field is correct.
Based on these considerations, select the topology with multiple sockets
and dies:
-smp 54,sockets=2,dies=3,cores=3,threads=3
The expected core count = cores per socket = cores (3) * dies (3) = 9.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231023094635.1588282-7-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 61ace1d77280b26f0d6ed32b27a1f532f85af9f5
https://github.com/qemu/qemu/commit/61ace1d77280b26f0d6ed32b27a1f532f85af9f5
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M tests/data/acpi/q35/APIC.core-count
M tests/data/acpi/q35/DSDT.core-count
M tests/data/acpi/q35/FACP.core-count
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: bios-tables-test: Add ACPI table binaries for smbios type4 core count
test
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
FACP:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-Y6WW91, Wed Aug 23 15:43:43 2023
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI
Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : B3
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0002
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 1
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000484A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 1
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
...
APIC:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-FFXW91, Wed Aug 23 15:43:43 2023
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC
Description Table (MADT)]
+[004h 0004 4] Table Length : 00000220
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : 3C
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
[snip]
+[1D4h 0468 1] Subtable Type : 00 [Processor Local APIC]
+[1D5h 0469 1] Length : 08
+[1D6h 0470 1] Processor ID : 35
+[1D7h 0471 1] Local Apic ID : 6A
+[1D8h 0472 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[1DCh 0476 1] Subtable Type : 01 [I/O APIC]
+[1DDh 0477 1] Length : 0C
+[1DEh 0478 1] I/O Apic ID : 00
+[1DFh 0479 1] Reserved : 00
+[1E0h 0480 4] Address : FEC00000
+[1E4h 0484 4] Interrupt : 00000000
+
+[1E8h 0488 1] Subtable Type : 02 [Interrupt Source Override]
+[1E9h 0489 1] Length : 0A
+[1EAh 0490 1] Bus : 00
+[1EBh 0491 1] Source : 00
+[1ECh 0492 4] Interrupt : 00000002
+[1F0h 0496 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[1F2h 0498 1] Subtable Type : 02 [Interrupt Source Override]
+[1F3h 0499 1] Length : 0A
+[1F4h 0500 1] Bus : 00
+[1F5h 0501 1] Source : 05
+[1F6h 0502 4] Interrupt : 00000005
+[1FAh 0506 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[1FCh 0508 1] Subtable Type : 02 [Interrupt Source Override]
+[1FDh 0509 1] Length : 0A
+[1FEh 0510 1] Bus : 00
+[1FFh 0511 1] Source : 09
+[200h 0512 4] Interrupt : 00000009
+[204h 0516 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[206h 0518 1] Subtable Type : 02 [Interrupt Source Override]
+[207h 0519 1] Length : 0A
+[208h 0520 1] Bus : 00
+[209h 0521 1] Source : 0A
+[20Ah 0522 4] Interrupt : 0000000A
+[20Eh 0526 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[210h 0528 1] Subtable Type : 02 [Interrupt Source Override]
+[211h 0529 1] Length : 0A
+[212h 0530 1] Bus : 00
+[213h 0531 1] Source : 0B
+[214h 0532 4] Interrupt : 0000000B
+[218h 0536 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[21Ah 0538 1] Subtable Type : 04 [Local APIC NMI]
+[21Bh 0539 1] Length : 06
+[21Ch 0540 1] Processor ID : FF
+[21Dh 0541 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[21Fh 0543 1] Interrupt Input LINT : 01
...
DSDT:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of /tmp/aml-9ZXW91, Wed Aug 23 15:43:43 2023
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x00003271 (12913)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0xAF
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPC "
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
[snip]
+ Device (\_SB.CPUS)
+ {
+ Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID:
Hardware ID
+ Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) //
_CID: Compatible ID
+ Method (CTFY, 2, NotSerialized)
+ {
+ If ((Arg0 == Zero))
+ {
+ Notify (C000, Arg1)
+ }
+
+ If ((Arg0 == One))
+ {
+ Notify (C001, Arg1)
+ }
[snip]
+ If ((Arg0 == 0x35))
+ {
+ Notify (C035, Arg1)
+ }
+ }
[snip]
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 //
........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+ }
+
+ Processor (C001, 0x01, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (One))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 //
........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (One)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (One, Arg0, Arg1, Arg2)
+ }
+ }
[snip]
+ Processor (C035, 0x35, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x35))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x35, 0x6A, 0x01, 0x00, 0x00, 0x00 //
..5j....
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x35)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x35, Arg0, Arg1, Arg2)
+ }
+ }
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231023094635.1588282-8-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: c63fcb2c10810e8294712f6e09657ef5bdd78833
https://github.com/qemu/qemu/commit/c63fcb2c10810e8294712f6e09657ef5bdd78833
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: bios-tables-test: Prepare the ACPI table change for smbios type4 core
count2 test
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 1 - 3.
List the ACPI tables that will be changed about the type 4 core count2
test case.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231023094635.1588282-9-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 6dc82e32226dd3455a1b82bb2ef37d938570084f
https://github.com/qemu/qemu/commit/6dc82e32226dd3455a1b82bb2ef37d938570084f
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M tests/qtest/bios-tables-test.c
Log Message:
-----------
tests: bios-tables-test: Extend smbios core count2 test to cover general
topology
The commit 196ea60a734c3 ("hw/smbios: Fix core count in type4") fixed
the miscalculation of cores per socket.
The original core count2 test (with the topology configured by
"-smp 275") didn't recognize that topology-related but because it just
created a special topology with only one socket and one die by default,
ignoring the effect of more topology levels (between socket and core) on
the cores per socket calculation.
So for the topology in this case, there're the following considerations:
1. cores per socket should be more than 255 to ensure we could cover
the core count2 field.
2. The original bug was that cores per socket was miscalculated, so now
we should include as many topology levels as possible (multiple
sockets or dies, no module since x86 hasn't supported it) to cover
more general topology scenarios, to ensure that the cores per socket
encoded in the core count2 field is correct.
Based on these considerations, select the topology with multiple dies:
-smp 260,dies=2,cores=130,threads=1
Note, here we doesn't configure multiple sockets to avoid the error
("kvm_init_vcpu: kvm_get_vcpu failed (*): Too many open files") if user
uses the default ulimit seeting on his machine.
And the cores per socket calculation for multiple sockets has already
been covered by the core count test case, so that only multiple dies
configuration is enough.
The expected core count2 = cores per socket = cores (130) * dies (2) =
260.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231023094635.1588282-10-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: f03359a85b4c29858c95d043961288c5e6dc662b
https://github.com/qemu/qemu/commit/f03359a85b4c29858c95d043961288c5e6dc662b
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M tests/data/acpi/q35/APIC.core-count2
M tests/data/acpi/q35/DSDT.core-count2
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: bios-tables-test: Update ACPI table binaries for smbios core count2
test
Change the core count2 from 275 to 260.
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
APIC:
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64-bit version)
* Copyright (c) 2000 - 2020 Intel Corporation
*
- * Disassembly of tests/data/acpi/q35/APIC.core-count2, Wed Aug 23 16:29:51
2023
+ * Disassembly of /tmp/aml-KQDX91, Wed Aug 23 16:29:51 2023
*
* ACPI Data Table [APIC]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
[000h 0000 4] Signature : "APIC" [Multiple APIC
Description Table (MADT)]
-[004h 0004 4] Table Length : 000009AE
+[004h 0004 4] Table Length : 00000CA6
[008h 0008 1] Revision : 03
-[009h 0009 1] Checksum : CE
+[009h 0009 1] Checksum : FA
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 4] Local Apic Address : FEE00000
[028h 0040 4] Flags (decoded below) : 00000001
PC-AT Compatibility : 1
[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
[02Dh 0045 1] Length : 08
[02Eh 0046 1] Processor ID : 00
[02Fh 0047 1] Local Apic ID : 00
[030h 0048 4] Flags (decoded below) : 00000001
Processor Enabled : 1
@@ -1051,1256 +1051,1136 @@
[42Ch 1068 1] Subtable Type : 00 [Processor Local APIC]
[42Dh 1069 1] Length : 08
[42Eh 1070 1] Processor ID : 80
[42Fh 1071 1] Local Apic ID : 80
[430h 1072 4] Flags (decoded below) : 00000001
Processor Enabled : 1
Runtime Online Capable : 0
[434h 1076 1] Subtable Type : 00 [Processor Local APIC]
[435h 1077 1] Length : 08
[436h 1078 1] Processor ID : 81
[437h 1079 1] Local Apic ID : 81
[438h 1080 4] Flags (decoded below) : 00000001
Processor Enabled : 1
Runtime Online Capable : 0
-[43Ch 1084 1] Subtable Type : 00 [Processor Local APIC]
-[43Dh 1085 1] Length : 08
-[43Eh 1086 1] Processor ID : 82
-[43Fh 1087 1] Local Apic ID : 82
-[440h 1088 4] Flags (decoded below) : 00000001
- Processor Enabled : 1
- Runtime Online Capable : 0
-
-[444h 1092 1] Subtable Type : 00 [Processor Local APIC]
-[445h 1093 1] Length : 08
-[446h 1094 1] Processor ID : 83
-[447h 1095 1] Local Apic ID : 83
-[448h 1096 4] Flags (decoded below) : 00000001
- Processor Enabled : 1
- Runtime Online Capable : 0
[snip]
-
-[964h 2404 1] Subtable Type : 01 [I/O APIC]
-[965h 2405 1] Length : 0C
-[966h 2406 1] I/O Apic ID : 00
-[967h 2407 1] Reserved : 00
-[968h 2408 4] Address : FEC00000
-[96Ch 2412 4] Interrupt : 00000000
-
-[970h 2416 1] Subtable Type : 02 [Interrupt Source Override]
-[971h 2417 1] Length : 0A
-[972h 2418 1] Bus : 00
-[973h 2419 1] Source : 00
-[974h 2420 4] Interrupt : 00000002
-[978h 2424 2] Flags (decoded below) : 0000
+[43Ch 1084 1] Subtable Type : 09 [Processor Local x2APIC]
+[43Dh 1085 1] Length : 10
+[43Eh 1086 2] Reserved : 0000
+[440h 1088 4] Processor x2Apic ID : 00000100
+[444h 1092 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+[448h 1096 4] Processor UID : 00000082
+
+[44Ch 1100 1] Subtable Type : 09 [Processor Local x2APIC]
+[44Dh 1101 1] Length : 10
+[44Eh 1102 2] Reserved : 0000
+[450h 1104 4] Processor x2Apic ID : 00000101
+[454h 1108 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+[458h 1112 4] Processor UID : 00000083
+
[snip]
+
+[C68h 3176 1] Subtable Type : 02 [Interrupt Source Override]
+[C69h 3177 1] Length : 0A
+[C6Ah 3178 1] Bus : 00
+[C6Bh 3179 1] Source : 00
+[C6Ch 3180 4] Interrupt : 00000002
+[C70h 3184 2] Flags (decoded below) : 0000
Polarity : 0
Trigger Mode : 0
-[97Ah 2426 1] Subtable Type : 02 [Interrupt Source Override]
-[97Bh 2427 1] Length : 0A
-[97Ch 2428 1] Bus : 00
-[97Dh 2429 1] Source : 05
-[97Eh 2430 4] Interrupt : 00000005
-[982h 2434 2] Flags (decoded below) : 000D
+[C72h 3186 1] Subtable Type : 02 [Interrupt Source Override]
+[C73h 3187 1] Length : 0A
+[C74h 3188 1] Bus : 00
+[C75h 3189 1] Source : 05
+[C76h 3190 4] Interrupt : 00000005
+[C7Ah 3194 2] Flags (decoded below) : 000D
Polarity : 1
Trigger Mode : 3
-[984h 2436 1] Subtable Type : 02 [Interrupt Source Override]
-[985h 2437 1] Length : 0A
-[986h 2438 1] Bus : 00
-[987h 2439 1] Source : 09
-[988h 2440 4] Interrupt : 00000009
-[98Ch 2444 2] Flags (decoded below) : 000D
+[C7Ch 3196 1] Subtable Type : 02 [Interrupt Source Override]
+[C7Dh 3197 1] Length : 0A
+[C7Eh 3198 1] Bus : 00
+[C7Fh 3199 1] Source : 09
+[C80h 3200 4] Interrupt : 00000009
+[C84h 3204 2] Flags (decoded below) : 000D
Polarity : 1
Trigger Mode : 3
-[98Eh 2446 1] Subtable Type : 02 [Interrupt Source Override]
-[98Fh 2447 1] Length : 0A
-[990h 2448 1] Bus : 00
-[991h 2449 1] Source : 0A
-[992h 2450 4] Interrupt : 0000000A
-[996h 2454 2] Flags (decoded below) : 000D
+[C86h 3206 1] Subtable Type : 02 [Interrupt Source Override]
+[C87h 3207 1] Length : 0A
+[C88h 3208 1] Bus : 00
+[C89h 3209 1] Source : 0A
+[C8Ah 3210 4] Interrupt : 0000000A
+[C8Eh 3214 2] Flags (decoded below) : 000D
Polarity : 1
Trigger Mode : 3
-[998h 2456 1] Subtable Type : 02 [Interrupt Source Override]
-[999h 2457 1] Length : 0A
-[99Ah 2458 1] Bus : 00
-[99Bh 2459 1] Source : 0B
-[99Ch 2460 4] Interrupt : 0000000B
-[9A0h 2464 2] Flags (decoded below) : 000D
+[C90h 3216 1] Subtable Type : 02 [Interrupt Source Override]
+[C91h 3217 1] Length : 0A
+[C92h 3218 1] Bus : 00
+[C93h 3219 1] Source : 0B
+[C94h 3220 4] Interrupt : 0000000B
+[C98h 3224 2] Flags (decoded below) : 000D
Polarity : 1
Trigger Mode : 3
-[9A2h 2466 1] Subtable Type : 0A [Local x2APIC NMI]
-[9A3h 2467 1] Length : 0C
-[9A4h 2468 2] Flags (decoded below) : 0000
+[C9Ah 3226 1] Subtable Type : 0A [Local x2APIC NMI]
+[C9Bh 3227 1] Length : 0C
+[C9Ch 3228 2] Flags (decoded below) : 0000
Polarity : 0
Trigger Mode : 0
-[9A6h 2470 4] Processor UID : FFFFFFFF
-[9AAh 2474 1] Interrupt Input LINT : 01
-[9ABh 2475 3] Reserved : 000000
+[C9Eh 3230 4] Processor UID : FFFFFFFF
+[CA2h 3234 1] Interrupt Input LINT : 01
+[CA3h 3235 3] Reserved : 000000
...
DSDT:
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64-bit version)
* Copyright (c) 2000 - 2020 Intel Corporation
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/q35/DSDT.core-count2, Wed Aug 23 16:29:51
2023
+ * Disassembly of /tmp/aml-6DDX91, Wed Aug 23 16:29:51 2023
*
* Original Table Header:
* Signature "DSDT"
- * Length 0x00007EEF (32495)
+ * Length 0x000083EA (33770)
* Revision 0x01 **** 32-bit table (V1), no 64-bit math support
- * Checksum 0x52
+ * Checksum 0x01
* OEM ID "BOCHS "
* OEM Table ID "BXPC "
* OEM Revision 0x00000001 (1)
* Compiler ID "BXPC"
* Compiler Version 0x00000001 (1)
*/
DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
{
Scope (\)
{
OperationRegion (DBG, SystemIO, 0x0402, One)
Field (DBG, ByteAcc, NoLock, Preserve)
{
DBGB, 8
}
@@ -4196,107 +4196,32 @@
}
If ((Arg0 == 0x0101))
{
Notify (C101, Arg1)
}
If ((Arg0 == 0x0102))
{
Notify (C102, Arg1)
}
If ((Arg0 == 0x0103))
{
Notify (C103, Arg1)
}
-
- If ((Arg0 == 0x0104))
- {
- Notify (C104, Arg1)
- }
-
- If ((Arg0 == 0x0105))
- {
- Notify (C105, Arg1)
- }
-
- If ((Arg0 == 0x0106))
- {
- Notify (C106, Arg1)
- }
-
[snip]
- If ((Arg0 == 0x0112))
- {
- Notify (C112, Arg1)
- }
}
Method (CSTA, 1, Serialized)
{
Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
\_SB.PCI0.PRES.CSEL = Arg0
Local0 = Zero
If ((\_SB.PCI0.PRES.CPEN == One))
{
Local0 = 0x0F
}
Release (\_SB.PCI0.PRES.CPLK)
Return (Local0)
}
@@ -4306,33 +4231,33 @@
\_SB.PCI0.PRES.CSEL = Arg0
\_SB.PCI0.PRES.CEJ0 = One
Release (\_SB.PCI0.PRES.CPLK)
}
Method (CSCN, 0, Serialized)
{
Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
Name (CNEW, Package (0xFF) {})
Local3 = Zero
Local4 = One
While ((Local4 == One))
{
Local4 = Zero
Local0 = One
Local1 = Zero
- While (((Local0 == One) && (Local3 < 0x0113)))
+ While (((Local0 == One) && (Local3 < 0x0104)))
{
Local0 = Zero
\_SB.PCI0.PRES.CSEL = Local3
\_SB.PCI0.PRES.CCMD = Zero
If ((\_SB.PCI0.PRES.CDAT < Local3))
{
Break
}
If ((Local1 == 0xFF))
{
Local4 = One
Break
}
Local3 = \_SB.PCI0.PRES.CDAT
@@ -7220,3281 +7145,3281 @@
Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
{
0x00, 0x08, 0x81, 0x81, 0x01, 0x00, 0x00, 0x00 //
........
})
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
CEJ0 (0x81)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
COST (0x81, Arg0, Arg1, Arg2)
}
}
- Processor (C082, 0x82, 0x00000000, 0x00)
+ Device (C082)
{
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID:
Hardware ID
+ Name (_UID, 0x82) // _UID: Unique ID
Method (_STA, 0, Serialized) // _STA: Status
{
Return (CSTA (0x82))
}
- Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry
{
- 0x00, 0x08, 0x82, 0x82, 0x01, 0x00, 0x00, 0x00 //
........
+ /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00,
0x00, // ........
+ /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x82, 0x00, 0x00, 0x00
// ........
})
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
CEJ0 (0x82)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
COST (0x82, Arg0, Arg1, Arg2)
}
}
- Processor (C083, 0x83, 0x00000000, 0x00)
+ Device (C083)
{
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID:
Hardware ID
+ Name (_UID, 0x83) // _UID: Unique ID
Method (_STA, 0, Serialized) // _STA: Status
{
Return (CSTA (0x83))
}
- Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry
{
- 0x00, 0x08, 0x83, 0x83, 0x01, 0x00, 0x00, 0x00 //
........
+ /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x01, 0x01, 0x00,
0x00, // ........
+ /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x83, 0x00, 0x00, 0x00
// ........
})
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
CEJ0 (0x83)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
COST (0x83, Arg0, Arg1, Arg2)
}
}
- Processor (C084, 0x84, 0x00000000, 0x00)
+ Device (C084)
{
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID:
Hardware ID
+ Name (_UID, 0x84) // _UID: Unique ID
Method (_STA, 0, Serialized) // _STA: Status
{
Return (CSTA (0x84))
}
- Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry
{
- 0x00, 0x08, 0x84, 0x84, 0x01, 0x00, 0x00, 0x00 //
........
+ /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x02, 0x01, 0x00,
0x00, // ........
+ /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x00
// ........
})
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
CEJ0 (0x84)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
COST (0x84, Arg0, Arg1, Arg2)
}
}
[snip]
- Processor (C0FE, 0xFE, 0x00000000, 0x00)
+ Device (C0FE)
{
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID:
Hardware ID
+ Name (_UID, 0xFE) // _UID: Unique ID
Method (_STA, 0, Serialized) // _STA: Status
{
Return (CSTA (0xFE))
}
- Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry
{
- 0x00, 0x08, 0xFE, 0xFE, 0x01, 0x00, 0x00, 0x00 //
........
+ /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0x7C, 0x01, 0x00,
0x00, // ....|...
+ /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00
// ........
})
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
CEJ0 (0xFE)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
COST (0xFE, Arg0, Arg1, Arg2)
}
}
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231023094635.1588282-11-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 85ccbe1275b58efe9e30d229c942d33144b5ef6f
https://github.com/qemu/qemu/commit/85ccbe1275b58efe9e30d229c942d33144b5ef6f
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
A tests/data/acpi/q35/APIC.thread-count
A tests/data/acpi/q35/DSDT.thread-count
A tests/data/acpi/q35/FACP.thread-count
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: bios-tables-test: Prepare the ACPI table change for smbios type4
thread count test
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 1 - 3.
List the ACPI tables that will be added to test the thread count field
of smbios type4 table.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231023094635.1588282-12-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 7ee18dcef14540c79892381d7af0a2c54ec11484
https://github.com/qemu/qemu/commit/7ee18dcef14540c79892381d7af0a2c54ec11484
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M tests/qtest/bios-tables-test.c
Log Message:
-----------
tests: bios-tables-test: Add test for smbios type4 thread count
This tests the commit 7298fd7de5551 ("hw/smbios: Fix thread count in
type4").
In smbios_build_type_4_table() (hw/smbios/smbios.c), if the number of
threads in the socket is not more than 255, then smbios type4 table
encodes threads per socket into the thread count field.
So for the topology in this case, there're the following considerations:
1. threads per socket should be not more than 255 to ensure we could
cover the thread count field.
2. The original bug was that threads per socket was miscalculated, so
now we should configure as many topology levels as possible (multiple
sockets & dies, no module since x86 hasn't supported it) to cover
more general topology scenarios, to ensure that the threads per
socket encoded in the thread count field is correct.
3. For the more general topology, we should also add "cpus" (presented
threads for machine) and "maxcpus" (total threads for machine) to
make sure that configuring unpluged CPUs in smp (cpus < maxcpus)
does not affect the correctness of threads per socket for thread
count field.
Based on these considerations, select the topology as the follow:
-smp cpus=15,maxcpus=54,sockets=2,dies=3,cores=3,threads=3
The expected thread count = threads per socket = threads (3) * cores (3)
* dies (3) = 27.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231023094635.1588282-13-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: a775cb191e85c86a1b43f0d082cf9fa7f6d80464
https://github.com/qemu/qemu/commit/a775cb191e85c86a1b43f0d082cf9fa7f6d80464
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M tests/data/acpi/q35/APIC.thread-count
M tests/data/acpi/q35/DSDT.thread-count
M tests/data/acpi/q35/FACP.thread-count
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread
count test
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
FACP:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-1NP791, Wed Aug 23 21:51:31 2023
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI
Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : B3
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0002
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 1
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000484A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 1
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
...
APIC:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-2JP791, Wed Aug 23 21:51:31 2023
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC
Description Table (MADT)]
+[004h 0004 4] Table Length : 00000220
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : 63
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 00 [Processor Local APIC]
+[035h 0053 1] Length : 08
+[036h 0054 1] Processor ID : 01
+[037h 0055 1] Local Apic ID : 01
+[038h 0056 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
[snip]
+[1D4h 0468 1] Subtable Type : 00 [Processor Local APIC]
+[1D5h 0469 1] Length : 08
+[1D6h 0470 1] Processor ID : 35
+[1D7h 0471 1] Local Apic ID : 6A
+[1D8h 0472 4] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+ Runtime Online Capable : 0
+
+[1DCh 0476 1] Subtable Type : 01 [I/O APIC]
+[1DDh 0477 1] Length : 0C
+[1DEh 0478 1] I/O Apic ID : 00
+[1DFh 0479 1] Reserved : 00
+[1E0h 0480 4] Address : FEC00000
+[1E4h 0484 4] Interrupt : 00000000
+
+[1E8h 0488 1] Subtable Type : 02 [Interrupt Source Override]
+[1E9h 0489 1] Length : 0A
+[1EAh 0490 1] Bus : 00
+[1EBh 0491 1] Source : 00
+[1ECh 0492 4] Interrupt : 00000002
+[1F0h 0496 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[1F2h 0498 1] Subtable Type : 02 [Interrupt Source Override]
+[1F3h 0499 1] Length : 0A
+[1F4h 0500 1] Bus : 00
+[1F5h 0501 1] Source : 05
+[1F6h 0502 4] Interrupt : 00000005
+[1FAh 0506 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[1FCh 0508 1] Subtable Type : 02 [Interrupt Source Override]
+[1FDh 0509 1] Length : 0A
+[1FEh 0510 1] Bus : 00
+[1FFh 0511 1] Source : 09
+[200h 0512 4] Interrupt : 00000009
+[204h 0516 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[206h 0518 1] Subtable Type : 02 [Interrupt Source Override]
+[207h 0519 1] Length : 0A
+[208h 0520 1] Bus : 00
+[209h 0521 1] Source : 0A
+[20Ah 0522 4] Interrupt : 0000000A
+[20Eh 0526 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[210h 0528 1] Subtable Type : 02 [Interrupt Source Override]
+[211h 0529 1] Length : 0A
+[212h 0530 1] Bus : 00
+[213h 0531 1] Source : 0B
+[214h 0532 4] Interrupt : 0000000B
+[218h 0536 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[21Ah 0538 1] Subtable Type : 04 [Local APIC NMI]
+[21Bh 0539 1] Length : 06
+[21Ch 0540 1] Processor ID : FF
+[21Dh 0541 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[21Fh 0543 1] Interrupt Input LINT : 01
...
DSDT:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of /tmp/aml-00O791, Wed Aug 23 21:51:31 2023
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x00003271 (12913)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0xAF
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPC "
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
[snip]
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 //
........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+ }
+
+ Processor (C001, 0x01, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (One))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 //
........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (One)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (One, Arg0, Arg1, Arg2)
+ }
+ }
[snip]
+ Processor (C035, 0x35, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x35))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x35, 0x6A, 0x01, 0x00, 0x00, 0x00 //
..5j....
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x35)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x35, Arg0, Arg1, Arg2)
+ }
+ }
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231023094635.1588282-14-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 7cb953ca1956d4ac5d8ad798321fe3fde765befc
https://github.com/qemu/qemu/commit/7cb953ca1956d4ac5d8ad798321fe3fde765befc
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
A tests/data/acpi/q35/APIC.thread-count2
A tests/data/acpi/q35/DSDT.thread-count2
A tests/data/acpi/q35/FACP.thread-count2
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: bios-tables-test: Prepare the ACPI table change for smbios type4
thread count2 test
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 1 - 3.
List the ACPI tables that will be added to test the thread count2 field
of smbios type4 table.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231023094635.1588282-15-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 198eee0cc17d74f17ecd54ddf72681f421f7bc43
https://github.com/qemu/qemu/commit/198eee0cc17d74f17ecd54ddf72681f421f7bc43
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M tests/qtest/bios-tables-test.c
Log Message:
-----------
tests: bios-tables-test: Add test for smbios type4 thread count2
This tests the commit 7298fd7de5551 ("hw/smbios: Fix thread count in
type4").
In smbios_build_type_4_table() (hw/smbios/smbios.c), if the number of
threads in the socket is more than 255, then smbios type4 table encodes
threads per socket into the thread count2 field.
So for the topology in this case, there're the following considerations:
1. threads per socket should be more than 255 to ensure we could cover
the thread count2 field.
2. The original bug was that threads per socket was miscalculated, so
now we should configure as many topology levels as possible (multiple
dies, no module since x86 hasn't supported it) to cover more general
topology scenarios, to ensure that the threads per socket encoded in
the thread count2 field is correct.
3. For the more general topology, we should also add "cpus" (presented
threads for machine) and "maxcpus" (total threads for machine) to
make sure that configuring unpluged CPUs in smp (cpus < maxcpus)
does not affect the correctness of threads per socket for thread
count2 field.
Note we don't consider the topology with multiple sockets since this
topology would create too many vCPUs (more than 255 threads per socket
with at least 2 sockets, which may cause the failure "Number of
hotpluggable cpus requested (*) exceeds the maximum cpus supported by
KVM (*) socket_accept failed: Resource temporarily unavailable"), and
the calculation of threads per socket has already been covered by
"thread count" test case.
Based on these considerations, select the topology as the follow:
-smp cpus=210,maxcpus=260,dies=2,cores=65,threads=2
The expected thread count2 = threads per socket = threads (2)
* cores (65) * dies (2) = 260.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20231023094635.1588282-16-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: f58db4eeb1c7f850de86d4efece653d1018f6eae
https://github.com/qemu/qemu/commit/f58db4eeb1c7f850de86d4efece653d1018f6eae
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M tests/data/acpi/q35/APIC.thread-count2
M tests/data/acpi/q35/DSDT.thread-count2
M tests/data/acpi/q35/FACP.thread-count2
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread
count2 test
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 5 and 6.
Changes in the tables:
FACP:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-CNE3C2, Mon Oct 23 15:25:01 2023
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI
Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : B3
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0002
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 1
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000484A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 1
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
...
APIC:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembly of /tmp/aml-WKE3C2, Mon Oct 23 15:25:01 2023
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC
Description Table (MADT)]
+[004h 0004 4] Table Length : 00000CA6
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : 2C
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPC "
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 00 [Processor Local APIC]
+[035h 0053 1] Length : 08
+[036h 0054 1] Processor ID : 01
+[037h 0055 1] Local Apic ID : 01
+[038h 0056 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
[snip]
+[434h 1076 1] Subtable Type : 00 [Processor Local APIC]
+[435h 1077 1] Length : 08
+[436h 1078 1] Processor ID : 81
+[437h 1079 1] Local Apic ID : 81
+[438h 1080 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[43Ch 1084 1] Subtable Type : 09 [Processor Local x2APIC]
+[43Dh 1085 1] Length : 10
+[43Eh 1086 2] Reserved : 0000
+[440h 1088 4] Processor x2Apic ID : 00000100
+[444h 1092 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+[448h 1096 4] Processor UID : 00000082
[snip]
+[C4Ch 3148 1] Subtable Type : 09 [Processor Local x2APIC]
+[C4Dh 3149 1] Length : 10
+[C4Eh 3150 2] Reserved : 0000
+[C50h 3152 4] Processor x2Apic ID : 00000181
+[C54h 3156 4] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+[C58h 3160 4] Processor UID : 00000103
+
+[C5Ch 3164 1] Subtable Type : 01 [I/O APIC]
+[C5Dh 3165 1] Length : 0C
+[C5Eh 3166 1] I/O Apic ID : 00
+[C5Fh 3167 1] Reserved : 00
+[C60h 3168 4] Address : FEC00000
+[C64h 3172 4] Interrupt : 00000000
+
+[C68h 3176 1] Subtable Type : 02 [Interrupt Source Override]
+[C69h 3177 1] Length : 0A
+[C6Ah 3178 1] Bus : 00
+[C6Bh 3179 1] Source : 00
+[C6Ch 3180 4] Interrupt : 00000002
+[C70h 3184 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
[snip]
+[C90h 3216 1] Subtable Type : 02 [Interrupt Source Override]
+[C91h 3217 1] Length : 0A
+[C92h 3218 1] Bus : 00
+[C93h 3219 1] Source : 0B
+[C94h 3220 4] Interrupt : 0000000B
+[C98h 3224 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[C9Ah 3226 1] Subtable Type : 0A [Local x2APIC NMI]
+[C9Bh 3227 1] Length : 0C
+[C9Ch 3228 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[C9Eh 3230 4] Processor UID : FFFFFFFF
+[CA2h 3234 1] Interrupt Input LINT : 01
+[CA3h 3235 3] Reserved : 000000
...
DSDT:
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20200925 (64-bit version)
+ * Copyright (c) 2000 - 2020 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of /tmp/aml-CDE3C2, Mon Oct 23 15:25:01 2023
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x000083EA (33770)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0x01
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPC "
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
[snip]
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 //
........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+ }
[snip]
+ Processor (C081, 0x81, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x81))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x81, 0x81, 0x01, 0x00, 0x00, 0x00 //
........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x81)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x81, Arg0, Arg1, Arg2)
+ }
+ }
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20231023094635.1588282-17-zhao1.liu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 629df5cc23cc9aec5d115cc9be3456458e2b44fa
https://github.com/qemu/qemu/commit/629df5cc23cc9aec5d115cc9be3456458e2b44fa
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/cxl/cxl-device-utils.c
Log Message:
-----------
hw/cxl: Use a switch to explicitly check size in caps_reg_read()
Bring this read function inline with the others that do
check for unexpected size values.
Also reduces line lengths to sub 80 chars.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Message-Id: <20231023140210.3089-2-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 388d6b574e282b02e8180f4cba428316a404deea
https://github.com/qemu/qemu/commit/388d6b574e282b02e8180f4cba428316a404deea
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/cxl/cxl-component-utils.c
Log Message:
-----------
hw/cxl: Use switch statements for read and write of cachemem registers
Establishing that only register accesses of size 4 and 8 can occur
using these functions requires looking at their callers. Make it
easier to see that by using switch statements.
Assertions are used to enforce that the register storage is of the
matching size, allowing fixed values to be used for divisors of
the array indices.
Suggested-by: Michael Tokarev <mjt@tls.msk.ru>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Message-Id: <20231023140210.3089-3-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: b34ae3c9064a976e718dc96e454d32c1d8409eba
https://github.com/qemu/qemu/commit/b34ae3c9064a976e718dc96e454d32c1d8409eba
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/cxl/cxl-component-utils.c
M hw/pci-bridge/cxl_downstream.c
M hw/pci-bridge/cxl_root_port.c
M hw/pci-bridge/cxl_upstream.c
M include/hw/cxl/cxl_pci.h
Log Message:
-----------
hw/cxl: CXLDVSECPortExtensions renamed to CXLDVSECPortExt
Done to reduce line lengths where this is used.
Ext seems sufficiently obvious that it need not be spelt out
fully.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Message-Id: <20231023140210.3089-4-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: b342489ae795f5c2a9f7a565bac8443ccb11b0ce
https://github.com/qemu/qemu/commit/b342489ae795f5c2a9f7a565bac8443ccb11b0ce
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/cxl/cxl-cdat.c
M hw/cxl/cxl-component-utils.c
M hw/cxl/cxl-events.c
M hw/cxl/cxl-mailbox-utils.c
M hw/mem/cxl_type3.c
M hw/mem/cxl_type3_stubs.c
M include/hw/cxl/cxl_component.h
M include/hw/cxl/cxl_device.h
M include/hw/cxl/cxl_events.h
Log Message:
-----------
hw/cxl: Line length reductions
Michael Tsirkin observed that there were some unnecessarily
long lines in the CXL code in a recent review.
This patch is intended to rectify that where it does not
hurt readability.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Michael Tokarev <mjt@tls.msk.ru>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Message-Id: <20231023140210.3089-5-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 45234c2dd2920f16f768bda1ec8353bda8c5a929
https://github.com/qemu/qemu/commit/45234c2dd2920f16f768bda1ec8353bda8c5a929
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/cxl/cxl-component-utils.c
Log Message:
-----------
hw/cxl: Fix a QEMU_BUILD_BUG_ON() in switch statement scope issue.
As _Static_assert is a declaration, it can't follow a label until C23.
Some older versions of GCC trip up on this one.
This check has no obvious purpose so just remove it.
Reported-by: Jeongtae Park <jtp.park@samsung.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20231023140210.3089-6-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: a7bb53b1eee6836d29003a8ffbd2c2c4c55a40c2
https://github.com/qemu/qemu/commit/a7bb53b1eee6836d29003a8ffbd2c2c4c55a40c2
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
M include/hw/cxl/cxl_device.h
Log Message:
-----------
hw/cxl/mbox: Pull the payload out of struct cxl_cmd and make instances
constant
Putting the pointer in the structure for command handling puts a single
variable element inside an otherwise constant structure. Move it out as
a directly passed variable and take the cxl_cmd structures constant.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Message-Id: <20231023160806.13206-2-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 6f59274e937576fbb2623b687aa2556e115a712f
https://github.com/qemu/qemu/commit/6f59274e937576fbb2623b687aa2556e115a712f
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/cxl/cxl-events.c
M hw/cxl/cxl-mailbox-utils.c
M include/hw/cxl/cxl_device.h
Log Message:
-----------
hw/cxl/mbox: Split mailbox command payload into separate input and output
New CCI types that will be supported shortly do not have a single buffer
used in both directions. As such, split it up. To avoid the complexities
of implementing all commands to handle potential aliasing, take a copy of
the input before use.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20231023160806.13206-3-Jonathan.Cameron@huawei.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: cac36a8faffc62ba6b07d8e9dfdc9fbf15c7d1bf
https://github.com/qemu/qemu/commit/cac36a8faffc62ba6b07d8e9dfdc9fbf15c7d1bf
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/cxl/cxl-device-utils.c
M hw/cxl/cxl-mailbox-utils.c
M hw/mem/cxl_type3.c
M include/hw/cxl/cxl_device.h
Log Message:
-----------
hw/cxl/mbox: Pull the CCI definition out of the CXLDeviceState
Enables having multiple CCIs per devices. Each CCI (mailbox) has it's own
state and command list, so they can't share a single structure.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20231023160806.13206-4-Jonathan.Cameron@huawei.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: c9460561edbd8b2d4adbf1f7c5cb4ad4d210de4c
https://github.com/qemu/qemu/commit/c9460561edbd8b2d4adbf1f7c5cb4ad4d210de4c
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/cxl/cxl-device-utils.c
M hw/cxl/cxl-mailbox-utils.c
M include/hw/cxl/cxl_device.h
Log Message:
-----------
hw/cxl/mbox: Generalize the CCI command processing
By moving the parts of the mailbox command handling that are CCI type
specific out to the caller, make the main handling code generic. Rename it
to cxl_process_cci_message() to reflect this new generality.
Change the type3 mailbox handling (reused shortly for the switch
mailbox CCI) to take a snapshot of the mailbox input data rather
than operating on it in place. This reduces the chance of bugs
due to aliasing going forwars.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20231023160806.13206-5-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 2710d49a7c8b9b117a46847c7ace5eb21d48e882
https://github.com/qemu/qemu/commit/2710d49a7c8b9b117a46847c7ace5eb21d48e882
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/pci-bridge/cxl_upstream.c
A include/hw/pci-bridge/cxl_upstream_port.h
Log Message:
-----------
hw/pci-bridge/cxl_upstream: Move defintion of device to header.
To avoid repetition of switch upstream port specific data in the
CXLDeviceState structure it will be necessary to access the switch USP
specific data from mailbox callbacks. Hence move it to cxl_device.h so it
is no longer an opaque structure.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Message-Id: <20231023160806.13206-6-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 4a58330343e6a16f6828e225fd0c054c8d1916bd
https://github.com/qemu/qemu/commit/4a58330343e6a16f6828e225fd0c054c8d1916bd
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/cxl/cxl-device-utils.c
M hw/cxl/cxl-mailbox-utils.c
M hw/cxl/meson.build
A hw/cxl/switch-mailbox-cci.c
M include/hw/cxl/cxl_component.h
M include/hw/cxl/cxl_device.h
M include/hw/pci-bridge/cxl_upstream_port.h
Log Message:
-----------
hw/cxl: Add a switch mailbox CCI function
CXL switch CCIs were added in CXL r3.0. They are a PCI function,
identified by class code that provides a CXL mailbox (identical
to that previously defined for CXL type 3 memory devices) over which
various FM-API commands may be used. Whilst the intent of this
feature is enable switch control from a BMC attached to a switch
upstream port, it is also useful to allow emulation of this feature
on the upstream port connected to a host using the CXL devices as
this greatly simplifies testing.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20231023160806.13206-7-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 6cf416c176f11bc093fcc1818d6c9a95136f4c59
https://github.com/qemu/qemu/commit/6cf416c176f11bc093fcc1818d6c9a95136f4c59
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
Log Message:
-----------
hw/cxl/mbox: Add Information and Status / Identify command
Add this command that is only available via out of band CCIs. It replicates
information that can be discovered inband via PCI config space.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20231023160806.13206-8-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 3314efd276ada18cc0b8beb70b8943f8deb872b7
https://github.com/qemu/qemu/commit/3314efd276ada18cc0b8beb70b8943f8deb872b7
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
M hw/pci-bridge/cxl_downstream.c
M include/hw/cxl/cxl.h
Log Message:
-----------
hw/cxl/mbox: Add Physical Switch Identify command.
Enable it for the switch CCI.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20231023160806.13206-9-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 314f5033c639ebe8218078a17513935747f15d9d
https://github.com/qemu/qemu/commit/314f5033c639ebe8218078a17513935747f15d9d
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/pci-bridge/cxl_downstream.c
Log Message:
-----------
hw/pci-bridge/cxl_downstream: Set default link width and link speed
Without these being set the PCIE Link Capabilities register has
invalid values in these two fields.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20231023160806.13206-10-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 892e3479d7283a38b50e06f42624f5a1ce61d24a
https://github.com/qemu/qemu/commit/892e3479d7283a38b50e06f42624f5a1ce61d24a
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
Log Message:
-----------
hw/cxl: Implement Physical Ports status retrieval
Add this command for both the Switch CCI in switch upstream ports.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20231023160806.13206-11-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 221d2cfbdb5301f8f0cfbf26baf76544a5d71c27
https://github.com/qemu/qemu/commit/221d2cfbdb5301f8f0cfbf26baf76544a5d71c27
Author: Davidlohr Bueso <dave@stgolabs.net>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/cxl/cxl-device-utils.c
M hw/cxl/cxl-mailbox-utils.c
M include/hw/cxl/cxl_device.h
Log Message:
-----------
hw/cxl/mbox: Add support for background operations
Support background commands in the mailbox, and update
cmd_infostat_bg_op_sts() accordingly. This patch does not implement mbox
interrupts upon completion, so the kernel driver must rely on polling to
know when the operation is done.
Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20231023160806.13206-12-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 43efb0bfad2b81b32fc19da442cbea2835cf38d4
https://github.com/qemu/qemu/commit/43efb0bfad2b81b32fc19da442cbea2835cf38d4
Author: Davidlohr Bueso <dave@stgolabs.net>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/cxl/cxl-device-utils.c
M hw/cxl/cxl-mailbox-utils.c
M include/hw/cxl/cxl_device.h
Log Message:
-----------
hw/cxl/mbox: Wire up interrupts for background completion
Notify when the background operation is done. Note that for now background
commands are only supported on the main Type 3 mailbox.
Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20231023160806.13206-13-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 25a52959f99d6860a186175bda898e3bdb605f91
https://github.com/qemu/qemu/commit/25a52959f99d6860a186175bda898e3bdb605f91
Author: Davidlohr Bueso <dave@stgolabs.net>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
M hw/mem/cxl_type3.c
M include/hw/cxl/cxl_device.h
Log Message:
-----------
hw/cxl: Add support for device sanitation
Make use of the background operations through the sanitize command, per CXL
3.0 specs. Traditionally run times can be rather long, depending on the
size of the media.
Estimate times based on:
https://pmem.io/documents/NVDIMM_DSM_Interface-V1.8.pdf
Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20231023160806.13206-14-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 9dd15ab6e6b35db6ff166e5016b0c2042c5439c6
https://github.com/qemu/qemu/commit/9dd15ab6e6b35db6ff166e5016b0c2042c5439c6
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
Log Message:
-----------
hw/cxl/mbox: Add Get Background Operation Status Command
For now, provide this command on type 3 main mailbox only.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20231023160806.13206-15-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: ede604d505d711e45abcc37dd4389967fda410d7
https://github.com/qemu/qemu/commit/ede604d505d711e45abcc37dd4389967fda410d7
Author: Gregory Price <gourry.memverge@gmail.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/mem/cxl_type3.c
Log Message:
-----------
hw/cxl/type3: Cleanup multiple CXL_TYPE3() calls in read/write functions
Call CXL_TYPE3 once at top of function to avoid multiple invocations.
Signed-off-by: Gregory Price <gregory.price@memverge.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20231023160806.13206-16-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 44e4b316e4bf8f7327f3917c25aae38172695680
https://github.com/qemu/qemu/commit/44e4b316e4bf8f7327f3917c25aae38172695680
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
Log Message:
-----------
hw/cxl: Add dummy security state get
Needed to allow the santize comamnds to be tested with proposed Linux Kernel
support. Default value + no control of the security state will work for now.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20231023160806.13206-17-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 004e3a93b814ca2d13ee2feb1f9ebacef6c83b9e
https://github.com/qemu/qemu/commit/004e3a93b814ca2d13ee2feb1f9ebacef6c83b9e
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
M hw/mem/cxl_type3.c
M include/hw/cxl/cxl_device.h
Log Message:
-----------
hw/cxl: Add tunneled command support to mailbox for switch cci.
This implementation of tunneling makes the choice that our Type 3 device is
a Logical Device (LD) of a Multi-Logical Device (MLD) that just happens to
only have one LD for now.
Tunneling is supported from a Switch Mailbox CCI (and shortly via MCTP over
I2C connected to the switch MCTP CCI) via an outer level to the FM owned LD
in the MLD Type 3 device. From there an inner tunnel may be used to access
particular LDs.
Protocol wise, the following is what happens in a real system but we
don't emulate the transports - just the destinations and the payloads.
( Host -> Switch Mailbox CCI - in band FM-API mailbox command
or
Host -> Switch MCTP CCI - MCTP over I2C using the CXL FM-API
MCTP Binding.
)
then (if a tunnel command)
Switch -> Type 3 FM Owned LD - MCTP over PCI VDM using the
CXL FM-API binding (addressed by switch port)
then (if unwrapped command also a tunnel command)
Type 3 FM Owned LD to LD0 via internal transport
(addressed by LD number)
or (added shortly)
Host to Type 3 FM Owned MCTP CCI - MCTP over I2C using the
CXL FM-API MCTP Binding.
then (if unwrapped comand is a tunnel comamnd)
Type 3 FM Owned LD to LD0 via internal transport.
(addressed by LD number)
It is worth noting that the tunneling commands over PCI VDM
presumably use the appropriate MCTP binding depending on opcode.
This may be the CXL FMAPI binding or the CXL Memory Device Binding.
Additional commands will need to be added to make this
useful beyond testing the tunneling works.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20231023160806.13206-18-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: a874ddc95a2b8b4b6303366c6ac6a2be53c41be4
https://github.com/qemu/qemu/commit/a874ddc95a2b8b4b6303366c6ac6a2be53c41be4
Author: Ani Sinha <anisinha@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M tests/avocado/acpi-bits.py
Log Message:
-----------
acpi/tests/avocado/bits: enforce 32-bit SMBIOS entry point
QEMU defaults to 64-bit entry point since the following commit
bf376f3020 ("hw/i386/pc: Default to use SMBIOS 3.0 for newer machine models")
The above change is applicable for all newer machine versions from version 8.1
and newer. i440fx and q35 machine versions 8.0 and older still use 32-bit entry
points.
Unfortunately, bits currently does not recognize 64-bit entry points and hence
is not able to parse SMBIOS tables. Therefore, we need to enforce 32-bit
SMBIOS entry point in QEMU command line so that bits is able to parse the
SMBIOS tables.
Once we implement the support in bits to parse 64-bit entry points, we can
remove the extra command line that is passed to enforce a 32-bit entry point.
The support can be added to the following smbios test script:
tests/avocado/acpi-bits/bits-tests/smbios.py2 in QEMU repository.
CC: jusual@redhat.com
CC: imammedo@redhat.com
Signed-off-by: Ani Sinha <anisinha@redhat.com>
Message-Id: <20231027032120.6012-2-anisinha@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 94cd94f1c0137b56000c01208e03d0907ad34910
https://github.com/qemu/qemu/commit/94cd94f1c0137b56000c01208e03d0907ad34910
Author: Ani Sinha <anisinha@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M tests/avocado/acpi-bits.py
Log Message:
-----------
acpi/tests/avocado/bits: enable console logging from bits VM
Console logs from the VM can be useful for debugging when things go wrong.
Other avocado tests enables them. This change enables console logging with the
following changes:
- point to the newer bios bits image that actually enabled VM console.
- change the bits test to drain the console logs from the VM and write the
logs.
- wait for SHUTDOWN event from QEMU so that console logs can be drained out
of the socket before it is closed as a part of vm.wait().
Additionally, following two cosmetic changes have been made:
- Removed VM QEMU command line logging as avocado framework already logs it.
This is a minor cleanup along the way.
- Update my email to my work email in the avocado acpi bios bits test.
CC: jsnow@redhat.com
Signed-off-by: Ani Sinha <anisinha@redhat.com>
Message-Id: <20231027032120.6012-3-anisinha@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 547c9757ddc4f83358e7187a6db9c05125dda2a2
https://github.com/qemu/qemu/commit/547c9757ddc4f83358e7187a6db9c05125dda2a2
Author: David Woodhouse <dwmw@amazon.co.uk>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/i386/kvm/xen-emu.c
Log Message:
-----------
i386/xen: Ignore VCPU_SSHOTTMR_future flag in set_singleshot_timer()
Upstream Xen now ignores this flag¹, since the only guest kernel ever to
use it was buggy.
¹ https://xenbits.xen.org/gitweb/?p=xen.git;a=commitdiff;h=19c6cbd909
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Paul Durrant <paul@xen.org>
Commit: be15509882f2a745ec81a52d023864f077c13182
https://github.com/qemu/qemu/commit/be15509882f2a745ec81a52d023864f077c13182
Author: David Woodhouse <dwmw@amazon.co.uk>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/i386/kvm/xen_evtchn.c
Log Message:
-----------
hw/xen: Clean up event channel 'type_val' handling to use union
A previous implementation of this stuff used a 64-bit field for all of
the port information (vcpu/type/type_val) and did atomic exchanges on
them. When I implemented that in Qemu I regretted my life choices and
just kept it simple with locking instead.
So there's no need for the XenEvtchnPort to be so simplistic. We can
use a union for the pirq/virq/interdomain information, which lets us
keep a separate bit for the 'remote domain' in interdomain ports. A
single bit is enough since the only possible targets are loopback or
qemu itself.
So now we can ditch PORT_INFO_TYPEVAL_REMOTE_QEMU and the horrid
manual masking, although the in-memory representation is identical
so there's no change in the saved state ABI.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Paul Durrant <paul@xen.org>
Commit: 8ac98aeddaac1778e7c725609f1fd5eaa38e2285
https://github.com/qemu/qemu/commit/8ac98aeddaac1778e7c725609f1fd5eaa38e2285
Author: David Woodhouse <dwmw@amazon.co.uk>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/i386/kvm/xen_xenstore.c
M include/hw/xen/interface/arch-arm.h
M include/hw/xen/interface/arch-x86/cpuid.h
M include/hw/xen/interface/arch-x86/xen-x86_32.h
M include/hw/xen/interface/arch-x86/xen-x86_64.h
M include/hw/xen/interface/arch-x86/xen.h
M include/hw/xen/interface/event_channel.h
M include/hw/xen/interface/features.h
M include/hw/xen/interface/grant_table.h
M include/hw/xen/interface/hvm/hvm_op.h
M include/hw/xen/interface/hvm/params.h
M include/hw/xen/interface/io/blkif.h
M include/hw/xen/interface/io/console.h
M include/hw/xen/interface/io/fbif.h
M include/hw/xen/interface/io/kbdif.h
M include/hw/xen/interface/io/netif.h
M include/hw/xen/interface/io/protocols.h
M include/hw/xen/interface/io/ring.h
M include/hw/xen/interface/io/usbif.h
M include/hw/xen/interface/io/xenbus.h
M include/hw/xen/interface/io/xs_wire.h
M include/hw/xen/interface/memory.h
M include/hw/xen/interface/physdev.h
M include/hw/xen/interface/sched.h
M include/hw/xen/interface/trace.h
M include/hw/xen/interface/vcpu.h
M include/hw/xen/interface/version.h
M include/hw/xen/interface/xen-compat.h
M include/hw/xen/interface/xen.h
Log Message:
-----------
include: update Xen public headers to Xen 4.17.2 release
... in order to advertise the XEN_HVM_CPUID_UPCALL_VECTOR feature,
which will come in a subsequent commit.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Acked-by: Paul Durrant <paul@xen.org>
Commit: 8473607bcfef62fd8f6bb98b27807bbfce30a81a
https://github.com/qemu/qemu/commit/8473607bcfef62fd8f6bb98b27807bbfce30a81a
Author: David Woodhouse <dwmw@amazon.co.uk>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M target/i386/kvm/kvm.c
Log Message:
-----------
i386/xen: advertise XEN_HVM_CPUID_UPCALL_VECTOR in CPUID
This will allow Linux guests (since v6.0) to use the per-vCPU upcall
vector delivered as MSI through the local APIC.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Paul Durrant <paul@xen.org>
Commit: d388c9f53b971fd185ee1dc2f4f3ca88abda906d
https://github.com/qemu/qemu/commit/d388c9f53b971fd185ee1dc2f4f3ca88abda906d
Author: David Woodhouse <dwmw@amazon.co.uk>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/i386/kvm/xen_xenstore.c
Log Message:
-----------
hw/xen: populate store frontend nodes with XenStore PFN/port
This is kind of redundant since without being able to get these through
some other method (HVMOP_get_param) the guest wouldn't be able to access
XenStore in order to find them.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Paul Durrant <paul@xen.org>
Commit: d3256f88d988809ae006aa28d6df88b37b253bc1
https://github.com/qemu/qemu/commit/d3256f88d988809ae006aa28d6df88b37b253bc1
Author: David Woodhouse <dwmw@amazon.co.uk>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M blockdev.c
M hw/block/xen-block.c
M hw/xen/xen_devconfig.c
M hw/xenpv/xen_machine_pv.c
M include/hw/xen/xen-legacy-backend.h
Log Message:
-----------
hw/xen: automatically assign device index to block devices
There's no need to force the user to assign a vdev. We can automatically
assign one, starting at xvda and searching until we find the first disk
name that's unused.
This means we can now allow '-drive if=xen,file=xxx' to work without an
explicit separate -driver argument, just like if=virtio.
Rip out the legacy handling from the xenpv machine, which was scribbling
over any disks configured by the toolstack, and didn't work with anything
but raw images.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Acked-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Paul Durrant <paul@xen.org>
Commit: 523b6b3abac928ff3574d8a45df58d29bd8ae454
https://github.com/qemu/qemu/commit/523b6b3abac928ff3574d8a45df58d29bd8ae454
Author: David Woodhouse <dwmw@amazon.co.uk>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/xen/xen-bus.c
M include/hw/xen/xen-bus.h
Log Message:
-----------
hw/xen: add get_frontend_path() method to XenDeviceClass
The primary Xen console is special. The guest's side is set up for it by
the toolstack automatically and not by the standard PV init sequence.
Accordingly, its *frontend* doesn't appear in …/device/console/0 either;
instead it appears under …/console in the guest's XenStore node.
To allow the Xen console driver to override the frontend path for the
primary console, add a method to the XenDeviceClass which can be used
instead of the standard xen_device_get_frontend_path()
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Paul Durrant <paul@xen.org>
Commit: eb6ae7a6829385ca41227e878f5ca3d1faf31d52
https://github.com/qemu/qemu/commit/eb6ae7a6829385ca41227e878f5ca3d1faf31d52
Author: David Woodhouse <dwmw@amazon.co.uk>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/xen/xen-backend.c
M hw/xen/xen-bus.c
M include/hw/xen/xen-backend.h
Log Message:
-----------
hw/xen: do not repeatedly try to create a failing backend device
If xen_backend_device_create() fails to instantiate a device, the XenBus
code will just keep trying over and over again each time the bus is
re-enumerated, as long as the backend appears online and in
XenbusStateInitialising.
The only thing which prevents the XenBus code from recreating duplicates
of devices which already exist, is the fact that xen_device_realize()
sets the backend state to XenbusStateInitWait. If the attempt to create
the device doesn't get *that* far, that's when it will keep getting
retried.
My first thought was to handle errors by setting the backend state to
XenbusStateClosed, but that doesn't work for XenConsole which wants to
*ignore* any device of type != "ioemu" completely.
So, make xen_backend_device_create() *keep* the XenBackendInstance for a
failed device, and provide a new xen_backend_exists() function to allow
xen_bus_type_enumerate() to check whether one already exists before
creating a new one.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Paul Durrant <paul@xen.org>
Commit: 9b773746908072bf0ec64aec12d02515ebcd717b
https://github.com/qemu/qemu/commit/9b773746908072bf0ec64aec12d02515ebcd717b
Author: David Woodhouse <dwmw@amazon.co.uk>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/char/trace-events
M hw/char/xen_console.c
M hw/xen/xen-legacy-backend.c
Log Message:
-----------
hw/xen: update Xen console to XenDevice model
This allows (non-primary) console devices to be created on the command
line and hotplugged.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Paul Durrant <paul@xen.org>
Commit: a72ccc7fc449748d79914439ddf5c12a6e9fd6a6
https://github.com/qemu/qemu/commit/a72ccc7fc449748d79914439ddf5c12a6e9fd6a6
Author: David Woodhouse <dwmw@amazon.co.uk>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/char/xen_console.c
M hw/i386/kvm/meson.build
M hw/i386/kvm/trace-events
M hw/i386/kvm/xen-stubs.c
M hw/i386/kvm/xen_gnttab.c
A hw/i386/kvm/xen_primary_console.c
A hw/i386/kvm/xen_primary_console.h
M hw/i386/kvm/xen_xenstore.c
M hw/xen/xen-bus.c
M include/hw/xen/xen-bus.h
M target/i386/kvm/xen-emu.c
Log Message:
-----------
hw/xen: add support for Xen primary console in emulated mode
The primary console is special because the toolstack maps a page into
the guest for its ring, and also allocates the guest-side event channel.
The guest's grant table is even primed to export that page using a known
grant ref#. Add support for all that in emulated mode, so that we can
have a primary console.
For reasons unclear, the backends running under real Xen don't just use
a mapping of the well-known GNTTAB_RESERVED_CONSOLE grant ref (which
would also be in the ring-ref node in XenStore). Instead, the toolstack
sets the ring-ref node of the primary console to the GFN of the guest
page. The backend is expected to handle that special case and map it
with foreignmem operations instead.
We don't have an implementation of foreignmem ops for emulated Xen mode,
so just make it map GNTTAB_RESERVED_CONSOLE instead. This would probably
work for real Xen too, but we can't work out how to make real Xen create
a primary console of type "ioemu" to make QEMU drive it, so we can't
test that; might as well leave it as it is for now under Xen.
Now at last we can boot the Xen PV shim and run PV kernels in QEMU.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Paul Durrant <paul@xen.org>
Commit: 25511f3e8c8e0c5a888d1c5de7891f7d287d2dd3
https://github.com/qemu/qemu/commit/25511f3e8c8e0c5a888d1c5de7891f7d287d2dd3
Author: David Woodhouse <dwmw@amazon.co.uk>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/i386/xen/xen_platform.c
Log Message:
-----------
hw/xen: only remove peers of PCI NICs on unplug
When the Xen guest asks to unplug *emulated* NICs, it's kind of unhelpful
also to unplug the peer of the *Xen* PV NIC.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Paul Durrant <paul@xen.org>
Commit: 25967ff69f61461cedf3289d5dafd1f6980cc894
https://github.com/qemu/qemu/commit/25967ff69f61461cedf3289d5dafd1f6980cc894
Author: David Woodhouse <dwmw@amazon.co.uk>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/net/meson.build
M hw/net/trace-events
M hw/net/xen_nic.c
M hw/xenpv/xen_machine_pv.c
Log Message:
-----------
hw/xen: update Xen PV NIC to XenDevice model
This allows us to use Xen PV networking with emulated Xen guests, and to
add them on the command line or hotplug.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Paul Durrant <paul@xen.org>
Commit: c10b4b3c0dcae2fe1836e534059b69e8bfce0e9f
https://github.com/qemu/qemu/commit/c10b4b3c0dcae2fe1836e534059b69e8bfce0e9f
Author: David Woodhouse <dwmw@amazon.co.uk>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/i386/pc.c
M hw/i386/pc_piix.c
M hw/i386/pc_q35.c
M hw/xen/xen-bus.c
M include/hw/i386/pc.h
M include/hw/xen/xen-bus.h
Log Message:
-----------
hw/i386/pc: support '-nic' for xen-net-device
The default NIC creation seems a bit hackish to me. I don't understand
why each platform has to call pci_nic_init_nofail() from a point in the
code where it actually has a pointer to the PCI bus, and then we have
the special cases for things like ne2k_isa.
If qmp_device_add() can *find* the appropriate bus and instantiate
the device on it, why can't we just do that from generic code for
creating the default NICs too?
But that isn't a yak I want to shave today. Add a xenbus field to the
PCMachineState so that it can make its way from pc_basic_device_init()
to pc_nic_init() and be handled as a special case like ne2k_isa is.
Now we can launch emulated Xen guests with '-nic user'.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Paul Durrant <paul@xen.org>
Commit: a73049953b7259a94d068c1b453a73b8905b1a6f
https://github.com/qemu/qemu/commit/a73049953b7259a94d068c1b453a73b8905b1a6f
Author: David Woodhouse <dwmw@amazon.co.uk>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/i386/xen/xen_platform.c
Log Message:
-----------
xen-platform: unplug AHCI disks
To support Xen guests using the Q35 chipset, the unplug protocol needs
to also remove AHCI disks.
Make pci_xen_ide_unplug() more generic, iterating over the children
of the PCI device and destroying the "ide-hd" devices. That works the
same for both AHCI and IDE, as does the detection of the primary disk
as unit 0 on the bus named "ide.0".
Then pci_xen_ide_unplug() can be used for both AHCI and IDE devices.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Paul Durrant <paul@xen.org>
Commit: cc9d10b9e89f0325c1a14955534d6b28ea586fba
https://github.com/qemu/qemu/commit/cc9d10b9e89f0325c1a14955534d6b28ea586fba
Author: David Woodhouse <dwmw@amazon.co.uk>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M MAINTAINERS
M docs/system/i386/xen.rst
M qemu-options.hx
Log Message:
-----------
docs: update Xen-on-KVM documentation
Add notes about console and network support, and how to launch PV guests.
Clean up the disk configuration examples now that that's simpler, and
remove the comment about IDE unplug on q35/AHCI now that it's fixed.
Update the -initrd option documentation to explain how to quote commas
in module command lines, and reference it when documenting PV guests.
Also update stale avocado test filename in MAINTAINERS.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Paul Durrant <paul@xen.org>
Commit: cca157568615465887a6f741d939865659a559ae
https://github.com/qemu/qemu/commit/cca157568615465887a6f741d939865659a559ae
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M Kconfig.host
M include/ui/qemu-pixman.h
M meson.build
M meson_options.txt
M scripts/meson-buildoptions.sh
Log Message:
-----------
build-sys: add a "pixman" feature
For now, pixman is mandatory, but we set config_host.h and Kconfig.
Once compilation is fixed, "pixman" will become actually optional.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Commit: ce59c54c4927d22e7d564f68f29c697d77ba9b86
https://github.com/qemu/qemu/commit/ce59c54c4927d22e7d564f68f29c697d77ba9b86
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M include/ui/qemu-pixman.h
Log Message:
-----------
build-sys: drop needless warning pragmas for old pixman
Since commit 236f282c1c7 ("configure: check for pixman-1 version"), QEMU
requires >= 0.21.8.
Suggested-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: b3ec48cf9241efd443caebb732587ac9cb33094b
https://github.com/qemu/qemu/commit/b3ec48cf9241efd443caebb732587ac9cb33094b
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M include/ui/qemu-pixman.h
M ui/qemu-pixman.c
Log Message:
-----------
ui: compile out some qemu-pixman functions when !PIXMAN
Those functions require the PIXMAN library.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 79a1f32559cbd1f2d8c6fc96c581fd460317a284
https://github.com/qemu/qemu/commit/79a1f32559cbd1f2d8c6fc96c581fd460317a284
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
A include/ui/pixman-minimal.h
M include/ui/qemu-pixman.h
Log Message:
-----------
ui: add pixman-minimal.h
This is a tiny subset of PIXMAN API that is used pervasively in QEMU
codebase to manage images and identify the underlying format.
It doesn't seems worth to wrap this in a QEMU-specific API.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Acked-by: Thomas Huth <thuth@redhat.com>
Commit: 6d9ed4eb9470db8fb7294baa83a73b854419bcc4
https://github.com/qemu/qemu/commit/6d9ed4eb9470db8fb7294baa83a73b854419bcc4
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M system/vl.c
Log Message:
-----------
vl: drop needless -spice checks
Since commit 5324e3e958e ("qemu-options: define -spice only #ifdef
CONFIG_SPICE"), it is unnecessary to check at runtime for "-spice"
option.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Commit: 6261164bd600422f1c557b5a1dea124a83181881
https://github.com/qemu/qemu/commit/6261164bd600422f1c557b5a1dea124a83181881
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M qemu-options.hx
M system/vl.c
M ui/vnc-stubs.c
Log Message:
-----------
qemu-options: define -vnc only #ifdef CONFIG_VNC
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Commit: 484629fc8141eaa257f961b5e5e310a1bbd0f1a2
https://github.com/qemu/qemu/commit/484629fc8141eaa257f961b5e5e310a1bbd0f1a2
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M system/vl.c
Log Message:
-----------
vl: simplify display_remote logic
Bump the display_remote variable when the -vnc option is parsed, just
like -spice.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Commit: 2aeaa4b2000d95139d5dfae8ca5061c1b19e749e
https://github.com/qemu/qemu/commit/2aeaa4b2000d95139d5dfae8ca5061c1b19e749e
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M system/vl.c
Log Message:
-----------
vl: move display early init before default devices
The next commit needs to have the display registered itself before
creating the default VCs.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Commit: 1bec1cc0da497e55c16e2a7b50f94cdb2a02197f
https://github.com/qemu/qemu/commit/1bec1cc0da497e55c16e2a7b50f94cdb2a02197f
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M include/ui/console.h
M system/vl.c
M ui/console.c
Log Message:
-----------
ui/console: allow to override the default VC
If a display is backed by a specialized VC, allow to override the
default "vc:80Cx24C".
As suggested by Paolo, if the display doesn't implement a VC (get_vc()
returns NULL), use a fallback that will use a muxed console on stdio.
This changes the behaviour of "qemu -display none", to create a muxed
serial/monitor by default (on TTY & not daemonized).
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Commit: 600179c39efb30cf072e18c7604ccf52360684c6
https://github.com/qemu/qemu/commit/600179c39efb30cf072e18c7604ccf52360684c6
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
A ui/console-vc-stubs.c
M ui/console.c
M ui/meson.build
Log Message:
-----------
ui/vc: console-vc requires PIXMAN
Add stubs for the fallback paths.
get_vc() now returns NULL by default if !PIXMAN.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Commit: f38aa2c7c0c85d8f978a3c23ab0a32578fc73134
https://github.com/qemu/qemu/commit/f38aa2c7c0c85d8f978a3c23ab0a32578fc73134
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hmp-commands.hx
M qapi/ui.json
M ui/ui-hmp-cmds.c
M ui/ui-qmp-cmds.c
Log Message:
-----------
qmp/hmp: disable screendump if PIXMAN is missing
The command requires color conversion and line-by-line feeding. We could
have a simple fallback for simple formats though.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Commit: a200d53b1fde2101ec624853139a52d2e4666208
https://github.com/qemu/qemu/commit/a200d53b1fde2101ec624853139a52d2e4666208
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/display/virtio-gpu.c
A include/ui/rect.h
Log Message:
-----------
virtio-gpu: replace PIXMAN for region/rect test
Use a simpler implementation for rectangle geometry & intersect, drop
the need for (more complex) PIXMAN functions.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Commit: d7e947965a064d762ece7873c1e695f399f76bd3
https://github.com/qemu/qemu/commit/d7e947965a064d762ece7873c1e695f399f76bd3
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M ui/console.c
Log Message:
-----------
ui/console: when PIXMAN is unavailable, don't draw placeholder msg
When we can't draw text, simply show a blank display.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Commit: 68fd167060e2b07741a03761264aa9495076a971
https://github.com/qemu/qemu/commit/68fd167060e2b07741a03761264aa9495076a971
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/display/vhost-user-gpu.c
Log Message:
-----------
vhost-user-gpu: skip VHOST_USER_GPU_UPDATE when !PIXMAN
This simply means that 2d drawing updates won't be handled, but 3d
should work.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 41e0bc3d5cde54571945e9515a469b65d0f39be9
https://github.com/qemu/qemu/commit/41e0bc3d5cde54571945e9515a469b65d0f39be9
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M ui/meson.build
Log Message:
-----------
ui/gl: opengl doesn't require PIXMAN
The QEMU fallback covers the requirements. We still need the flags of
header inclusion with CONFIG_PIXMAN.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Commit: 89fd3eab52f4dcdd7fcbb6e30a78ad0c7f8b6e80
https://github.com/qemu/qemu/commit/89fd3eab52f4dcdd7fcbb6e30a78ad0c7f8b6e80
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M meson.build
M ui/meson.build
Log Message:
-----------
ui/vnc: VNC requires PIXMAN
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Commit: c98791eb63517299d0c87fdd2823c3738d8c73cb
https://github.com/qemu/qemu/commit/c98791eb63517299d0c87fdd2823c3738d8c73cb
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/display/Kconfig
M meson.build
M ui/meson.build
Log Message:
-----------
ui/spice: SPICE/QXL requires PIXMAN
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Commit: da554e1616be52d3e3bbbda6044aff806c355fc0
https://github.com/qemu/qemu/commit/da554e1616be52d3e3bbbda6044aff806c355fc0
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M meson.build
Log Message:
-----------
ui/gtk: -display gtk requires PIXMAN
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Commit: 949c084ad62f99448ca4866e41f38f283e990298
https://github.com/qemu/qemu/commit/949c084ad62f99448ca4866e41f38f283e990298
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M ui/dbus-listener.c
M ui/meson.build
Log Message:
-----------
ui/dbus: do not require PIXMAN
Implement a fallback path for region 2D update.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Commit: 04c4cc10d9f127eef61ef9b3e4acb6333bc0f670
https://github.com/qemu/qemu/commit/04c4cc10d9f127eef61ef9b3e4acb6333bc0f670
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/arm/Kconfig
M hw/display/Kconfig
M hw/display/meson.build
Log Message:
-----------
arm/kconfig: XLNX_ZYNQMP_ARM depends on PIXMAN
The Display Port has some strong PIXMAN dependency.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: b271b6a392ba74858b04538cad14fa385c4894dc
https://github.com/qemu/qemu/commit/b271b6a392ba74858b04538cad14fa385c4894dc
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/arm/Kconfig
Log Message:
-----------
hw/arm: XLNX_VERSAL depends on XLNX_CSU_DMA
Fixes: 868d968004 ("hw/arm/xlnx-versal: Connect OSPI flash controller")
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: fa140b9562f0dc4665da0620b10d7ef1e3009078
https://github.com/qemu/qemu/commit/fa140b9562f0dc4665da0620b10d7ef1e3009078
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/display/sm501.c
Log Message:
-----------
hw/sm501: allow compiling without PIXMAN
Change the "x-pixman" property default value and use the fallback path
when PIXMAN support is disabled.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Commit: 376a0531d4f5ebe3e895986e0b2e1c15a9e4721c
https://github.com/qemu/qemu/commit/376a0531d4f5ebe3e895986e0b2e1c15a9e4721c
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/mips/Kconfig
Log Message:
-----------
hw/mips: FULOONG depends on VT82C686
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 699f15fd0c062c5f337584c585223bf7c3a9cd8e
https://github.com/qemu/qemu/commit/699f15fd0c062c5f337584c585223bf7c3a9cd8e
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M hw/display/ati.c
M hw/display/ati_2d.c
M hw/display/meson.build
Log Message:
-----------
hw/display/ati: allow compiling without PIXMAN
Change the "x-pixman" property default value and use the fallback path
when PIXMAN support is disabled.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Acked-by: BALATON Zoltan <balaton@eik.bme.hu>
Commit: d017f28a2ee082f472ed69fedf0435b468000e92
https://github.com/qemu/qemu/commit/d017f28a2ee082f472ed69fedf0435b468000e92
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M meson.build
Log Message:
-----------
build-sys: make pixman actually optional
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Commit: 3e34860a3a03f969ad0720ec9c12ea10e88738a6
https://github.com/qemu/qemu/commit/3e34860a3a03f969ad0720ec9c12ea10e88738a6
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M MAINTAINERS
M blockdev.c
M docs/system/i386/xen.rst
M hw/block/xen-block.c
M hw/char/trace-events
M hw/char/xen_console.c
M hw/i386/kvm/meson.build
M hw/i386/kvm/trace-events
M hw/i386/kvm/xen-stubs.c
M hw/i386/kvm/xen_evtchn.c
M hw/i386/kvm/xen_gnttab.c
A hw/i386/kvm/xen_primary_console.c
A hw/i386/kvm/xen_primary_console.h
M hw/i386/kvm/xen_xenstore.c
M hw/i386/pc.c
M hw/i386/pc_piix.c
M hw/i386/pc_q35.c
M hw/i386/xen/xen_platform.c
M hw/net/meson.build
M hw/net/trace-events
M hw/net/xen_nic.c
M hw/xen/xen-backend.c
M hw/xen/xen-bus.c
M hw/xen/xen-legacy-backend.c
M hw/xen/xen_devconfig.c
M hw/xenpv/xen_machine_pv.c
M include/hw/i386/pc.h
M include/hw/xen/interface/arch-arm.h
M include/hw/xen/interface/arch-x86/cpuid.h
M include/hw/xen/interface/arch-x86/xen-x86_32.h
M include/hw/xen/interface/arch-x86/xen-x86_64.h
M include/hw/xen/interface/arch-x86/xen.h
M include/hw/xen/interface/event_channel.h
M include/hw/xen/interface/features.h
M include/hw/xen/interface/grant_table.h
M include/hw/xen/interface/hvm/hvm_op.h
M include/hw/xen/interface/hvm/params.h
M include/hw/xen/interface/io/blkif.h
M include/hw/xen/interface/io/console.h
M include/hw/xen/interface/io/fbif.h
M include/hw/xen/interface/io/kbdif.h
M include/hw/xen/interface/io/netif.h
M include/hw/xen/interface/io/protocols.h
M include/hw/xen/interface/io/ring.h
M include/hw/xen/interface/io/usbif.h
M include/hw/xen/interface/io/xenbus.h
M include/hw/xen/interface/io/xs_wire.h
M include/hw/xen/interface/memory.h
M include/hw/xen/interface/physdev.h
M include/hw/xen/interface/sched.h
M include/hw/xen/interface/trace.h
M include/hw/xen/interface/vcpu.h
M include/hw/xen/interface/version.h
M include/hw/xen/interface/xen-compat.h
M include/hw/xen/interface/xen.h
M include/hw/xen/xen-backend.h
M include/hw/xen/xen-bus.h
M include/hw/xen/xen-legacy-backend.h
M qemu-options.hx
M target/i386/kvm/kvm.c
M target/i386/kvm/xen-emu.c
Log Message:
-----------
Merge tag 'pull-xenfv.for-upstream-20231107' of
git://git.infradead.org/users/dwmw2/qemu into staging
Xen PV guest support for 8.2
Add Xen PV console and network support, the former of which enables the
Xen "PV shim" to be used to support PV guests.
Also clean up the block support and make it work when the user passes
just 'drive file=IMAGE,if=xen' on the command line.
Update the documentation to reflect all of these, taking the opportunity
to simplify what it says about q35 by making unplug work for AHCI.
Ignore the VCPU_SSHOTTMR_future timer flag, and advertise the 'fixed'
per-vCPU upcall vector support, as newer upstream Xen do.
# -----BEGIN PGP SIGNATURE-----
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# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 07 Nov 2023 17:13:21 HKT
# gpg: using RSA key BE07D9FD54809AB2C4B0FF5F63762CDA67E2F359
# gpg: issuer "dwmw2@infradead.org"
# gpg: Good signature from "David Woodhouse <dwmw2@infradead.org>" [unknown]
# gpg: aka "David Woodhouse <dwmw2@exim.org>" [unknown]
# gpg: aka "David Woodhouse <david@woodhou.se>" [unknown]
# gpg: aka "David Woodhouse <dwmw2@kernel.org>" [unknown]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: BE07 D9FD 5480 9AB2 C4B0 FF5F 6376 2CDA 67E2 F359
* tag 'pull-xenfv.for-upstream-20231107' of
git://git.infradead.org/users/dwmw2/qemu:
docs: update Xen-on-KVM documentation
xen-platform: unplug AHCI disks
hw/i386/pc: support '-nic' for xen-net-device
hw/xen: update Xen PV NIC to XenDevice model
hw/xen: only remove peers of PCI NICs on unplug
hw/xen: add support for Xen primary console in emulated mode
hw/xen: update Xen console to XenDevice model
hw/xen: do not repeatedly try to create a failing backend device
hw/xen: add get_frontend_path() method to XenDeviceClass
hw/xen: automatically assign device index to block devices
hw/xen: populate store frontend nodes with XenStore PFN/port
i386/xen: advertise XEN_HVM_CPUID_UPCALL_VECTOR in CPUID
include: update Xen public headers to Xen 4.17.2 release
hw/xen: Clean up event channel 'type_val' handling to use union
i386/xen: Ignore VCPU_SSHOTTMR_future flag in set_singleshot_timer()
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 7eee58ae3bb15a2bceb368997ce1a48fd3c607e7
https://github.com/qemu/qemu/commit/7eee58ae3bb15a2bceb368997ce1a48fd3c607e7
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M qapi/ui.json
M ui/cocoa.m
M ui/gtk-egl.c
M ui/gtk.c
Log Message:
-----------
Merge tag 'ui-pull-request' of https://gitlab.com/marcandre.lureau/qemu into
staging
UI patch queue
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# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 07 Nov 2023 17:30:27 HKT
# gpg: using RSA key 87A9BD933F87C606D276F62DDAE8E10975969CE5
# gpg: issuer "marcandre.lureau@redhat.com"
# gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>"
[full]
# gpg: aka "Marc-André Lureau <marcandre.lureau@gmail.com>"
[full]
# Primary key fingerprint: 87A9 BD93 3F87 C606 D276 F62D DAE8 E109 7596 9CE5
* tag 'ui-pull-request' of https://gitlab.com/marcandre.lureau/qemu:
ui: Replacing pointer in function
ui/cocoa: add zoom-to-fit display option
ui/gtk-egl: apply scale factor when calculating window's dimension
ui/gtk-egl: Check EGLSurface before doing scanout
ui/gtk: force realization of drawing area
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: f6b615b52d1d92f02103596a30df95f31138a2e4
https://github.com/qemu/qemu/commit/f6b615b52d1d92f02103596a30df95f31138a2e4
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M MAINTAINERS
M docs/interop/vhost-user.rst
M docs/system/device-emulation.rst
A docs/system/devices/virtio-snd.rst
M hw/audio/Kconfig
M hw/audio/meson.build
M hw/audio/trace-events
A hw/audio/virtio-snd-pci.c
A hw/audio/virtio-snd.c
M hw/cxl/cxl-cdat.c
M hw/cxl/cxl-component-utils.c
M hw/cxl/cxl-device-utils.c
M hw/cxl/cxl-events.c
M hw/cxl/cxl-mailbox-utils.c
M hw/cxl/meson.build
A hw/cxl/switch-mailbox-cci.c
M hw/mem/cxl_type3.c
M hw/mem/cxl_type3_stubs.c
M hw/pci-bridge/cxl_downstream.c
M hw/pci-bridge/cxl_root_port.c
M hw/pci-bridge/cxl_upstream.c
M hw/virtio/vhost-user-fs.c
M hw/virtio/vhost-user.c
M hw/virtio/vhost.c
A include/hw/audio/virtio-snd.h
M include/hw/cxl/cxl.h
M include/hw/cxl/cxl_component.h
M include/hw/cxl/cxl_device.h
M include/hw/cxl/cxl_events.h
M include/hw/cxl/cxl_pci.h
A include/hw/pci-bridge/cxl_upstream_port.h
M include/hw/virtio/vhost-backend.h
M include/hw/virtio/vhost-user.h
M include/hw/virtio/vhost.h
M net/vhost-vdpa.c
M system/qdev-monitor.c
M tests/avocado/acpi-bits.py
A tests/data/acpi/q35/APIC.core-count
M tests/data/acpi/q35/APIC.core-count2
A tests/data/acpi/q35/APIC.thread-count
A tests/data/acpi/q35/APIC.thread-count2
A tests/data/acpi/q35/APIC.type4-count
A tests/data/acpi/q35/DSDT.core-count
M tests/data/acpi/q35/DSDT.core-count2
A tests/data/acpi/q35/DSDT.thread-count
A tests/data/acpi/q35/DSDT.thread-count2
A tests/data/acpi/q35/DSDT.type4-count
A tests/data/acpi/q35/FACP.core-count
A tests/data/acpi/q35/FACP.thread-count
A tests/data/acpi/q35/FACP.thread-count2
A tests/data/acpi/q35/FACP.type4-count
M tests/qtest/bios-tables-test.c
M tests/unit/test-smp-parse.c
Log Message:
-----------
Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu
into staging
virtio,pc,pci: features, fixes
virtio sound card support
vhost-user: back-end state migration
cxl:
line length reduction
enabling fabric management
vhost-vdpa:
shadow virtqueue hash calculation Support
shadow virtqueue RSS Support
tests:
CPU topology related smbios test cases
Fixes, cleanups all over the place
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 07 Nov 2023 18:06:50 HKT
# gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
# gpg: issuer "mst@redhat.com"
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full]
# gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full]
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67
# Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469
* tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (63
commits)
acpi/tests/avocado/bits: enable console logging from bits VM
acpi/tests/avocado/bits: enforce 32-bit SMBIOS entry point
hw/cxl: Add tunneled command support to mailbox for switch cci.
hw/cxl: Add dummy security state get
hw/cxl/type3: Cleanup multiple CXL_TYPE3() calls in read/write functions
hw/cxl/mbox: Add Get Background Operation Status Command
hw/cxl: Add support for device sanitation
hw/cxl/mbox: Wire up interrupts for background completion
hw/cxl/mbox: Add support for background operations
hw/cxl: Implement Physical Ports status retrieval
hw/pci-bridge/cxl_downstream: Set default link width and link speed
hw/cxl/mbox: Add Physical Switch Identify command.
hw/cxl/mbox: Add Information and Status / Identify command
hw/cxl: Add a switch mailbox CCI function
hw/pci-bridge/cxl_upstream: Move defintion of device to header.
hw/cxl/mbox: Generalize the CCI command processing
hw/cxl/mbox: Pull the CCI definition out of the CXLDeviceState
hw/cxl/mbox: Split mailbox command payload into separate input and output
hw/cxl/mbox: Pull the payload out of struct cxl_cmd and make instances
constant
hw/cxl: Fix a QEMU_BUILD_BUG_ON() in switch statement scope issue.
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 462ad017ed76889d46696a3581e1b52343f9b683
https://github.com/qemu/qemu/commit/462ad017ed76889d46696a3581e1b52343f9b683
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2023-11-07 (Tue, 07 Nov 2023)
Changed paths:
M Kconfig.host
M hmp-commands.hx
M hw/arm/Kconfig
M hw/display/Kconfig
M hw/display/ati.c
M hw/display/ati_2d.c
M hw/display/meson.build
M hw/display/sm501.c
M hw/display/vhost-user-gpu.c
M hw/display/virtio-gpu.c
M hw/mips/Kconfig
M include/ui/console.h
A include/ui/pixman-minimal.h
M include/ui/qemu-pixman.h
A include/ui/rect.h
M meson.build
M meson_options.txt
M qapi/ui.json
M qemu-options.hx
M scripts/meson-buildoptions.sh
M system/vl.c
A ui/console-vc-stubs.c
M ui/console.c
M ui/dbus-listener.c
M ui/meson.build
M ui/qemu-pixman.c
M ui/ui-hmp-cmds.c
M ui/ui-qmp-cmds.c
M ui/vnc-stubs.c
Log Message:
-----------
Merge tag 'pixman-pull-request' of https://gitlab.com/marcandre.lureau/qemu
into staging
Make Pixman an optional dependency
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# gpg: Signature made Tue 07 Nov 2023 18:14:49 HKT
# gpg: using RSA key 87A9BD933F87C606D276F62DDAE8E10975969CE5
# gpg: issuer "marcandre.lureau@redhat.com"
# gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>"
[full]
# gpg: aka "Marc-André Lureau <marcandre.lureau@gmail.com>"
[full]
# Primary key fingerprint: 87A9 BD93 3F87 C606 D276 F62D DAE8 E109 7596 9CE5
* tag 'pixman-pull-request' of https://gitlab.com/marcandre.lureau/qemu: (25
commits)
build-sys: make pixman actually optional
hw/display/ati: allow compiling without PIXMAN
hw/mips: FULOONG depends on VT82C686
hw/sm501: allow compiling without PIXMAN
hw/arm: XLNX_VERSAL depends on XLNX_CSU_DMA
arm/kconfig: XLNX_ZYNQMP_ARM depends on PIXMAN
ui/dbus: do not require PIXMAN
ui/gtk: -display gtk requires PIXMAN
ui/spice: SPICE/QXL requires PIXMAN
ui/vnc: VNC requires PIXMAN
ui/gl: opengl doesn't require PIXMAN
vhost-user-gpu: skip VHOST_USER_GPU_UPDATE when !PIXMAN
ui/console: when PIXMAN is unavailable, don't draw placeholder msg
virtio-gpu: replace PIXMAN for region/rect test
qmp/hmp: disable screendump if PIXMAN is missing
ui/vc: console-vc requires PIXMAN
ui/console: allow to override the default VC
vl: move display early init before default devices
vl: simplify display_remote logic
qemu-options: define -vnc only #ifdef CONFIG_VNC
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Compare: https://github.com/qemu/qemu/compare/bb541a7068d2...462ad017ed76
- [Qemu-commits] [qemu/qemu] 565f85: ui/gtk: force realization of drawing area,
Alex Bennée <=