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[Qemu-commits] [qemu/qemu] 7fb7c9: target/hppa: Fix BE, L set of sr0
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 7fb7c9: target/hppa: Fix BE, L set of sr0 |
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Date: |
Sun, 31 Mar 2024 08:48:41 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 7fb7c9da347731956da4a4b937c721e233482df7
https://github.com/qemu/qemu/commit/7fb7c9da347731956da4a4b937c721e233482df7
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-03-27 (Wed, 27 Mar 2024)
Changed paths:
M target/hppa/translate.c
Log Message:
-----------
target/hppa: Fix BE,L set of sr0
The return address comes from IA*Q_Next, and IASQ_Next
is always equal to IASQ_Back, not IASQ_Front.
Tested-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 2f48ba7b94e41241e5cd19af7b37948559272734
https://github.com/qemu/qemu/commit/2f48ba7b94e41241e5cd19af7b37948559272734
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-03-27 (Wed, 27 Mar 2024)
Changed paths:
M target/hppa/translate.c
Log Message:
-----------
target/hppa: Fix B,GATE for wide mode
Do not clobber the high bits of the address by using a 32-bit deposit.
Reviewed-by: Helge Deller <deller@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 578b8132b2666f7168b16422ac566684918a371e
https://github.com/qemu/qemu/commit/578b8132b2666f7168b16422ac566684918a371e
Author: Sven Schnelle <svens@stackframe.org>
Date: 2024-03-27 (Wed, 27 Mar 2024)
Changed paths:
M target/hppa/translate.c
Log Message:
-----------
target/hppa: Handle unit conditions for wide mode
Wide mode provides two more conditions, add them.
Fixes: 59963d8fdf42 ("target/hppa: Pass d to do_unit_cond")
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240321184228.611897-1-svens@stackframe.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: bd1ad92ccfa48c44f001ebea17633ef61ff62642
https://github.com/qemu/qemu/commit/bd1ad92ccfa48c44f001ebea17633ef61ff62642
Author: Sven Schnelle <svens@stackframe.org>
Date: 2024-03-27 (Wed, 27 Mar 2024)
Changed paths:
M target/hppa/translate.c
Log Message:
-----------
target/hppa: Fix ADD/SUB trap on overflow for narrow mode
Fixes: c53e401ed9ff ("target/hppa: Remove TARGET_REGISTER_BITS")
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240321184228.611897-2-svens@stackframe.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 104281c10ea6386f40d919e994443a014869b292
https://github.com/qemu/qemu/commit/104281c10ea6386f40d919e994443a014869b292
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-03-27 (Wed, 27 Mar 2024)
Changed paths:
M target/hppa/translate.c
Log Message:
-----------
target/hppa: Mark interval timer write as io
Reviewed-by: Helge Deller <deller@gmx.de>
Tested-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 0c58c1bc1c1c055e39904517b6b83dba82b2651d
https://github.com/qemu/qemu/commit/0c58c1bc1c1c055e39904517b6b83dba82b2651d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-03-27 (Wed, 27 Mar 2024)
Changed paths:
M target/hppa/translate.c
Log Message:
-----------
target/hppa: Tidy read of interval timer
The call to gen_helper_read_interval_timer is
identical on both sides of the IF.
Reviewed-by: Helge Deller <deller@gmx.de>
Tested-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 6ebebea758998b4da6472aad5eecc641c3b8c6dc
https://github.com/qemu/qemu/commit/6ebebea758998b4da6472aad5eecc641c3b8c6dc
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-03-27 (Wed, 27 Mar 2024)
Changed paths:
M target/hppa/helper.h
M target/hppa/int_helper.c
M target/hppa/translate.c
Log Message:
-----------
target/hppa: Fix EIRR, EIEM versus icount
Call translator_io_start before write to EIRR.
Move evaluation of EIRR vs EIEM to hppa_cpu_exec_interrupt.
Exit TB after write to EIEM, but otherwise use a straight store.
Reviewed-by: Helge Deller <deller@gmx.de>
Tested-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 7d50b696601deecfcefcfb2d8ba9eaf98cb294b6
https://github.com/qemu/qemu/commit/7d50b696601deecfcefcfb2d8ba9eaf98cb294b6
Author: Sven Schnelle <svens@stackframe.org>
Date: 2024-03-27 (Wed, 27 Mar 2024)
Changed paths:
M target/hppa/cpu.h
M target/hppa/translate.c
Log Message:
-----------
target/hppa: Use gva_offset_mask() everywhere
Move it to cpu.h, so it can also be used in hppa_form_gva_psw().
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-by: Helge Deller <deller@gmx.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240324080945.991100-2-svens@stackframe.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: d0ae87a27c212b4dda1b5e83507f5ebdfd019097
https://github.com/qemu/qemu/commit/d0ae87a27c212b4dda1b5e83507f5ebdfd019097
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-03-27 (Wed, 27 Mar 2024)
Changed paths:
M target/hppa/translate.c
Log Message:
-----------
target/hppa: Fix DCOR reconstruction of carry bits
The carry bits for each nibble N are located in bit (N+1)*4,
so the shift by 3 was off by one. Furthermore, the carry bit
for the most significant carry bit is indeed located in bit 64,
which is located in a different storage word.
Use a double-word shift-right to reassemble into a single word
and place them all at bit 0 of their respective nibbles.
Tested-by: Helge Deller <deller@gmx.de>
Reviewed-by: Helge Deller <deller@gmx.de>
Fixes: b2167459ae4 ("target-hppa: Implement basic arithmetic")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: ababac165b375b617e5b333536b846a33c48006e
https://github.com/qemu/qemu/commit/ababac165b375b617e5b333536b846a33c48006e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-03-27 (Wed, 27 Mar 2024)
Changed paths:
M target/hppa/translate.c
Log Message:
-----------
target/hppa: Optimize UADDCM with no condition
With r1 as zero is by far the most common usage of UADDCM, as the
easiest way to invert a register. The compiler does occasionally
use the addition step as well, and we can simplify that to avoid
a temp and write directly into the destination.
Tested-by: Helge Deller <deller@gmx.de>
Reviewed-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 46bb3d467cbb5227db6d70d1835a0852cd3eafd2
https://github.com/qemu/qemu/commit/46bb3d467cbb5227db6d70d1835a0852cd3eafd2
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-03-27 (Wed, 27 Mar 2024)
Changed paths:
M target/hppa/translate.c
Log Message:
-----------
target/hppa: Fix unit carry conditions
Split do_unit_cond to do_unit_zero_cond to only handle conditions
versus zero. These are the only ones that are legal for UXOR.
Simplify trans_uxor accordingly.
Rename do_unit to do_unit_addsub, since xor has been split.
Properly compute carry-out bits for add and subtract, mirroring
the code in do_add and do_sub.
Tested-by: Helge Deller <deller@gmx.de>
Reviewed-by: Helge Deller <deller@gmx.de>
Fixes: b2167459ae4 ("target-hppa: Implement basic arithmetic")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 82d0c831ceff6ae03c4ccc865999a7231972df2e
https://github.com/qemu/qemu/commit/82d0c831ceff6ae03c4ccc865999a7231972df2e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-03-27 (Wed, 27 Mar 2024)
Changed paths:
M target/hppa/insns.decode
M target/hppa/translate.c
Log Message:
-----------
target/hppa: Squash d for pa1.x during decode
The cond_need_ext predicate was created while we still had a
32-bit compilation mode. It now makes more sense to treat D
as an absolute indicator of a 64-bit operation.
Tested-by: Helge Deller <deller@gmx.de>
Reviewed-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: fe2d066a9e3dc3d902ef7d3860c077563146b35b
https://github.com/qemu/qemu/commit/fe2d066a9e3dc3d902ef7d3860c077563146b35b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-03-27 (Wed, 27 Mar 2024)
Changed paths:
M target/hppa/translate.c
Log Message:
-----------
target/hppa: Replace c with uv in do_cond
Prepare for proper indication of shladd unsigned overflow.
The UV indicator will be zero/not-zero instead of a single bit.
Tested-by: Helge Deller <deller@gmx.de>
Reviewed-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: f8f5986edc542444a318e8783dfe2bad912669fe
https://github.com/qemu/qemu/commit/f8f5986edc542444a318e8783dfe2bad912669fe
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-03-27 (Wed, 27 Mar 2024)
Changed paths:
M target/hppa/translate.c
Log Message:
-----------
target/hppa: Fix overflow computation for shladd
Overflow indicator should include the effect of the shift step.
We had previously left ??? comments about the issue.
Tested-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 981eb1060336ee0e371369088c55f81f5a577ce8
https://github.com/qemu/qemu/commit/981eb1060336ee0e371369088c55f81f5a577ce8
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-03-28 (Thu, 28 Mar 2024)
Changed paths:
M tests/qtest/virtio-9p-test.c
Log Message:
-----------
qtest/virtio-9p-test.c: create/remove temp dirs after each test
The local 9p driver in virtio-9p-test.c its temporary dir right at the
start of qos-test (via virtio_9p_create_local_test_dir()) and only
deletes it after qos-test is finished (via
virtio_9p_remove_local_test_dir()).
This means that any qos-test machine that ends up running virtio-9p-test
local tests more than once will end up re-using the same temp dir. This
is what's happening in [1] after we introduced the riscv machine nodes:
if we enable slow tests with the '-m slow' flag using
qemu-system-riscv64, this is what happens:
- a temp dir is created;
- virtio-9p-device tests will run virtio-9p-test successfully;
- virtio-9p-pci tests will run virtio-9p-test, and fail right at the
first slow test at fs_create_dir() because the "01" file was already
created by fs_create_dir() test when running with the virtio-9p-device.
The root cause is that we're creating a single temporary dir, via the
construct/destruct callbacks, and this temp dir is kept for the entire
qos-test run.
We can change each test to clean after themselves. This approach would
make the 'create' tests obsolete since we would need to create and
delete dirs/files/symlinks for the cleanup, turning them into the
'unlinkat' tests that comes right after.
We chose a different approach that handles the root cause: do not use
constructor/destructor to create the temp dir. Create one temp dir for
each test, and remove it after the test is complete. This is the
approach taken for other qtests like vhost-user-test.c where each test
requires a setup() and a subsequent cleanup(), all of those instantiated
in the .before callback.
[1] https://mail.gnu.org/archive/html/qemu-devel/2024-03/msg05807.html
Reported-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20240327142011.805728-2-dbarboza@ventanamicro.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Tested-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Commit: dcae75fba1084823d0fc87caa13f0ba6f32155f3
https://github.com/qemu/qemu/commit/dcae75fba1084823d0fc87caa13f0ba6f32155f3
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-03-28 (Thu, 28 Mar 2024)
Changed paths:
M tests/qtest/virtio-9p-test.c
Log Message:
-----------
qtest/virtio-9p-test.c: remove g_test_slow() gate
Commit 558f5c42ef gated the local tests with g_test_slow() to skip them
in 'make check'. The reported issue back then was this following CI
problem:
https://lists.nongnu.org/archive/html/qemu-devel/2020-11/msg05510.html
This problem ended up being fixed after it was detected with the
recently added risc-v machine nodes [1]. virtio-9p-test.c is now
creating and removing temporary dirs for each test run, instead of
creating a single dir for the entire qos-test scope.
We're now able to run these tests with 'make check' in the CI, so let's
go ahead and re-enable them.
This reverts commit 558f5c42efded3e0d0b20a90bce2a9a14580d824.
[1] https://mail.gnu.org/archive/html/qemu-devel/2024-03/msg05807.html
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20240327142011.805728-3-dbarboza@ventanamicro.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Tested-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Commit: 558c09bef87cfa891f0eb12651208cb46212815d
https://github.com/qemu/qemu/commit/558c09bef87cfa891f0eb12651208cb46212815d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-03-29 (Fri, 29 Mar 2024)
Changed paths:
M target/hppa/helper.h
M target/hppa/sys_helper.c
M target/hppa/translate.c
Log Message:
-----------
target/hppa: Generate getshadowregs inline
This operation is trivial and does not require a helper.
Reviewed-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 381931275a9e09fb832bd6be0b41ebd6ce415099
https://github.com/qemu/qemu/commit/381931275a9e09fb832bd6be0b41ebd6ce415099
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-03-29 (Fri, 29 Mar 2024)
Changed paths:
M target/hppa/insns.decode
M target/hppa/translate.c
Log Message:
-----------
target/hppa: Move diag argument handling to decodetree
Split trans_diag into per-operation functions.
Reviewed-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 3bdf20819e6824b75a498332961abe7fd25ed671
https://github.com/qemu/qemu/commit/3bdf20819e6824b75a498332961abe7fd25ed671
Author: Helge Deller <deller@kernel.org>
Date: 2024-03-29 (Fri, 29 Mar 2024)
Changed paths:
M target/hppa/insns.decode
M target/hppa/translate.c
Log Message:
-----------
target/hppa: Add diag instructions to set/restore shadow registers
The 32-bit PA-7300LC (PCX-L2) CPU and the 64-bit PA8700 (PCX-W2) CPU
use different diag instructions to save or restore the CPU registers
to/from the shadow registers.
Implement those per-CPU architecture diag instructions to fix those
parts of the HP ODE testcases (L2DIAG and WDIAG, section 1) which test
the shadow registers.
Signed-off-by: Helge Deller <deller@gmx.de>
[rth: Use decodetree to distinguish cases]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Helge Deller <deller@gmx.de>
Tested-by: Helge Deller <deller@gmx.de>
Commit: 4a3aa11e1fb25c28c24a43fd2835c429b00a463d
https://github.com/qemu/qemu/commit/4a3aa11e1fb25c28c24a43fd2835c429b00a463d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-03-29 (Fri, 29 Mar 2024)
Changed paths:
M target/hppa/translate.c
Log Message:
-----------
target/hppa: Clear psw_n for BE on use_nullify_skip path
Along this path we have already skipped the insn to be
nullified, so the subsequent insn should be executed.
Cc: qemu-stable@nongnu.org
Reported-by: Sven Schnelle <svens@stackframe.org>
Tested-by: Sven Schnelle <svens@stackframe.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 58cb91b34d9b1e87353c4a21ff39062dd8b25dd5
https://github.com/qemu/qemu/commit/58cb91b34d9b1e87353c4a21ff39062dd8b25dd5
Author: Harsh Prateek Bora <harshpb@linux.ibm.com>
Date: 2024-03-30 (Sat, 30 Mar 2024)
Changed paths:
M hw/ppc/spapr_nested.c
Log Message:
-----------
spapr: nested: use bitwise NOT operator for flags check
Check for flag bit in H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE need to use
bitwise NOT operator to ensure no other flag bits are set.
Resolves: Coverity CID 1540008
Resolves: Coverity CID 1540009
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: beb0b62c3e0f7e486eac680f41b140f4ed492f59
https://github.com/qemu/qemu/commit/beb0b62c3e0f7e486eac680f41b140f4ed492f59
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-03-30 (Sat, 30 Mar 2024)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
hw/ppc/spapr: Include missing 'sysemu/tcg.h' header
"sysemu/tcg.h" declares tcg_enabled(), and is implicitly included.
Include it explicitly to avoid the following error when refactoring
headers:
hw/ppc/spapr.c:2612:9: error: call to undeclared function 'tcg_enabled'; ISO
C99 and later do not support implicit function declarations
[-Wimplicit-function-declaration]
if (tcg_enabled()) {
^
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: d7d9c6071e6dc5d466b229457fc4ad34e101dccd
https://github.com/qemu/qemu/commit/d7d9c6071e6dc5d466b229457fc4ad34e101dccd
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-03-30 (Sat, 30 Mar 2024)
Changed paths:
M target/ppc/mmu-radix64.c
Log Message:
-----------
target/ppc/mmu-radix64: Use correct string format in walk_tree()
'mask', 'nlb' and 'base_addr' are all uin64_t types.
Use the corresponding PRIx64 format.
Fixes: d2066bc50d ("target/ppc: Check page dir/table base alignment")
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 978897a572e975faad912a473815a668a43d9f1f
https://github.com/qemu/qemu/commit/978897a572e975faad912a473815a668a43d9f1f
Author: Benjamin Gray <bgray@linux.ibm.com>
Date: 2024-03-30 (Sat, 30 Mar 2024)
Changed paths:
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: Restore [H]DEXCR to 64-bits
The DEXCR emulation was recently changed to a 32-bit register, possibly
because it does have a 32-bit read-only view. It is a full 64-bit
SPR though, so use the corresponding 64-bit write functions.
Fixes: fbda88f7abdee ("target/ppc: Fix width of some 32-bit SPRs")
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Benjamin Gray <bgray@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: ed399ade3c85adf82fe507339560693e83a27020
https://github.com/qemu/qemu/commit/ed399ade3c85adf82fe507339560693e83a27020
Author: Benjamin Gray <bgray@linux.ibm.com>
Date: 2024-03-30 (Sat, 30 Mar 2024)
Changed paths:
M target/ppc/gdbstub.c
Log Message:
-----------
target/ppc: Fix GDB register indexing on secondary CPUs
The GDB server protocol assigns an arbitrary numbering of the SPRs.
We track this correspondence on each SPR with gdb_id, using it to
resolve any SPR requests GDB makes.
Early on we generate an XML representation of the SPRs to give GDB,
including this numbering. However the XML is cached globally, and we
skip setting the SPR gdb_id values on subsequent threads if we detect
it is cached. This causes QEMU to fail to resolve SPR requests against
secondary CPUs because it cannot find the matching gdb_id value on that
thread's SPRs.
This is a minimal fix to first assign the gdb_id values, then return
early if the XML is cached. Otherwise we generate the XML using the
now already initialised gdb_id values.
Fixes: 1b53948ff8f7 ("target/ppc: Use GDBFeature for dynamic XML")
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Benjamin Gray <bgray@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 434531619fecd5ff9a08e548ed87b2b73c29cf3e
https://github.com/qemu/qemu/commit/434531619fecd5ff9a08e548ed87b2b73c29cf3e
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-03-30 (Sat, 30 Mar 2024)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Do not clear MSR[ME] on MCE interrupts to supervisor
Hardware clears the MSR[ME] bit when delivering a machine check
interrupt, so that is what QEMU does.
The spapr environment runs in supervisor mode though, and receives
machine check interrupts after they are processed by the hypervisor,
and MSR[ME] must always be enabled in supervisor mode (otherwise it
could checkstop the system). So MSR[ME] must not be cleared when
delivering machine checks to the supervisor.
The fix to prevent supervisor mode from modifying MSR[ME] also
prevented it from re-enabling the incorrectly cleared MSR[ME] bit
when returning from handling the interrupt. Before that fix, the
problem was not very noticable with well-behaved code. So the
Fixes tag is not strictly correct, but practically they go together.
Found by kvm-unit-tests machine check tests (not yet upstream).
Fixes: 678b6f1af75ef ("target/ppc: Prevent supervisor from modifying MSR[ME]")
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: 74eb04af186457517b6bae8ec6ceac872bde822e
https://github.com/qemu/qemu/commit/74eb04af186457517b6bae8ec6ceac872bde822e
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-03-30 (Sat, 30 Mar 2024)
Changed paths:
M tests/avocado/ppc_hv_tests.py
Log Message:
-----------
tests/avocado: Fix ppc_hv_tests.py xorriso dependency guard
For some reason the skipIf missing_deps() check fails to skip the test
if it comes after the skipUnless lines, causing an error running on
systems without xorriso.
Avocado implements skipUnless is just an inverted skipIf, so it's not
clear what the bug is or why this fixes it. For now it's enough to
get things working.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2246
Fixes: c9cb496710758 ("tests/avocado: ppc add hypervisor tests")
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: b07a5bb736ca08d55cc3ada8ca309943b55d4b70
https://github.com/qemu/qemu/commit/b07a5bb736ca08d55cc3ada8ca309943b55d4b70
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2024-03-30 (Sat, 30 Mar 2024)
Changed paths:
M tests/avocado/ppc_hv_tests.py
Log Message:
-----------
tests/avocado: ppc_hv_tests.py set alpine time before setup-alpine
If the time is wrong, setup-alpine SSL certificate checks can fail.
setup-alpine is used to bring up the network, but it doesn't seem
to to set NTP time before the failing SSL checks. This test has
recently started failing presumably because the default time has
now fallen too far behind.
Fix this by setting time from the host time before running setup-alpine.
Fixes: c9cb496710758 ("tests/avocado: ppc add hypervisor tests")
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Commit: c919bc65c54433420eecf8dc918ed6bcfeab40bf
https://github.com/qemu/qemu/commit/c919bc65c54433420eecf8dc918ed6bcfeab40bf
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-03-31 (Sun, 31 Mar 2024)
Changed paths:
M target/hppa/cpu.h
M target/hppa/helper.h
M target/hppa/insns.decode
M target/hppa/int_helper.c
M target/hppa/sys_helper.c
M target/hppa/translate.c
Log Message:
-----------
Merge tag 'pull-pa-20240329' of https://gitlab.com/rth7680/qemu into staging
target/hppa: Fix BE,L set of sr0
target/hppa: Fix B,GATE for wide mode
target/hppa: Mark interval timer write as io
target/hppa: Fix EIRR, EIEM versus icount
target/hppa: Fix DCOR reconstruction of carry bits
target/hppa: Fix unit carry conditions
target/hppa: Fix overflow computation for shladd
target/hppa: Add diag instructions to set/restore shadow registers
target/hppa: Clear psw_n for BE on use_nullify_skip path
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# gpg: Signature made Fri 29 Mar 2024 22:30:09 GMT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-pa-20240329' of https://gitlab.com/rth7680/qemu:
target/hppa: Clear psw_n for BE on use_nullify_skip path
target/hppa: Add diag instructions to set/restore shadow registers
target/hppa: Move diag argument handling to decodetree
target/hppa: Generate getshadowregs inline
target/hppa: Fix overflow computation for shladd
target/hppa: Replace c with uv in do_cond
target/hppa: Squash d for pa1.x during decode
target/hppa: Fix unit carry conditions
target/hppa: Optimize UADDCM with no condition
target/hppa: Fix DCOR reconstruction of carry bits
target/hppa: Use gva_offset_mask() everywhere
target/hppa: Fix EIRR, EIEM versus icount
target/hppa: Tidy read of interval timer
target/hppa: Mark interval timer write as io
target/hppa: Fix ADD/SUB trap on overflow for narrow mode
target/hppa: Handle unit conditions for wide mode
target/hppa: Fix B,GATE for wide mode
target/hppa: Fix BE,L set of sr0
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: fa967115cbee0ec89f53b2d96bd3e6e16365eb1e
https://github.com/qemu/qemu/commit/fa967115cbee0ec89f53b2d96bd3e6e16365eb1e
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-03-31 (Sun, 31 Mar 2024)
Changed paths:
M tests/qtest/virtio-9p-test.c
Log Message:
-----------
Merge tag 'pull-9p-20240329' of https://github.com/cschoenebeck/qemu into
staging
Changes for 9p tests only:
* Fix 9p tests for riscv.
* Re-enable 9p 'local' tests for running in CI pipelines.
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# gpg: Signature made Fri 29 Mar 2024 08:46:18 GMT
# gpg: using RSA key 96D8D110CF7AF8084F88590134C2B58765A47395
# gpg: issuer "qemu_oss@crudebyte.com"
# gpg: Good signature from "Christian Schoenebeck <qemu_oss@crudebyte.com>"
[unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: ECAB 1A45 4014 1413 BA38 4926 30DB 47C3 A012 D5F4
# Subkey fingerprint: 96D8 D110 CF7A F808 4F88 5901 34C2 B587 65A4 7395
* tag 'pull-9p-20240329' of https://github.com/cschoenebeck/qemu:
qtest/virtio-9p-test.c: remove g_test_slow() gate
qtest/virtio-9p-test.c: create/remove temp dirs after each test
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7901c12bd77e2da20b3a93e7012f998ce5379402
https://github.com/qemu/qemu/commit/7901c12bd77e2da20b3a93e7012f998ce5379402
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-03-31 (Sun, 31 Mar 2024)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_nested.c
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/gdbstub.c
M target/ppc/mmu-radix64.c
M tests/avocado/ppc_hv_tests.py
Log Message:
-----------
Merge tag 'pull-ppc-for-9.0-3-20240331' of https://gitlab.com/npiggin/qemu
into staging
Various fixes for recent regressions and new code.
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# gpg: Signature made Sun 31 Mar 2024 08:30:11 BST
# gpg: using RSA key 4E437DDA56616F4329B0A79567B30276A8621CAE
# gpg: Good signature from "Nicholas Piggin <npiggin@gmail.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 4E43 7DDA 5661 6F43 29B0 A795 67B3 0276 A862 1CAE
* tag 'pull-ppc-for-9.0-3-20240331' of https://gitlab.com/npiggin/qemu:
tests/avocado: ppc_hv_tests.py set alpine time before setup-alpine
tests/avocado: Fix ppc_hv_tests.py xorriso dependency guard
target/ppc: Do not clear MSR[ME] on MCE interrupts to supervisor
target/ppc: Fix GDB register indexing on secondary CPUs
target/ppc: Restore [H]DEXCR to 64-bits
target/ppc/mmu-radix64: Use correct string format in walk_tree()
hw/ppc/spapr: Include missing 'sysemu/tcg.h' header
spapr: nested: use bitwise NOT operator for flags check
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/b9dbf6f9bf53...7901c12bd77e
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- [Qemu-commits] [qemu/qemu] 7fb7c9: target/hppa: Fix BE, L set of sr0,
Peter Maydell <=