[Qemu-commits] [qemu/qemu] e25fe8: tcg/optimize: Do not attempt to const

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[Qemu-commits] [qemu/qemu] e25fe8: tcg/optimize: Do not attempt to const

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] e25fe8: tcg/optimize: Do not attempt to constant fold neg_vec
Date:	Tue, 09 Apr 2024 14:35:30 -0700
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: e25fe886b89a396bae5847520b70c148587d490a
      
https://github.com/qemu/qemu/commit/e25fe886b89a396bae5847520b70c148587d490a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-04-09 (Tue, 09 Apr 2024)

  Changed paths:
    M tcg/optimize.c
    M tests/tcg/aarch64/Makefile.target
    A tests/tcg/aarch64/test-2150.c

  Log Message:
  -----------
  tcg/optimize: Do not attempt to constant fold neg_vec

Split out the tail of fold_neg to fold_neg_no_const so that we
can avoid attempting to constant fold vector negate.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2150
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: f0907ff4cae743f1a4ef3d0a55a047029eed06ff
      
https://github.com/qemu/qemu/commit/f0907ff4cae743f1a4ef3d0a55a047029eed06ff
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-04-09 (Tue, 09 Apr 2024)

  Changed paths:
    M linux-user/syscall.c

  Log Message:
  -----------
  linux-user: Fix waitid return of siginfo_t and rusage

The copy back to siginfo_t should be conditional only on arg3,
not the specific values that might have been written.
The copy back to rusage was missing entirely.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2262
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Alex Fan <alex.fan.q@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>


  Commit: 2ee80bce4f7cf2ef78f996ea608755d4e97c94de
      
https://github.com/qemu/qemu/commit/2ee80bce4f7cf2ef78f996ea608755d4e97c94de
  Author: Nguyen Dinh Phi <phind.uet@gmail.com>
  Date:   2024-04-09 (Tue, 09 Apr 2024)

  Changed paths:
    M linux-user/main.c

  Log Message:
  -----------
  linux-user: replace calloc() with g_new0()

Use glib allocation as recommended by the coding convention

Signed-off-by: Nguyen Dinh Phi <phind.uet@gmail.com>
Message-Id: <20240317171747.1642207-1-phind.uet@gmail.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 26d937237f363297e5f70efcb001b15b1cb0fc2b
      
https://github.com/qemu/qemu/commit/26d937237f363297e5f70efcb001b15b1cb0fc2b
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-04-09 (Tue, 09 Apr 2024)

  Changed paths:
    M target/hppa/int_helper.c
    M target/hppa/sys_helper.c

  Log Message:
  -----------
  target/hppa: Fix IIAOQ, IIASQ for pa2.0

The contents of IIAOQ depend on PSW_W.
Follow the text in "Interruption Instruction Address Queues",
pages 2-13 through 2-15.

Tested-by: Sven Schnelle <svens@stackframe.org>
Tested-by: Helge Deller <deller@gmx.de>
Reported-by: Sven Schnelle <svens@stackframe.org>
Fixes: b10700d826c ("target/hppa: Update IIAOQ, IIASQ for pa2.0")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: b0f2f2976b4db05351117b0440b32bf0aac2c5c6
      
https://github.com/qemu/qemu/commit/b0f2f2976b4db05351117b0440b32bf0aac2c5c6
  Author: Zack Buhman <zack@buhman.org>
  Date:   2024-04-09 (Tue, 09 Apr 2024)

  Changed paths:
    M target/sh4/translate.c

  Log Message:
  -----------
  target/sh4: mac.w: memory accesses are 16-bit words

Before this change, executing a code sequence such as:

           mova   tblm,r0
           mov    r0,r1
           mova   tbln,r0
           clrs
           clrmac
           mac.w  @r0+,@r1+
           mac.w  @r0+,@r1+

           .align 4
  tblm:    .word  0x1234
           .word  0x5678
  tbln:    .word  0x9abc
           .word  0xdefg

Does not result in correct behavior:

Expected behavior:
  first macw : macl = 0x1234 * 0x9abc + 0x0
               mach = 0x0

  second macw: macl = 0x5678 * 0xdefg + 0xb00a630
               mach = 0x0

Observed behavior (qemu-sh4eb, prior to this commit):

  first macw : macl = 0x5678 * 0xdefg + 0x0
               mach = 0x0

  second macw: (unaligned longword memory access, SIGBUS)

Various SH-4 ISA manuals also confirm that `mac.w` is a 16-bit word memory
access, not a 32-bit longword memory access.

Signed-off-by: Zack Buhman <zack@buhman.org>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20240402093756.27466-1-zack@buhman.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 7d95db5e78a24d3315e3112d26909a7262355cb7
      
https://github.com/qemu/qemu/commit/7d95db5e78a24d3315e3112d26909a7262355cb7
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-04-09 (Tue, 09 Apr 2024)

  Changed paths:
    M target/sh4/cpu.h

  Log Message:
  -----------
  target/sh4: Merge mach and macl into a union

Allow host access to the entire 64-bit accumulator.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c97e8977dcacb3fa8362ee28bcee75ceb01fceaa
      
https://github.com/qemu/qemu/commit/c97e8977dcacb3fa8362ee28bcee75ceb01fceaa
  Author: Zack Buhman <zack@buhman.org>
  Date:   2024-04-09 (Tue, 09 Apr 2024)

  Changed paths:
    M target/sh4/helper.h
    M target/sh4/op_helper.c
    M tests/tcg/sh4/Makefile.target
    A tests/tcg/sh4/test-macl.c

  Log Message:
  -----------
  target/sh4: Fix mac.l with saturation enabled

The saturation arithmetic logic in helper_macl is not correct.
I tested and verified this behavior on a SH7091.

Signed-off-by: Zack Buhman <zack@buhman.org>
Message-Id: <20240404162641.27528-2-zack@buhman.org>
[rth: Reformat helper_macl, add a test case.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>


  Commit: 7227c0cd506eaab5b1d89d15832cac7e05ecb412
      
https://github.com/qemu/qemu/commit/7227c0cd506eaab5b1d89d15832cac7e05ecb412
  Author: Zack Buhman <zack@buhman.org>
  Date:   2024-04-09 (Tue, 09 Apr 2024)

  Changed paths:
    M target/sh4/helper.h
    M target/sh4/op_helper.c
    M tests/tcg/sh4/Makefile.target
    A tests/tcg/sh4/test-macw.c

  Log Message:
  -----------
  target/sh4: Fix mac.w with saturation enabled

The saturation arithmetic logic in helper_macw is not correct.
I tested and verified this behavior on a SH7091.

Reviewd-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Zack Buhman <zack@buhman.org>
Message-Id: <20240405233802.29128-3-zack@buhman.org>
[rth: Reformat helper_macw, add a test case.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>


  Commit: b754cb2dcde26a7bc8a9d17bb6900a0ac0dd38e2
      
https://github.com/qemu/qemu/commit/b754cb2dcde26a7bc8a9d17bb6900a0ac0dd38e2
  Author: Zack Buhman <zack@buhman.org>
  Date:   2024-04-09 (Tue, 09 Apr 2024)

  Changed paths:
    M target/sh4/translate.c

  Log Message:
  -----------
  target/sh4: add missing CHECK_NOT_DELAY_SLOT

CHECK_NOT_DELAY_SLOT is correctly applied to the branch-related
instructions, but not to the PC-relative mov* instructions.

I verified the existence of an illegal slot exception on a SH7091 when
any of these instructions are attempted inside a delay slot.

This also matches the behavior described in the SH-4 ISA manual.

Signed-off-by: Zack Buhman <zack@buhman.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240407150705.5965-1-zack@buhman.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewd-by: Yoshinori Sato <ysato@users.sourceforge.jp>


  Commit: 5888357942da1fd5a50efb6e4a6af8b1a27a5af8
      
https://github.com/qemu/qemu/commit/5888357942da1fd5a50efb6e4a6af8b1a27a5af8
  Author: Keith Packard <keithp@keithp.com>
  Date:   2024-04-09 (Tue, 09 Apr 2024)

  Changed paths:
    M target/m68k/cpu.c
    M target/m68k/cpu.h
    M target/m68k/fpu_helper.c
    M target/m68k/helper.c
    M target/m68k/helper.h
    M target/m68k/translate.c

  Log Message:
  -----------
  target/m68k: Map FPU exceptions to FPSR register

Add helpers for reading/writing the 68881 FPSR register so that
changes in floating point exception state can be seen by the
application.

Call these helpers in pre_load/post_load hooks to synchronize
exception state.

Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230803035231.429697-1-keithp@keithp.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 07843f75fdaff26950e4ddfd5d03556915fee1a7
      
https://github.com/qemu/qemu/commit/07843f75fdaff26950e4ddfd5d03556915fee1a7
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-04-09 (Tue, 09 Apr 2024)

  Changed paths:
    M include/tcg/tcg.h
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Add TCGContext.emit_before_op

Allow operations to be emitted via normal expanders
into the middle of the opcode stream.

Tested-by: Jørgen Hansen <Jorgen.Hansen@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: e7face702ac1e98109dbfde557e7974ea04a295d
      
https://github.com/qemu/qemu/commit/e7face702ac1e98109dbfde557e7974ea04a295d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-04-09 (Tue, 09 Apr 2024)

  Changed paths:
    M accel/tcg/translator.c
    M include/exec/translator.h

  Log Message:
  -----------
  accel/tcg: Add insn_start to DisasContextBase

This is currently target-specific for many; begin making it
target independent.

Tested-by: Jørgen Hansen <Jorgen.Hansen@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 4642250e3c4c00495c0902ff8f32559ad99ce130
      
https://github.com/qemu/qemu/commit/4642250e3c4c00495c0902ff8f32559ad99ce130
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-04-09 (Tue, 09 Apr 2024)

  Changed paths:
    M target/arm/tcg/translate-a64.c
    M target/arm/tcg/translate.c
    M target/arm/tcg/translate.h

  Log Message:
  -----------
  target/arm: Use insn_start from DisasContextBase

To keep the multiple update check, replace insn_start
with insn_start_updated.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 24638bd17df4bdd7d54634dd5f6a5e8ec1282dc8
      
https://github.com/qemu/qemu/commit/24638bd17df4bdd7d54634dd5f6a5e8ec1282dc8
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-04-09 (Tue, 09 Apr 2024)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Use insn_start from DisasContextBase

To keep the multiple update check, replace insn_start
with insn_start_updated.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 8df1ba49d76e30fa5c8889121f4ed206ad6c2098
      
https://github.com/qemu/qemu/commit/8df1ba49d76e30fa5c8889121f4ed206ad6c2098
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-04-09 (Tue, 09 Apr 2024)

  Changed paths:
    M target/i386/tcg/translate.c

  Log Message:
  -----------
  target/i386: Preserve DisasContextBase.insn_start across rewind

When aborting translation of the current insn, restore the
previous value of insn_start.

Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Tested-by: Jørgen Hansen <Jorgen.Hansen@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: e2313450274659a08d9791435766dc43ab388aa9
      
https://github.com/qemu/qemu/commit/e2313450274659a08d9791435766dc43ab388aa9
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-04-09 (Tue, 09 Apr 2024)

  Changed paths:
    M target/microblaze/translate.c

  Log Message:
  -----------
  target/microblaze: Use insn_start from DisasContextBase

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 401aa608d8d1ee7a4bbf88cae1a16854103324e6
      
https://github.com/qemu/qemu/commit/401aa608d8d1ee7a4bbf88cae1a16854103324e6
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-04-09 (Tue, 09 Apr 2024)

  Changed paths:
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Use insn_start from DisasContextBase

To keep the multiple update check, replace insn_start
with insn_start_updated.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: b338970f8cdcba114dad467e085f3ff13dfa9a43
      
https://github.com/qemu/qemu/commit/b338970f8cdcba114dad467e085f3ff13dfa9a43
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-04-09 (Tue, 09 Apr 2024)

  Changed paths:
    M target/s390x/tcg/translate.c

  Log Message:
  -----------
  target/s390x: Use insn_start from DisasContextBase

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: dcd092a0636ec36e69e42a3dbbe447d97cb0d113
      
https://github.com/qemu/qemu/commit/dcd092a0636ec36e69e42a3dbbe447d97cb0d113
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-04-09 (Tue, 09 Apr 2024)

  Changed paths:
    M accel/tcg/translator.c
    M include/exec/translator.h

  Log Message:
  -----------
  accel/tcg: Improve can_do_io management

We already attempted to set and clear can_do_io before the first
and last insns, but only used the initial value of max_insns and
the call to translator_io_start to find those insns.

Now that we track insn_start in DisasContextBase, and now that
we have emit_before_op, we can wait until we have finished
translation to identify the true first and last insns and emit
the sets of can_do_io at that time.

This fixes the case of a translation block which crossed a page
boundary, and for which the second page turned out to be mmio.
In this case we truncate the block, and the previous logic for
can_do_io could leave a block with a single insn with can_do_io
set to false, which would fail an assertion in cpu_io_recompile.

Reported-by: Jørgen Hansen <Jorgen.Hansen@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Jørgen Hansen <Jorgen.Hansen@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 143bcc1d59f174b6c6743bd4ca8f99415ed1aba2
      
https://github.com/qemu/qemu/commit/143bcc1d59f174b6c6743bd4ca8f99415ed1aba2
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-04-09 (Tue, 09 Apr 2024)

  Changed paths:
    M linux-user/signal.c

  Log Message:
  -----------
  linux-user: Preserve unswapped siginfo_t for strace

Passing the tswapped structure to strace means that
our internal si_type is also gone, which then aborts
in print_siginfo.

Fixes: 4d6d8a05a0a ("linux-user: Move tswap_siginfo out of target code")
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: fee571c7afced9bf4b01b864ea6e85f00fb50e30
      
https://github.com/qemu/qemu/commit/fee571c7afced9bf4b01b864ea6e85f00fb50e30
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-04-09 (Tue, 09 Apr 2024)

  Changed paths:
    M accel/tcg/translator.c
    M include/exec/translator.h
    M include/tcg/tcg.h
    M linux-user/main.c
    M linux-user/signal.c
    M linux-user/syscall.c
    M target/arm/tcg/translate-a64.c
    M target/arm/tcg/translate.c
    M target/arm/tcg/translate.h
    M target/hppa/int_helper.c
    M target/hppa/sys_helper.c
    M target/hppa/translate.c
    M target/i386/tcg/translate.c
    M target/m68k/cpu.c
    M target/m68k/cpu.h
    M target/m68k/fpu_helper.c
    M target/m68k/helper.c
    M target/m68k/helper.h
    M target/m68k/translate.c
    M target/microblaze/translate.c
    M target/riscv/translate.c
    M target/s390x/tcg/translate.c
    M target/sh4/cpu.h
    M target/sh4/helper.h
    M target/sh4/op_helper.c
    M target/sh4/translate.c
    M tcg/optimize.c
    M tcg/tcg.c
    M tests/tcg/aarch64/Makefile.target
    A tests/tcg/aarch64/test-2150.c
    M tests/tcg/sh4/Makefile.target
    A tests/tcg/sh4/test-macl.c
    A tests/tcg/sh4/test-macw.c

  Log Message:
  -----------
  Merge tag 'pull-misc-20240409' of https://gitlab.com/rth7680/qemu into staging

target/m68k: Fix fp accrued exception reporting
target/hppa: Fix IIAOQ, IIASQ for pa2.0
target/sh4: Fixes to mac.l and mac.w saturation
target/sh4: Fixes to illegal delay slot reporting
linux-user: Fix waitid return of siginfo_t and rusage
linux-user: Preserve unswapped siginfo_t for strace
tcg/optimize: Do not attempt to constant fold neg_vec
accel/tcg: Improve can_do_io management, mmio bug fix

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* tag 'pull-misc-20240409' of https://gitlab.com/rth7680/qemu:
  linux-user: Preserve unswapped siginfo_t for strace
  accel/tcg: Improve can_do_io management
  target/s390x: Use insn_start from DisasContextBase
  target/riscv: Use insn_start from DisasContextBase
  target/microblaze: Use insn_start from DisasContextBase
  target/i386: Preserve DisasContextBase.insn_start across rewind
  target/hppa: Use insn_start from DisasContextBase
  target/arm: Use insn_start from DisasContextBase
  accel/tcg: Add insn_start to DisasContextBase
  tcg: Add TCGContext.emit_before_op
  target/m68k: Map FPU exceptions to FPSR register
  target/sh4: add missing CHECK_NOT_DELAY_SLOT
  target/sh4: Fix mac.w with saturation enabled
  target/sh4: Fix mac.l with saturation enabled
  target/sh4: Merge mach and macl into a union
  target/sh4: mac.w: memory accesses are 16-bit words
  target/hppa: Fix IIAOQ, IIASQ for pa2.0
  linux-user: replace calloc() with g_new0()
  linux-user: Fix waitid return of siginfo_t and rusage
  tcg/optimize: Do not attempt to constant fold neg_vec

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/927284d65bce...fee571c7afce

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- [Qemu-commits] [qemu/qemu] e25fe8: tcg/optimize: Do not attempt to constant fold neg_vec, Peter Maydell, 2024/04/10
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