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[Qemu-commits] [qemu/qemu] cbd58e: MAINTAINERS: update email of Peter Li
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] cbd58e: MAINTAINERS: update email of Peter Lieven |
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Date: |
Thu, 25 Apr 2024 08:10:14 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: cbd58e7cc26cef811bd947f48345ec930481e4e2
https://github.com/qemu/qemu/commit/cbd58e7cc26cef811bd947f48345ec930481e4e2
Author: Peter Lieven <pl@kamp.de>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: update email of Peter Lieven
I will leave KAMP in the next days. Update email to stay reachable.
Signed-off-by: Peter Lieven <pl@kamp.de>
Message-ID: <20230105095039.182718-1-pl@kamp.de>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 58045186fccaf400d3938fad220a99b1b5f3da6d
https://github.com/qemu/qemu/commit/58045186fccaf400d3938fad220a99b1b5f3da6d
Author: Inès Varhol <ines.varhol@telecom-paris.fr>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M tests/qtest/aspeed_fsi-test.c
M tests/qtest/cmsdk-apb-dualtimer-test.c
M tests/qtest/cmsdk-apb-watchdog-test.c
M tests/qtest/erst-test.c
M tests/qtest/ivshmem-test.c
M tests/qtest/libqos/ahci.c
M tests/qtest/microbit-test.c
M tests/qtest/sse-timer-test.c
M tests/qtest/stm32l4x5_exti-test.c
M tests/qtest/stm32l4x5_syscfg-test.c
Log Message:
-----------
tests/qtest : Use `g_assert_cmphex` instead of `g_assert_cmpuint`
The messages for assertions using hexadecimal numbers will be
easier to understand with `g_assert_cmphex`.
Cases changed : "cmpuint.*0x", "cmpuint.*<<"
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Ninad Palsule <ninad@linux.ibm.com>
Message-ID: <20240414173349.31194-1-ines.varhol@telecom-paris.fr>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 838f82468a1282f7e89dbbd6c015c8742bfdafce
https://github.com/qemu/qemu/commit/838f82468a1282f7e89dbbd6c015c8742bfdafce
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M docs/system/target-i386-desc.rst.inc
Log Message:
-----------
docs: i386: pc: Update maximum CPU numbers for PC Q35
Commit e4e98c7eebfa ("pc: q35: Bump max_cpus to 4096 vcpus") increases
the supported CPUs for PC Q35 machine.
Update maximum CPU numbers for PC Q35 in the document.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-ID: <20240412085358.731560-1-zhao1.liu@linux.intel.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 5e279f38c7eabfcb9c3ab0bac8ae04316c3d7814
https://github.com/qemu/qemu/commit/5e279f38c7eabfcb9c3ab0bac8ae04316c3d7814
Author: Brad Smith <brad@comstyle.com>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M tests/vm/openbsd
Log Message:
-----------
tests/vm: update openbsd image to 7.5
tests/vm: update openbsd to release 7.5
Signed-off-by: Brad Smith <brad@comstyle.com>
Message-ID: <ZhaDVpNjq_ZifvPT@humpty.home.comstyle.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 6705587adbf11dacb9722e7c4091936439ae5dad
https://github.com/qemu/qemu/commit/6705587adbf11dacb9722e7c4091936439ae5dad
Author: Thomas Huth <thuth@redhat.com>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M .travis.yml
Log Message:
-----------
Revert ".travis.yml: Cache Avocado cache"
This reverts commit c1073e44b46490133e16420e1784dec7bcd4e030.
The Avocado tests have been removed from Travis a long time ago with
commit c5008c76ee ("gitlab: add acceptance testing to system builds"),
so we don't need to cache the avocado files here anymore.
Message-ID: <20240320104144.823425-4-thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: aeb99d0772477c6c94e7def85526ee88fbe6135b
https://github.com/qemu/qemu/commit/aeb99d0772477c6c94e7def85526ee88fbe6135b
Author: Thomas Huth <thuth@redhat.com>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M .travis.yml
Log Message:
-----------
.travis.yml: Remove the unused UNRELIABLE environment variable
This variable was used to allow jobs to fail without spoiling the
overall result. But the required "allow_failures:" hunk has been
accidentally removed in commit 9d03f5abed ("travis.yml: Remove the
"Release tarball" job"), and it was anyway only useful while we
still had the x86 jobs here around that were our main CI jobs.
Thus let's simply remove this useless variable now.
Message-ID: <20240320104144.823425-6-thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 66163bc7d79f40fb323d405559f19edb0f92f72b
https://github.com/qemu/qemu/commit/66163bc7d79f40fb323d405559f19edb0f92f72b
Author: Thomas Huth <thuth@redhat.com>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M .travis.yml
Log Message:
-----------
.travis.yml: Update the jobs to Ubuntu 22.04
According to our support policy, we'll soon drop our official support
for Ubuntu 20.04 ("Focal Fossa") in QEMU. Thus we should update the
Travis jobs now to a newer release (Ubuntu 22.04 - "Jammy Jellyfish")
for future testing. Since all jobs are using this release now, we
can drop the entries from the individual jobs and use the global
setting again.
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-ID: <20240418101056.302103-6-thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 4d6ae2df56b7ef7a479a1656872a95e0ed23f2d9
https://github.com/qemu/qemu/commit/4d6ae2df56b7ef7a479a1656872a95e0ed23f2d9
Author: Thomas Huth <thuth@redhat.com>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M .travis.yml
Log Message:
-----------
.travis.yml: Do some more testing with Clang
We are doing a lot of cross-compilation tests with GCC in the gitlab-CI
already, so we could get some more test coverage by using Clang in the
Travis-CI instead. Thus let's switch two additional jobs to use Clang
for compilation.
Message-ID: <20240320104144.823425-7-thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 45070eb716172cf168f6334fe5346510cdde1a92
https://github.com/qemu/qemu/commit/45070eb716172cf168f6334fe5346510cdde1a92
Author: Thomas Huth <thuth@redhat.com>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
R tests/docker/dockerfiles/ubuntu2004.docker
M tests/lcitool/refresh
Log Message:
-----------
tests: Remove Ubuntu 20.04 container
Since Ubuntu 22.04 has now been available for more than two years, we
can stop actively supporting the previous LTS version of Ubuntu now.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240418101056.302103-2-thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: c723d9d16f15e4255f9bcf293e55763da21ab51f
https://github.com/qemu/qemu/commit/c723d9d16f15e4255f9bcf293e55763da21ab51f
Author: Thomas Huth <thuth@redhat.com>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M tests/lcitool/libvirt-ci
Log Message:
-----------
tests/lcitool/libvirt-ci: Update to the latest master branch
We need the latest fixes for the lcitool to be able to properly
update our CentOS docker file to CentOS Stream 9.
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-ID: <20240418101056.302103-3-thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 2355d18c79e05c2b790113c95c5ccfee35fb7fcf
https://github.com/qemu/qemu/commit/2355d18c79e05c2b790113c95c5ccfee35fb7fcf
Author: Thomas Huth <thuth@redhat.com>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M tests/docker/dockerfiles/alpine.docker
M tests/docker/dockerfiles/centos8.docker
M tests/docker/dockerfiles/debian-amd64-cross.docker
M tests/docker/dockerfiles/debian-arm64-cross.docker
M tests/docker/dockerfiles/debian-armel-cross.docker
M tests/docker/dockerfiles/debian-armhf-cross.docker
M tests/docker/dockerfiles/debian-i686-cross.docker
M tests/docker/dockerfiles/debian-mips64el-cross.docker
M tests/docker/dockerfiles/debian-mipsel-cross.docker
M tests/docker/dockerfiles/debian-ppc64el-cross.docker
M tests/docker/dockerfiles/debian-riscv64-cross.docker
M tests/docker/dockerfiles/debian-s390x-cross.docker
M tests/docker/dockerfiles/debian.docker
M tests/docker/dockerfiles/fedora-win64-cross.docker
M tests/docker/dockerfiles/fedora.docker
M tests/docker/dockerfiles/opensuse-leap.docker
M tests/docker/dockerfiles/ubuntu2204.docker
Log Message:
-----------
tests/docker/dockerfiles: Run lcitool-refresh after the lcitool update
This update adds the removing of the EXTERNALLY-MANAGED marker files
that has been added to the lcitool recently.
Quoting Daniel:
"For those who don't know, python now commonly blocks the ability to
run 'pip install' outside of a venv. This generally makes sense for
a precious installation environment. Our containers are disposable
though, so a venv has no benefit. Removing the 'EXTERNALLY-MANAGED'
allows the historical arbitrary use of 'pip' outside a venv.
lcitool just does this unconditionally given the containers are
not precious."
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-ID: <20240418101056.302103-4-thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 641b1efe01b2dd6e7ac92f23d392dcee73508746
https://github.com/qemu/qemu/commit/641b1efe01b2dd6e7ac92f23d392dcee73508746
Author: Thomas Huth <thuth@redhat.com>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M .gitlab-ci.d/buildtest.yml
M .gitlab-ci.d/container-core.yml
R tests/docker/dockerfiles/centos8.docker
A tests/docker/dockerfiles/centos9.docker
M tests/lcitool/mappings.yml
M tests/lcitool/refresh
M tests/vm/centos
Log Message:
-----------
tests: Update our CI to use CentOS Stream 9 instead of 8
RHEL 9 (and thus also the derivatives) have been available since two
years now, so according to QEMU's support policy, we can drop the active
support for the previous major version 8 now.
Another reason for doing this is that Centos Stream 8 will go EOL soon:
https://blog.centos.org/2023/04/end-dates-are-coming-for-centos-stream-8-and-centos-linux-7/
"After May 31, 2024, CentOS Stream 8 will be archived
and no further updates will be provided."
Thus upgrade our CentOS Stream container to major version 9 now.
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-ID: <20240418101056.302103-5-thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 2b0d2ab895022814da13127e47c17890690488da
https://github.com/qemu/qemu/commit/2b0d2ab895022814da13127e47c17890690488da
Author: Jinjie Ruan <ruanjinjie@huawei.com>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M target/arm/cpu-features.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NMI
FEAT_NMI defines another three new bits in HCRX_EL2: TALLINT, HCRX_VINMI and
HCRX_VFNMI. When the feature is enabled, allow these bits to be written in
HCRX_EL2.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-2-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 6aa20415613096034ac943872aebd49fbe48e2d0
https://github.com/qemu/qemu/commit/6aa20415613096034ac943872aebd49fbe48e2d0
Author: Jinjie Ruan <ruanjinjie@huawei.com>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M target/arm/cpu.h
M target/arm/tcg/helper-a64.c
Log Message:
-----------
target/arm: Add PSTATE.ALLINT
When PSTATE.ALLINT is set, an IRQ or FIQ interrupt that is targeted to
ELx, with or without superpriority is masked. As Richard suggested, place
ALLINT bit in PSTATE in env->pstate.
In the pseudocode, AArch64.ExceptionReturn() calls SetPSTATEFromPSR(), which
treats PSTATE.ALLINT as one of the bits which are reinstated from SPSR to
PSTATE regardless of whether this is an illegal exception return or not. So
handle PSTATE.ALLINT the same way as PSTATE.DAIF in the illegal_return exit
path of the exception_return helper. With the change, exception entry and
return are automatically handled.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-3-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4833c75611e334164b970c79be95f239ce676ab1
https://github.com/qemu/qemu/commit/4833c75611e334164b970c79be95f239ce676ab1
Author: Jinjie Ruan <ruanjinjie@huawei.com>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M target/arm/internals.h
Log Message:
-----------
target/arm: Add support for FEAT_NMI, Non-maskable Interrupt
Add support for FEAT_NMI. NMI (FEAT_NMI) is an mandatory feature in
ARMv8.8-A and ARM v9.3-A.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-4-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: cbf817a2ff7dc12b62e0bccc15ae93369ea5829e
https://github.com/qemu/qemu/commit/cbf817a2ff7dc12b62e0bccc15ae93369ea5829e
Author: Jinjie Ruan <ruanjinjie@huawei.com>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M target/arm/tcg/a64.decode
M target/arm/tcg/helper-a64.c
M target/arm/tcg/helper-a64.h
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Implement ALLINT MSR (immediate)
Add ALLINT MSR (immediate) to decodetree, in which the CRm is 0b000x. The
EL0 check is necessary to ALLINT, and the EL1 check is necessary when
imm == 1. So implement it inline for EL2/3, or EL1 with imm==0. Avoid the
unconditional write to pc and use raise_exception_ra to unwind.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-5-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5c2169746136ffc93bf1e18c294a05e8446d8af7
https://github.com/qemu/qemu/commit/5c2169746136ffc93bf1e18c294a05e8446d8af7
Author: Jinjie Ruan <ruanjinjie@huawei.com>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Support MSR access to ALLINT
Support ALLINT msr access as follow:
mrs <xt>, ALLINT // read allint
msr ALLINT, <xt> // write allint with imm
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-6-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b36a32ead1596929b1fa5436593d49cac20c20e6
https://github.com/qemu/qemu/commit/b36a32ead1596929b1fa5436593d49cac20c20e6
Author: Jinjie Ruan <ruanjinjie@huawei.com>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M target/arm/cpu-qom.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Add support for Non-maskable Interrupt
This only implements the external delivery method via the GICv3.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-7-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 963e4e3648e0601a8f0b288edaf524b3c98fffbd
https://github.com/qemu/qemu/commit/963e4e3648e0601a8f0b288edaf524b3c98fffbd
Author: Jinjie Ruan <ruanjinjie@huawei.com>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Add support for NMI in arm_phys_excp_target_el()
According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt
with superpriority is always IRQ, never FIQ, so handle NMI same as IRQ in
arm_phys_excp_target_el().
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-8-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 2e0be5f6b122e3dca53b926514287ffcead2689c
https://github.com/qemu/qemu/commit/2e0be5f6b122e3dca53b926514287ffcead2689c
Author: Jinjie Ruan <ruanjinjie@huawei.com>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Handle IS/FS in ISR_EL1 for NMI, VINMI and VFNMI
Add IS and FS bit in ISR_EL1 and handle the read. With CPU_INTERRUPT_NMI or
CPU_INTERRUPT_VINMI, both CPSR_I and ISR_IS must be set. With
CPU_INTERRUPT_VFNMI, both CPSR_F and ISR_FS must be set.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-9-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 167f2631df98c5b1af622a9afe3afe00867ef080
https://github.com/qemu/qemu/commit/167f2631df98c5b1af622a9afe3afe00867ef080
Author: Jinjie Ruan <ruanjinjie@huawei.com>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Handle PSTATE.ALLINT on taking an exception
Set or clear PSTATE.ALLINT on taking an exception to ELx according to the
SCTLR_ELx.SPINTMASK bit.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-10-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 83f320753827da6bd381b46b8f3e6736046c86cd
https://github.com/qemu/qemu/commit/83f320753827da6bd381b46b8f3e6736046c86cd
Author: Jinjie Ruan <ruanjinjie@huawei.com>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M hw/intc/arm_gicv3_common.c
M include/hw/intc/arm_gic_common.h
M include/hw/intc/arm_gicv3_common.h
Log Message:
-----------
hw/intc/arm_gicv3: Add external IRQ lines for NMI
Augment the GICv3's QOM device interface by adding one
new set of sysbus IRQ line, to signal NMI to each CPU.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-11-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 34d94b7af9f1dc4cae550ecc7b825c9567741a12
https://github.com/qemu/qemu/commit/34d94b7af9f1dc4cae550ecc7b825c9567741a12
Author: Jinjie Ruan <ruanjinjie@huawei.com>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Wire NMI and VINMI irq lines from GIC to CPU
Wire the new NMI and VINMI interrupt line from the GIC to each CPU if it
is not GICv2.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240407081733.3231820-12-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e4eb290571606c5e6dc7739547b5056389cd92fb
https://github.com/qemu/qemu/commit/e4eb290571606c5e6dc7739547b5056389cd92fb
Author: Jinjie Ruan <ruanjinjie@huawei.com>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64()
According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt
with superpriority is always IRQ, never FIQ, so the NMI exception trap entry
behave like IRQ. And VINMI(vIRQ with Superpriority) can be raised from the
GIC or come from the hcrx_el2.HCRX_VINMI bit, VFNMI(vFIQ with Superpriority)
come from the hcrx_el2.HCRX_VFNMI bit.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-13-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c9e86cbd3400032dc818bf24e823959e565b8b41
https://github.com/qemu/qemu/commit/c9e86cbd3400032dc818bf24e823959e565b8b41
Author: Jinjie Ruan <ruanjinjie@huawei.com>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M hw/intc/arm_gicv3_common.c
M hw/intc/arm_gicv3_dist.c
M hw/intc/gicv3_internal.h
M include/hw/intc/arm_gicv3_common.h
Log Message:
-----------
hw/intc/arm_gicv3: Add has-nmi property to GICv3 device
Add a property has-nmi to the GICv3 device, and use this to set
the NMI bit in the GICD_TYPER register. This isn't visible to
guests yet because the property defaults to false and we won't
set it in the board code until we've landed all of the changes
needed to implement FEAT_GICV3_NMI.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-14-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 67d74e4c54236b53917edfa9f52efb4207064014
https://github.com/qemu/qemu/commit/67d74e4c54236b53917edfa9f52efb4207064014
Author: Jinjie Ruan <ruanjinjie@huawei.com>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M hw/intc/arm_gicv3_kvm.c
Log Message:
-----------
hw/intc/arm_gicv3_kvm: Not set has-nmi=true for the KVM GICv3
So far, there is no FEAT_GICv3_NMI support in the in-kernel GIC, so make it
an error to try to set has-nmi=true for the KVM GICv3.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Message-id: 20240407081733.3231820-15-ruanjinjie@huawei.com
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0e9f4e8e7b9e3bde8b8c0a84c577f64c679b535c
https://github.com/qemu/qemu/commit/0e9f4e8e7b9e3bde8b8c0a84c577f64c679b535c
Author: Jinjie Ruan <ruanjinjie@huawei.com>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M hw/intc/arm_gicv3_common.c
M include/hw/intc/arm_gicv3_common.h
Log Message:
-----------
hw/intc/arm_gicv3: Add irq non-maskable property
A SPI, PPI or SGI interrupt can have non-maskable property. So maintain
non-maskable property in PendingIrq and GICR/GICD. Since add new device
state, it also needs to be migrated, so also save NMI info in
vmstate_gicv3_cpu and vmstate_gicv3.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-16-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7c79d98d2e4de5b8c919002e6ead6bae7f46003d
https://github.com/qemu/qemu/commit/7c79d98d2e4de5b8c919002e6ead6bae7f46003d
Author: Jinjie Ruan <ruanjinjie@huawei.com>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M hw/intc/arm_gicv3_redist.c
M hw/intc/gicv3_internal.h
Log Message:
-----------
hw/intc/arm_gicv3_redist: Implement GICR_INMIR0
Add GICR_INMIR0 register and support access GICR_INMIR0.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-17-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 44ed1e4b9a4df256bb56487ae5150b6807536703
https://github.com/qemu/qemu/commit/44ed1e4b9a4df256bb56487ae5150b6807536703
Author: Jinjie Ruan <ruanjinjie@huawei.com>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M hw/intc/arm_gicv3_dist.c
M hw/intc/gicv3_internal.h
Log Message:
-----------
hw/intc/arm_gicv3: Implement GICD_INMIR
Add GICD_INMIR, GICD_INMIRnE register and support access GICD_INMIR0.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-18-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 28cca59c469b16f1352e784b566fd36ace2be4b4
https://github.com/qemu/qemu/commit/28cca59c469b16f1352e784b566fd36ace2be4b4
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
M hw/intc/gicv3_internal.h
M hw/intc/trace-events
M include/hw/intc/arm_gicv3_common.h
Log Message:
-----------
hw/intc/arm_gicv3: Add NMI handling CPU interface registers
Add the NMIAR CPU interface registers which deal with acknowledging NMI.
When introduce NMI interrupt, there are some updates to the semantics for the
register ICC_IAR1_EL1 and ICC_HPPIR1_EL1. For ICC_IAR1_EL1 register, it
should return 1022 if the intid has non-maskable property. And for
ICC_NMIAR1_EL1 register, it should return 1023 if the intid do not have
non-maskable property. Howerever, these are not necessary for ICC_HPPIR1_EL1
register.
And the APR and RPR has NMI bits which should be handled correctly.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[PMM: Separate out whether cpuif supports NMI from whether the
GIC proper (IRI) supports NMI]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-19-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d2c0c6aab6c6748726149c37159a75751ec6ac92
https://github.com/qemu/qemu/commit/d2c0c6aab6c6748726149c37159a75751ec6ac92
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
M hw/intc/gicv3_internal.h
M hw/intc/trace-events
Log Message:
-----------
hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read()
Implement icv_nmiar1_read() for icc_nmiar1_read(), so add definition for
ICH_LR_EL2.NMI and ICH_AP1R_EL2.NMI bit.
If FEAT_GICv3_NMI is supported, ich_ap_write() should consider ICV_AP1R_EL1.NMI
bit. In icv_activate_irq() and icv_eoir_write(), the ICV_AP1R_EL1.NMI bit
should be set or clear according to the Non-maskable property. And the RPR
priority should also update the NMI bit according to the APR priority NMI bit.
By the way, add gicv3_icv_nmiar1_read trace event.
If the hpp irq is a NMI, the icv iar read should return 1022 and trap for
NMI again
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[PMM: use cs->nmi_support instead of cs->gic->nmi_support]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-20-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d89daa893f51280652032640d77a8bc1dea95bdd
https://github.com/qemu/qemu/commit/d89daa893f51280652032640d77a8bc1dea95bdd
Author: Jinjie Ruan <ruanjinjie@huawei.com>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M hw/intc/arm_gicv3.c
M hw/intc/arm_gicv3_common.c
M hw/intc/arm_gicv3_redist.c
Log Message:
-----------
hw/intc/arm_gicv3: Implement NMI interrupt priority
If GICD_CTLR_DS bit is zero and the NMI is non-secure, the NMI priority is
higher than 0x80, otherwise it is higher than 0x0. And save the interrupt
non-maskable property in hppi.nmi to deliver NMI exception. Since both GICR
and GICD can deliver NMI, it is both necessary to check whether the pending
irq is NMI in gicv3_redist_update_noirqset and gicv3_update_noirqset.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-21-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f3c26a44fe3dc27988f07b7e1c4155b9a55818fc
https://github.com/qemu/qemu/commit/f3c26a44fe3dc27988f07b7e1c4155b9a55818fc
Author: Jinjie Ruan <ruanjinjie@huawei.com>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
Log Message:
-----------
hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update()
In CPU Interface, if the IRQ has the non-maskable property, report NMI to
the corresponding PE.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-22-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c57e81889faa5823d0d47c14a4dfc45914205d71
https://github.com/qemu/qemu/commit/c57e81889faa5823d0d47c14a4dfc45914205d71
Author: Jinjie Ruan <ruanjinjie@huawei.com>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
Log Message:
-----------
hw/intc/arm_gicv3: Report the VINMI interrupt
In vCPU Interface, if the vIRQ has the non-maskable property, report
vINMI to the corresponding vPE.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-23-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 14a164030ada5c5d6f346e152521cb878b142b2a
https://github.com/qemu/qemu/commit/14a164030ada5c5d6f346e152521cb878b142b2a
Author: Jinjie Ruan <ruanjinjie@huawei.com>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/tcg/cpu64.c
Log Message:
-----------
target/arm: Add FEAT_NMI to max
Enable FEAT_NMI on the 'max' CPU.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-24-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5ae47f7aece19c5a6efbf99d000f389278e93c1d
https://github.com/qemu/qemu/commit/5ae47f7aece19c5a6efbf99d000f389278e93c1d
Author: Jinjie Ruan <ruanjinjie@huawei.com>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Enable NMI support in the GIC if the CPU has FEAT_NMI
If the CPU implements FEAT_NMI, then turn on the NMI support in the
GICv3 too. It's permitted to have a configuration with FEAT_NMI in
the CPU (and thus NMI support in the CPU interfaces too) but no NMI
support in the distributor and redistributor, but this isn't a very
useful setup as it's close to having no NMI support at all.
We don't need to gate the enabling of NMI in the GIC behind a
machine version property, because none of our current CPUs
implement FEAT_NMI, and '-cpu max' is not something we maintain
migration compatibility across versions for. So we can always
enable the GIC NMI support when the CPU has it.
Neither hvf nor KVM support NMI in the GIC yet, so we don't enable
it unless we're using TCG.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240407081733.3231820-25-ruanjinjie@huawei.com
[PMM: Update comment and commit message]
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c3a68dfd191682b140951e423b72866102097df9
https://github.com/qemu/qemu/commit/c3a68dfd191682b140951e423b72866102097df9
Author: Anastasia Belova <abelova@astralinux.ru>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M hw/dma/soc_dma.c
Log Message:
-----------
hw/dma: avoid apparent overflow in soc_dma_set_request
In soc_dma_set_request() we try to set a bit in a uint64_t, but we
do it with "1 << ch->num", which can't set any bits past 31;
any use for a channel number of 32 or more would fail due to
integer overflow.
This doesn't happen in practice for our current use of this code,
because the worst case is when we call soc_dma_init() with an
argument of 32 for the number of channels, and QEMU builds with
-fwrapv so the shift into the sign bit is well-defined. However,
it's obviously not the intended behaviour of the code.
Add casts to force the shift to be done as 64-bit arithmetic,
allowing up to 64 channels.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Fixes: afbb5194d4 ("Handle on-chip DMA controllers in one place, convert OMAP
DMA to use it.")
Signed-off-by: Anastasia Belova <abelova@astralinux.ru>
Message-id: 20240409115301.21829-1-abelova@astralinux.ru
[PMM: Edit commit message to clarify that this doesn't actually
bite us in our current usage of this code.]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a6819c1bd0b76d7fa0c8f4ae19e4e80dd61a1502
https://github.com/qemu/qemu/commit/a6819c1bd0b76d7fa0c8f4ae19e4e80dd61a1502
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M linux-user/flat.h
M linux-user/flatload.c
Log Message:
-----------
linux-user/flatload.c: Remove unused bFLT shared-library and ZFLAT code
Ever since the bFLT format support was added in 2006, there has been
a chunk of code in the file guarded by CONFIG_BINFMT_SHARED_FLAT
which is supposedly for shared library support. This is not enabled
and it's not possible to enable it, because if you do you'll run into
the "#error needs checking" in the calc_reloc() function.
Similarly, CONFIG_BINFMT_ZFLAT exists but can't be enabled because of
an "#error code needs checking" in load_flat_file().
This code is obviously unfinished and has never been used; nobody in
the intervening 18 years has complained about this or fixed it, so
just delete the dead code. If anybody ever wants the feature they
can always pull it out of git, or (perhaps better) write it from
scratch based on the current Linux bFLT loader rather than the one of
18 years ago.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240411115313.680433-1-peter.maydell@linaro.org
Commit: 1e0f2b38ac104ec3606750cce847cc9d8e4f66ac
https://github.com/qemu/qemu/commit/1e0f2b38ac104ec3606750cce847cc9d8e4f66ac
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M hw/misc/npcm7xx_clk.c
M hw/misc/npcm7xx_gcr.c
Log Message:
-----------
hw/misc: Don't special case RESET_TYPE_COLD in npcm7xx_clk, gcr
The npcm7xx_clk and npcm7xx_gcr device reset methods look at
the ResetType argument and only handle RESET_TYPE_COLD,
producing a warning if another reset type is passed. This
is different from how every other three-phase-reset method
we have works, and makes it difficult to add new reset types.
A better pattern is "assume that any reset type you don't know
about should be handled like RESET_TYPE_COLD"; switch these
devices to do that. Then adding a new reset type will only
need to touch those devices where its behaviour really needs
to be different from the standard cold reset.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Message-id: 20240412160809.1260625-2-peter.maydell@linaro.org
Commit: ef6ab2922fc94956c0b28c55ec2abe61f71446a9
https://github.com/qemu/qemu/commit/ef6ab2922fc94956c0b28c55ec2abe61f71446a9
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M hw/i2c/allwinner-i2c.c
M hw/sensor/adm1272.c
Log Message:
-----------
allwinner-i2c, adm1272: Use device_cold_reset() for software-triggered reset
Rather than directly calling the device's implementation of its 'hold'
reset phase, call device_cold_reset(). This means we don't have to
adjust this callsite when we add another argument to the function
signature for the hold and exit reset methods.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Message-id: 20240412160809.1260625-3-peter.maydell@linaro.org
Commit: aadea887f4429fcc96429b126c254de94317b474
https://github.com/qemu/qemu/commit/aadea887f4429fcc96429b126c254de94317b474
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
A scripts/coccinelle/reset-type.cocci
Log Message:
-----------
scripts/coccinelle: New script to add ResetType to hold and exit phases
We pass a ResetType argument to the Resettable class enter phase
method, but we don't pass it to hold and exit, even though the
callsites have it readily available. This means that if a device
cared about the ResetType it would need to record it in the enter
phase method to use later on. We should pass the type to all three
of the phase methods to avoid having to do that.
This coccinelle script adds the ResetType argument to the hold and
exit phases of the Resettable interface.
The first part of the script (rules holdfn_assigned, holdfn_defined,
exitfn_assigned, exitfn_defined) update implementations of the
interface within device models, both to change the signature of their
method implementations and to pass on the reset type when they invoke
reset on some other device.
The second part of the script is various special cases:
* method callsites in resettable_phase_hold(), resettable_phase_exit()
and device_phases_reset()
* updating the typedefs for the methods
* isl_pmbus_vr.c has some code where one device's reset method directly
calls the implementation of a different device's method
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Message-id: 20240412160809.1260625-4-peter.maydell@linaro.org
Commit: ad80e36744785fe9326d4104d98e976822e90cc2
https://github.com/qemu/qemu/commit/ad80e36744785fe9326d4104d98e976822e90cc2
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M hw/adc/npcm7xx_adc.c
M hw/arm/pxa2xx_pic.c
M hw/arm/smmu-common.c
M hw/arm/smmuv3.c
M hw/arm/stellaris.c
M hw/audio/asc.c
M hw/char/cadence_uart.c
M hw/char/sifive_uart.c
M hw/core/cpu-common.c
M hw/core/qdev.c
M hw/core/reset.c
M hw/core/resettable.c
M hw/display/virtio-vga.c
M hw/gpio/npcm7xx_gpio.c
M hw/gpio/pl061.c
M hw/gpio/stm32l4x5_gpio.c
M hw/hyperv/vmbus.c
M hw/i2c/allwinner-i2c.c
M hw/i2c/npcm7xx_smbus.c
M hw/input/adb.c
M hw/input/ps2.c
M hw/intc/arm_gic_common.c
M hw/intc/arm_gic_kvm.c
M hw/intc/arm_gicv3_common.c
M hw/intc/arm_gicv3_its.c
M hw/intc/arm_gicv3_its_common.c
M hw/intc/arm_gicv3_its_kvm.c
M hw/intc/arm_gicv3_kvm.c
M hw/intc/xics.c
M hw/m68k/q800-glue.c
M hw/misc/djmemc.c
M hw/misc/iosb.c
M hw/misc/mac_via.c
M hw/misc/macio/cuda.c
M hw/misc/macio/pmu.c
M hw/misc/mos6522.c
M hw/misc/npcm7xx_mft.c
M hw/misc/npcm7xx_pwm.c
M hw/misc/stm32l4x5_exti.c
M hw/misc/stm32l4x5_rcc.c
M hw/misc/stm32l4x5_syscfg.c
M hw/misc/xlnx-versal-cframe-reg.c
M hw/misc/xlnx-versal-crl.c
M hw/misc/xlnx-versal-pmc-iou-slcr.c
M hw/misc/xlnx-versal-trng.c
M hw/misc/xlnx-versal-xramc.c
M hw/misc/xlnx-zynqmp-apu-ctrl.c
M hw/misc/xlnx-zynqmp-crf.c
M hw/misc/zynq_slcr.c
M hw/net/can/xlnx-zynqmp-can.c
M hw/net/e1000.c
M hw/net/e1000e.c
M hw/net/igb.c
M hw/net/igbvf.c
M hw/nvram/xlnx-bbram.c
M hw/nvram/xlnx-versal-efuse-ctrl.c
M hw/nvram/xlnx-zynqmp-efuse.c
M hw/pci-bridge/cxl_root_port.c
M hw/pci-bridge/pcie_root_port.c
M hw/pci-host/bonito.c
M hw/pci-host/pnv_phb.c
M hw/pci-host/pnv_phb3_msi.c
M hw/pci/pci.c
M hw/rtc/mc146818rtc.c
M hw/s390x/css-bridge.c
M hw/sensor/adm1266.c
M hw/sensor/adm1272.c
M hw/sensor/isl_pmbus_vr.c
M hw/sensor/max31785.c
M hw/sensor/max34451.c
M hw/ssi/npcm7xx_fiu.c
M hw/timer/etraxfs_timer.c
M hw/timer/npcm7xx_timer.c
M hw/usb/hcd-dwc2.c
M hw/usb/xlnx-versal-usb2-ctrl-regs.c
M hw/virtio/virtio-pci.c
M include/hw/resettable.h
M target/arm/cpu.c
M target/avr/cpu.c
M target/cris/cpu.c
M target/hexagon/cpu.c
M target/i386/cpu.c
M target/loongarch/cpu.c
M target/m68k/cpu.c
M target/microblaze/cpu.c
M target/mips/cpu.c
M target/openrisc/cpu.c
M target/ppc/cpu_init.c
M target/riscv/cpu.c
M target/rx/cpu.c
M target/sh4/cpu.c
M target/sparc/cpu.c
M target/tricore/cpu.c
M target/xtensa/cpu.c
Log Message:
-----------
hw, target: Add ResetType argument to hold and exit phase methods
We pass a ResetType argument to the Resettable class enter
phase method, but we don't pass it to hold and exit, even though
the callsites have it readily available. This means that if
a device cared about the ResetType it would need to record it
in the enter phase method to use later on. Pass the type to
all three of the phase methods to avoid having to do that.
Commit created with
for dir in hw target include; do \
spatch --macro-file scripts/cocci-macro-file.h \
--sp-file scripts/coccinelle/reset-type.cocci \
--keep-comments --smpl-spacing --in-place \
--include-headers --dir $dir; done
and no manual edits.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Message-id: 20240412160809.1260625-5-peter.maydell@linaro.org
Commit: 41d49ec190db9171d2ebb158fd4d5daad06ed8e1
https://github.com/qemu/qemu/commit/41d49ec190db9171d2ebb158fd4d5daad06ed8e1
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M docs/devel/reset.rst
Log Message:
-----------
docs/devel/reset: Update to new API for hold and exit phase methods
Update the reset documentation's example code to match the new API
for the hold and exit phase method APIs where they take a ResetType
argument.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Message-id: 20240412160809.1260625-6-peter.maydell@linaro.org
Commit: 631f46d4ea7cb7ac0e529aacc1e7d832473f96c3
https://github.com/qemu/qemu/commit/631f46d4ea7cb7ac0e529aacc1e7d832473f96c3
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M docs/devel/reset.rst
M hw/core/reset.c
M hw/core/resettable.c
M include/hw/resettable.h
Log Message:
-----------
reset: Add RESET_TYPE_SNAPSHOT_LOAD
Some devices and machines need to handle the reset before a vmsave
snapshot is loaded differently -- the main user is the handling of
RNG seed information, which does not want to put a new RNG seed into
a ROM blob when we are doing a snapshot load.
Currently this kind of reset handling is supported only for:
* TYPE_MACHINE reset methods, which take a ShutdownCause argument
* reset functions registered with qemu_register_reset_nosnapshotload
To allow a three-phase-reset device to also distinguish "snapshot
load" reset from the normal kind, add a new ResetType
RESET_TYPE_SNAPSHOT_LOAD. All our existing reset methods ignore
the reset type, so we don't need to update any device code.
Add the enum type, and make qemu_devices_reset() use the
right reset type for the ShutdownCause it is passed. This
allows us to get rid of the device_reset_reason global we
were using to implement qemu_register_reset_nosnapshotload().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Message-id: 20240412160809.1260625-7-peter.maydell@linaro.org
Commit: 4fb37aea7e01679db44758eb9407d5a49e3dbd7a
https://github.com/qemu/qemu/commit/4fb37aea7e01679db44758eb9407d5a49e3dbd7a
Author: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M MAINTAINERS
M hw/char/Kconfig
M hw/char/meson.build
A hw/char/stm32l4x5_usart.c
M hw/char/trace-events
A include/hw/char/stm32l4x5_usart.h
Log Message:
-----------
hw/char: Implement STM32L4x5 USART skeleton
Add the basic infrastructure (register read/write, type...)
to implement the STM32L4x5 USART.
Also create different types for the USART, UART and LPUART
of the STM32L4x5 to deduplicate code and enable the
implementation of different behaviors depending on the type.
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240329174402.60382-2-arnaud.minier@telecom-paris.fr
[PMM: update to new reset hold method signature;
fixed a few checkpatch nits]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 87b77e6e01cad9a6cbdc3532a5bb3c674e34d089
https://github.com/qemu/qemu/commit/87b77e6e01cad9a6cbdc3532a5bb3c674e34d089
Author: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M hw/char/stm32l4x5_usart.c
M hw/char/trace-events
M include/hw/char/stm32l4x5_usart.h
Log Message:
-----------
hw/char/stm32l4x5_usart: Enable serial read and write
Implement the ability to read and write characters to the
usart using the serial port.
The character transmission is based on the
cmsdk-apb-uart implementation.
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240329174402.60382-3-arnaud.minier@telecom-paris.fr
[PMM: fixed a few checkpatch nits]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c4c12ee48709aeb896ebb60163e8eb26cdaa3d65
https://github.com/qemu/qemu/commit/c4c12ee48709aeb896ebb60163e8eb26cdaa3d65
Author: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M hw/char/stm32l4x5_usart.c
M hw/char/trace-events
Log Message:
-----------
hw/char/stm32l4x5_usart: Add options for serial parameters setting
Add a function to change the settings of the
serial connection.
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240329174402.60382-4-arnaud.minier@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 92741432ed6f98ab01bdace5baaf2894c7855563
https://github.com/qemu/qemu/commit/92741432ed6f98ab01bdace5baaf2894c7855563
Author: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M docs/system/arm/b-l475e-iot01a.rst
M hw/arm/Kconfig
M hw/arm/stm32l4x5_soc.c
M include/hw/arm/stm32l4x5_soc.h
Log Message:
-----------
hw/arm: Add the USART to the stm32l4x5 SoC
Add the USART to the SoC and connect it to the other implemented devices.
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240329174402.60382-5-arnaud.minier@telecom-paris.fr
[PMM: fixed a few checkpatch nits]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 214652da123e3821657a64691ee556281e9f6238
https://github.com/qemu/qemu/commit/214652da123e3821657a64691ee556281e9f6238
Author: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M tests/qtest/meson.build
A tests/qtest/stm32l4x5_usart-test.c
Log Message:
-----------
tests/qtest: Add tests for the STM32L4x5 USART
Test:
- read/write from/to the usart registers
- send/receive a character/string over the serial port
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240329174402.60382-6-arnaud.minier@telecom-paris.fr
[PMM: fix checkpatch nits, remove commented out code]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9a72bea6828ef3f9c957fde1a390a81d66b38cec
https://github.com/qemu/qemu/commit/9a72bea6828ef3f9c957fde1a390a81d66b38cec
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M hw/s390x/s390-stattrib.c
M hw/s390x/s390-virtio-hcall.h
Log Message:
-----------
hw/s390x: Include missing 'cpu.h' header
"cpu.h" is implicitly included. Include it explicitly to
avoid the following error when refactoring headers:
hw/s390x/s390-stattrib.c:86:40: error: use of undeclared identifier
'TARGET_PAGE_SIZE'
len = sac->peek_stattr(sas, addr / TARGET_PAGE_SIZE, buflen, vals);
^
hw/s390x/s390-stattrib.c:94:58: error: use of undeclared identifier
'TARGET_PAGE_MASK'
addr / TARGET_PAGE_SIZE, len, addr & ~TARGET_PAGE_MASK);
^
hw/s390x/s390-stattrib.c:224:40: error: use of undeclared identifier
'TARGET_PAGE_BITS'
qemu_put_be64(f, (start_gfn << TARGET_PAGE_BITS) | STATTR_FLAG_MORE);
^
In file included from hw/s390x/s390-virtio-ccw.c:17:
hw/s390x/s390-virtio-hcall.h:22:27: error: unknown type name 'CPUS390XState'
int s390_virtio_hypercall(CPUS390XState *env);
^
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Acked-by: Eric Farman <farman@linux.ibm.com>
Message-ID: <20240322162822.7391-1-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: b1f8536c943dd1d0ffea081d79001ee124157f97
https://github.com/qemu/qemu/commit/b1f8536c943dd1d0ffea081d79001ee124157f97
Author: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M docs/devel/submitting-a-patch.rst
Log Message:
-----------
docs/devel: fix minor typo in submitting-a-patch.rst
s/Resolved:/Resolves:/
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Message-ID: <20240422124128.4034482-1-manos.pitsidianakis@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 73a1e96935dbaec950a310916eec13b46871b8b2
https://github.com/qemu/qemu/commit/73a1e96935dbaec950a310916eec13b46871b8b2
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M tests/unit/test-nested-aio-poll.c
Log Message:
-----------
tests/unit: Remove debug statements in test-nested-aio-poll.c
We have been running this test for almost a year; it
is safe to remove its debug statements, which clutter
CI jobs output:
▶ 88/100 /nested-aio-poll OK
io_read 0x16bb26158
io_poll_true 0x16bb26158
> io_poll_ready
io_read 0x16bb26164
< io_poll_ready
io_poll_true 0x16bb26158
io_poll_false 0x16bb26164
> io_poll_ready
io_poll_false 0x16bb26164
io_poll_false 0x16bb26164
io_poll_false 0x16bb26164
io_poll_false 0x16bb26164
io_poll_false 0x16bb26164
io_poll_false 0x16bb26164
io_poll_false 0x16bb26164
io_poll_false 0x16bb26164
io_poll_false 0x16bb26164
io_read 0x16bb26164
< io_poll_ready
88/100 qemu:unit / test-nested-aio-poll OK
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-ID: <20240422112246.83812-1-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 17523a38194d80f2955c6a8e0702e0fc86dd083d
https://github.com/qemu/qemu/commit/17523a38194d80f2955c6a8e0702e0fc86dd083d
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M target/s390x/cpu_models.h
Log Message:
-----------
target/s390x: Remove KVM stubs in cpu_models.h
Since the calls are elided when KVM is not available,
we can remove the stubs (which are never compiled).
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240419090631.48055-1-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 45bef95ca5e9d649e432f2acd82163fb5bccbe47
https://github.com/qemu/qemu/commit/45bef95ca5e9d649e432f2acd82163fb5bccbe47
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M .gitlab-ci.d/buildtest.yml
M .gitlab-ci.d/container-core.yml
M .travis.yml
M MAINTAINERS
M docs/devel/submitting-a-patch.rst
M docs/system/target-i386-desc.rst.inc
M hw/s390x/s390-stattrib.c
M hw/s390x/s390-virtio-hcall.h
M target/s390x/cpu_models.h
M tests/docker/dockerfiles/alpine.docker
R tests/docker/dockerfiles/centos8.docker
A tests/docker/dockerfiles/centos9.docker
M tests/docker/dockerfiles/debian-amd64-cross.docker
M tests/docker/dockerfiles/debian-arm64-cross.docker
M tests/docker/dockerfiles/debian-armel-cross.docker
M tests/docker/dockerfiles/debian-armhf-cross.docker
M tests/docker/dockerfiles/debian-i686-cross.docker
M tests/docker/dockerfiles/debian-mips64el-cross.docker
M tests/docker/dockerfiles/debian-mipsel-cross.docker
M tests/docker/dockerfiles/debian-ppc64el-cross.docker
M tests/docker/dockerfiles/debian-riscv64-cross.docker
M tests/docker/dockerfiles/debian-s390x-cross.docker
M tests/docker/dockerfiles/debian.docker
M tests/docker/dockerfiles/fedora-win64-cross.docker
M tests/docker/dockerfiles/fedora.docker
M tests/docker/dockerfiles/opensuse-leap.docker
R tests/docker/dockerfiles/ubuntu2004.docker
M tests/docker/dockerfiles/ubuntu2204.docker
M tests/lcitool/libvirt-ci
M tests/lcitool/mappings.yml
M tests/lcitool/refresh
M tests/qtest/aspeed_fsi-test.c
M tests/qtest/cmsdk-apb-dualtimer-test.c
M tests/qtest/cmsdk-apb-watchdog-test.c
M tests/qtest/erst-test.c
M tests/qtest/ivshmem-test.c
M tests/qtest/libqos/ahci.c
M tests/qtest/microbit-test.c
M tests/qtest/sse-timer-test.c
M tests/qtest/stm32l4x5_exti-test.c
M tests/qtest/stm32l4x5_syscfg-test.c
M tests/unit/test-nested-aio-poll.c
M tests/vm/centos
M tests/vm/openbsd
Log Message:
-----------
Merge tag 'pull-request-2024-04-25' of https://gitlab.com/thuth/qemu into
staging
* Update OpenBSD CI image to 7.5
* Update/remove Ubuntu 20.04 CI jobs
* Update (most) CentOS 8 CI jobs to CentOS 9
* Some clean-ups and improvements to travis.yml
* Minor test fixes
* s390x header clean-ups
* Doc updates
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# gpg: Signature made Thu 25 Apr 2024 07:55:42 AM PDT
# gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg: aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full]
* tag 'pull-request-2024-04-25' of https://gitlab.com/thuth/qemu:
target/s390x: Remove KVM stubs in cpu_models.h
tests/unit: Remove debug statements in test-nested-aio-poll.c
docs/devel: fix minor typo in submitting-a-patch.rst
hw/s390x: Include missing 'cpu.h' header
tests: Update our CI to use CentOS Stream 9 instead of 8
tests/docker/dockerfiles: Run lcitool-refresh after the lcitool update
tests/lcitool/libvirt-ci: Update to the latest master branch
tests: Remove Ubuntu 20.04 container
.travis.yml: Do some more testing with Clang
.travis.yml: Update the jobs to Ubuntu 22.04
.travis.yml: Remove the unused UNRELIABLE environment variable
Revert ".travis.yml: Cache Avocado cache"
tests/vm: update openbsd image to 7.5
docs: i386: pc: Update maximum CPU numbers for PC Q35
tests/qtest : Use `g_assert_cmphex` instead of `g_assert_cmpuint`
MAINTAINERS: update email of Peter Lieven
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 83baec642a13a69398a2643a1f905606c13cd363
https://github.com/qemu/qemu/commit/83baec642a13a69398a2643a1f905606c13cd363
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M MAINTAINERS
M docs/devel/reset.rst
M docs/system/arm/b-l475e-iot01a.rst
M docs/system/arm/emulation.rst
M hw/adc/npcm7xx_adc.c
M hw/arm/Kconfig
M hw/arm/pxa2xx_pic.c
M hw/arm/smmu-common.c
M hw/arm/smmuv3.c
M hw/arm/stellaris.c
M hw/arm/stm32l4x5_soc.c
M hw/arm/virt.c
M hw/audio/asc.c
M hw/char/Kconfig
M hw/char/cadence_uart.c
M hw/char/meson.build
M hw/char/sifive_uart.c
A hw/char/stm32l4x5_usart.c
M hw/char/trace-events
M hw/core/cpu-common.c
M hw/core/qdev.c
M hw/core/reset.c
M hw/core/resettable.c
M hw/display/virtio-vga.c
M hw/dma/soc_dma.c
M hw/gpio/npcm7xx_gpio.c
M hw/gpio/pl061.c
M hw/gpio/stm32l4x5_gpio.c
M hw/hyperv/vmbus.c
M hw/i2c/allwinner-i2c.c
M hw/i2c/npcm7xx_smbus.c
M hw/input/adb.c
M hw/input/ps2.c
M hw/intc/arm_gic_common.c
M hw/intc/arm_gic_kvm.c
M hw/intc/arm_gicv3.c
M hw/intc/arm_gicv3_common.c
M hw/intc/arm_gicv3_cpuif.c
M hw/intc/arm_gicv3_dist.c
M hw/intc/arm_gicv3_its.c
M hw/intc/arm_gicv3_its_common.c
M hw/intc/arm_gicv3_its_kvm.c
M hw/intc/arm_gicv3_kvm.c
M hw/intc/arm_gicv3_redist.c
M hw/intc/gicv3_internal.h
M hw/intc/trace-events
M hw/intc/xics.c
M hw/m68k/q800-glue.c
M hw/misc/djmemc.c
M hw/misc/iosb.c
M hw/misc/mac_via.c
M hw/misc/macio/cuda.c
M hw/misc/macio/pmu.c
M hw/misc/mos6522.c
M hw/misc/npcm7xx_clk.c
M hw/misc/npcm7xx_gcr.c
M hw/misc/npcm7xx_mft.c
M hw/misc/npcm7xx_pwm.c
M hw/misc/stm32l4x5_exti.c
M hw/misc/stm32l4x5_rcc.c
M hw/misc/stm32l4x5_syscfg.c
M hw/misc/xlnx-versal-cframe-reg.c
M hw/misc/xlnx-versal-crl.c
M hw/misc/xlnx-versal-pmc-iou-slcr.c
M hw/misc/xlnx-versal-trng.c
M hw/misc/xlnx-versal-xramc.c
M hw/misc/xlnx-zynqmp-apu-ctrl.c
M hw/misc/xlnx-zynqmp-crf.c
M hw/misc/zynq_slcr.c
M hw/net/can/xlnx-zynqmp-can.c
M hw/net/e1000.c
M hw/net/e1000e.c
M hw/net/igb.c
M hw/net/igbvf.c
M hw/nvram/xlnx-bbram.c
M hw/nvram/xlnx-versal-efuse-ctrl.c
M hw/nvram/xlnx-zynqmp-efuse.c
M hw/pci-bridge/cxl_root_port.c
M hw/pci-bridge/pcie_root_port.c
M hw/pci-host/bonito.c
M hw/pci-host/pnv_phb.c
M hw/pci-host/pnv_phb3_msi.c
M hw/pci/pci.c
M hw/rtc/mc146818rtc.c
M hw/s390x/css-bridge.c
M hw/sensor/adm1266.c
M hw/sensor/adm1272.c
M hw/sensor/isl_pmbus_vr.c
M hw/sensor/max31785.c
M hw/sensor/max34451.c
M hw/ssi/npcm7xx_fiu.c
M hw/timer/etraxfs_timer.c
M hw/timer/npcm7xx_timer.c
M hw/usb/hcd-dwc2.c
M hw/usb/xlnx-versal-usb2-ctrl-regs.c
M hw/virtio/virtio-pci.c
M include/hw/arm/stm32l4x5_soc.h
A include/hw/char/stm32l4x5_usart.h
M include/hw/intc/arm_gic_common.h
M include/hw/intc/arm_gicv3_common.h
M include/hw/resettable.h
M linux-user/flat.h
M linux-user/flatload.c
A scripts/coccinelle/reset-type.cocci
M target/arm/cpu-features.h
M target/arm/cpu-qom.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/internals.h
M target/arm/tcg/a64.decode
M target/arm/tcg/cpu64.c
M target/arm/tcg/helper-a64.c
M target/arm/tcg/helper-a64.h
M target/arm/tcg/translate-a64.c
M target/avr/cpu.c
M target/cris/cpu.c
M target/hexagon/cpu.c
M target/i386/cpu.c
M target/loongarch/cpu.c
M target/m68k/cpu.c
M target/microblaze/cpu.c
M target/mips/cpu.c
M target/openrisc/cpu.c
M target/ppc/cpu_init.c
M target/riscv/cpu.c
M target/rx/cpu.c
M target/sh4/cpu.c
M target/sparc/cpu.c
M target/tricore/cpu.c
M target/xtensa/cpu.c
M tests/qtest/meson.build
A tests/qtest/stm32l4x5_usart-test.c
Log Message:
-----------
Merge tag 'pull-target-arm-20240425' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* Implement FEAT_NMI and NMI support in the GICv3
* hw/dma: avoid apparent overflow in soc_dma_set_request
* linux-user/flatload.c: Remove unused bFLT shared-library and ZFLAT code
* Add ResetType argument to Resettable hold and exit phase methods
* Add RESET_TYPE_SNAPSHOT_LOAD ResetType
* Implement STM32L4x5 USART
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# gpg: Signature made Thu 25 Apr 2024 03:36:03 AM PDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
* tag 'pull-target-arm-20240425' of
https://git.linaro.org/people/pmaydell/qemu-arm: (37 commits)
tests/qtest: Add tests for the STM32L4x5 USART
hw/arm: Add the USART to the stm32l4x5 SoC
hw/char/stm32l4x5_usart: Add options for serial parameters setting
hw/char/stm32l4x5_usart: Enable serial read and write
hw/char: Implement STM32L4x5 USART skeleton
reset: Add RESET_TYPE_SNAPSHOT_LOAD
docs/devel/reset: Update to new API for hold and exit phase methods
hw, target: Add ResetType argument to hold and exit phase methods
scripts/coccinelle: New script to add ResetType to hold and exit phases
allwinner-i2c, adm1272: Use device_cold_reset() for software-triggered reset
hw/misc: Don't special case RESET_TYPE_COLD in npcm7xx_clk, gcr
linux-user/flatload.c: Remove unused bFLT shared-library and ZFLAT code
hw/dma: avoid apparent overflow in soc_dma_set_request
hw/arm/virt: Enable NMI support in the GIC if the CPU has FEAT_NMI
target/arm: Add FEAT_NMI to max
hw/intc/arm_gicv3: Report the VINMI interrupt
hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update()
hw/intc/arm_gicv3: Implement NMI interrupt priority
hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read()
hw/intc/arm_gicv3: Add NMI handling CPU interface registers
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/5da72194df36...83baec642a13
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