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[Qemu-commits] [qemu/qemu] ea8618: target/arm: Correct comments about M-
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] ea8618: target/arm: Correct comments about M-profile FPSCR |
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Date: |
Thu, 11 Jul 2024 14:32:02 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: ea8618382aba2a7a8a993e61237f2af933fba9ad
https://github.com/qemu/qemu/commit/ea8618382aba2a7a8a993e61237f2af933fba9ad
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-07-11 (Thu, 11 Jul 2024)
Changed paths:
M target/arm/vfp_helper.c
Log Message:
-----------
target/arm: Correct comments about M-profile FPSCR
The M-profile FPSCR LTPSIZE is bits [18:16]; this is the same
field as A-profile FPSCR Len, not Stride. Correct the comment
in vfp_get_fpscr().
We also implemented M-profile FPSCR.QC, but forgot to delete
a TODO comment from vfp_set_fpscr(); remove it now.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240628142347.1283015-2-peter.maydell@linaro.org
Commit: 2de7cf9e0568f18203004a839c9bea0cb9ce96d3
https://github.com/qemu/qemu/commit/2de7cf9e0568f18203004a839c9bea0cb9ce96d3
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-07-11 (Thu, 11 Jul 2024)
Changed paths:
M target/arm/cpu.h
M target/arm/vfp_helper.c
Log Message:
-----------
target/arm: Make vfp_get_fpscr() call vfp_get_{fpcr, fpsr}
In AArch32, the floating point control and status bits are all in a
single register, FPSCR. In AArch64, these were split into separate
FPCR and FPSR registers, but the bit layouts remained the same, with
no overlaps, so that you could construct an FPSCR value by ORing FPCR
and FPSR, or equivalently could produce FPSR and FPCR by masking an
FPSCR value. For QEMU's implementation, we opted to use masking to
produce FPSR and FPCR, because we started with an AArch32
implementation of FPSCR.
The addition of the (AArch64-only) FEAT_AFP adds new bits to the FPCR
which overlap with some bits in the FPSR. This means we'll no longer
be able to consider the FPSCR-encoded value as the primary one, but
instead need to treat FPSR/FPCR as the primary encoding and construct
the FPSCR from those. (This remains possible because the FEAT_AFP
bits in FPCR don't appear in the FPSCR.)
As the first step in this refactoring, make vfp_get_fpscr() call
vfp_get_fpcr() and vfp_get_fpsr(), instead of the other way around.
Note that vfp_get_fpcsr_from_host() returns only bits in the FPSR
(for the cumulative fp exception bits), so we can simply rename
it without needing to add a new function for getting FPCR bits.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240628142347.1283015-3-peter.maydell@linaro.org
Commit: b167325e938706433f00400a0586cedbe965d76d
https://github.com/qemu/qemu/commit/b167325e938706433f00400a0586cedbe965d76d
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-07-11 (Thu, 11 Jul 2024)
Changed paths:
M target/arm/cpu.h
M target/arm/vfp_helper.c
Log Message:
-----------
target/arm: Make vfp_set_fpscr() call vfp_set_{fpcr, fpsr}
Make vfp_set_fpscr() call vfp_set_fpsr() and vfp_set_fpcr()
instead of the other way around.
The masking we do when getting and setting vfp.xregs[ARM_VFP_FPSCR]
is a little awkward, but we are going to change where we store the
underlying FPSR and FPCR information in a later commit, so it will
go away then.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240628142347.1283015-4-peter.maydell@linaro.org
Commit: abf1046a155bc73ceb2c3be3fdfb9c8ffebf9dd1
https://github.com/qemu/qemu/commit/abf1046a155bc73ceb2c3be3fdfb9c8ffebf9dd1
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-07-11 (Thu, 11 Jul 2024)
Changed paths:
M target/arm/machine.c
Log Message:
-----------
target/arm: Support migration when FPSR/FPCR won't fit in the FPSCR
To support FPSR and FPCR bits that don't exist in the AArch32 FPSCR
view of floating point control and status (such as the FEAT_AFP ones),
we need to make sure those bits can be migrated. This commit allows
that, whilst maintaining backwards and forwards migration compatibility
for CPUs where there are no such bits:
On sending:
* If either the FPCR or the FPSR include set bits that are not
visible in the AArch32 FPSCR view of floating point control/status
then we send the FPCR and FPSR as two separate fields in a new
cpu/vfp/fpcr_fpsr subsection, and we send a 0 for the old
FPSCR field in cpu/vfp
* Otherwise, we don't send the fpcr_fpsr subsection, and we send
an FPSCR-format value in cpu/vfp as we did previously
On receiving:
* if we see a non-zero FPSCR field, that is the right information
* if we see a fpcr_fpsr subsection then that has the information
* if we see neither, then FPSCR/FPCR/FPSR are all zero on the source;
cpu_pre_load() ensures the CPU state defaults to that
* if we see both, then the migration source is buggy or malicious;
either the fpcr_fpsr or the FPSCR will "win" depending which
is first in the migration stream; we don't care which that is
We make the new FPCR and FPSR on-the-wire data be 64 bits, because
architecturally these registers are that wide, and this avoids the
need to engage in further migration-compatibility contortions in
future if some new architecture revision defines bits in the high
half of either register.
(We won't ever send the new migration subsection until we add support
for a CPU feature which enables setting overlapping FPCR bits, like
FEAT_AFP.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240628142347.1283015-5-peter.maydell@linaro.org
Commit: 81ae37dbb4a5c5b8eb54bc7f5e6c69097eacb9d2
https://github.com/qemu/qemu/commit/81ae37dbb4a5c5b8eb54bc7f5e6c69097eacb9d2
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-07-11 (Thu, 11 Jul 2024)
Changed paths:
M target/arm/tcg/translate-a32.h
Log Message:
-----------
target/arm: Implement store_cpu_field_low32() macro
We already have a load_cpu_field_low32() to load the low half of a
64-bit CPU struct field to a TCGv_i32; however we haven't yet needed
the store equivalent. We'll want that in the next patch, so
implement it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240628142347.1283015-6-peter.maydell@linaro.org
Commit: ce07ea61ed3b2c92f3a679016d8fa1c285c207a2
https://github.com/qemu/qemu/commit/ce07ea61ed3b2c92f3a679016d8fa1c285c207a2
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-07-11 (Thu, 11 Jul 2024)
Changed paths:
M target/arm/cpu.h
M target/arm/tcg/mve_helper.c
M target/arm/tcg/translate-m-nocp.c
M target/arm/tcg/translate-vfp.c
M target/arm/tcg/translate.h
M target/arm/vfp_helper.c
Log Message:
-----------
target/arm: Store FPSR and FPCR in separate CPU state fields
Now that we have refactored the set/get functions so that the FPSCR
format is no longer the authoritative one, we can keep FPSR and FPCR
in separate CPU state fields.
As well as the get and set functions, we also have a scattering of
places in the code which directly access vfp.xregs[ARM_VFP_FPSCR] to
extract single fields which are stored there. These all change to
directly access either vfp.fpsr or vfp.fpcr, depending on the
location of the field. (Most commonly, this is the NZCV flags.)
We make the field in the CPU state struct 64 bits, because
architecturally FPSR and FPCR are 64 bits. However we leave the
types of the arguments and return values of the get/set functions as
32 bits, since we don't need to make that change with the current
architecture and various callsites would be unable to handle
set bits in the high half (for instance the gdbstub protocol
assumes they're only 32 bit registers).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240628142347.1283015-7-peter.maydell@linaro.org
Commit: a26db547b7d571d97d33afc0f952afa34678ea3b
https://github.com/qemu/qemu/commit/a26db547b7d571d97d33afc0f952afa34678ea3b
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-07-11 (Thu, 11 Jul 2024)
Changed paths:
M target/arm/cpu.h
M target/arm/tcg/mve_helper.c
M target/arm/tcg/translate-m-nocp.c
M target/arm/tcg/translate-vfp.c
M target/arm/vfp_helper.c
Log Message:
-----------
target/arm: Rename FPCR_ QC, NZCV macros to FPSR_
The QC, N, Z, C, V bits live in the FPSR, not the FPCR. Rename the
macros that define these bits accordingly.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240628142347.1283015-8-peter.maydell@linaro.org
Commit: db397a81eea8a7dce25804398caa750fd6700e49
https://github.com/qemu/qemu/commit/db397a81eea8a7dce25804398caa750fd6700e49
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-07-11 (Thu, 11 Jul 2024)
Changed paths:
M target/arm/cpu.h
M target/arm/machine.c
M target/arm/vfp_helper.c
Log Message:
-----------
target/arm: Rename FPSR_MASK and FPCR_MASK and define them symbolically
Now that we store FPSR and FPCR separately, the FPSR_MASK and
FPCR_MASK macros are slightly confusingly named and the comment
describing them is out of date. Rename them to FPSCR_FPSR_MASK and
FPSCR_FPCR_MASK, document that they are the mask of which FPSCR bits
are architecturally mapped to which AArch64 register, and define them
symbolically rather than as hex values. (This latter requires
defining some extra macros for bits which we haven't previously
defined.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240628142347.1283015-9-peter.maydell@linaro.org
Commit: a8ab8706d4cc461481ce419e62e3ad48b03638a8
https://github.com/qemu/qemu/commit/a8ab8706d4cc461481ce419e62e3ad48b03638a8
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-07-11 (Thu, 11 Jul 2024)
Changed paths:
M target/arm/vfp_helper.c
Log Message:
-----------
target/arm: Allow FPCR bits that aren't in FPSCR
In order to allow FPCR bits that aren't in the FPSCR (like the new
bits that are defined for FEAT_AFP), we need to make sure that writes
to the FPSCR only write to the bits of FPCR that are architecturally
mapped, and not the others.
Implement this with a new function vfp_set_fpcr_masked() which
takes a mask of which bits to update.
(We could do the same for FPSR, but we leave that until we actually
are likely to need it.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240628142347.1283015-10-peter.maydell@linaro.org
Commit: b88cfee90268cad376682da8f99ccf024d7aa304
https://github.com/qemu/qemu/commit/b88cfee90268cad376682da8f99ccf024d7aa304
Author: Zheyu Ma <zheyuma97@gmail.com>
Date: 2024-07-11 (Thu, 11 Jul 2024)
Changed paths:
M hw/char/pl011.c
Log Message:
-----------
hw/char/pl011: Avoid division-by-zero in pl011_get_baudrate()
In pl011_get_baudrate(), when we calculate the baudrate we can
accidentally divide by zero. This happens because although (as the
specification requires) we treat UARTIBRD = 0 as invalid, we aren't
correctly limiting UARTIBRD and UARTFBRD values to the 16-bit and 6-bit
ranges the hardware allows, and so some non-zero values of UARTIBRD can
result in a zero divisor.
Enforce the correct register field widths on guest writes and on inbound
migration to avoid the division by zero.
ASAN log:
==2973125==ERROR: AddressSanitizer: FPE on unknown address 0x55f72629b348
(pc 0x55f72629b348 bp 0x7fffa24d0e00 sp 0x7fffa24d0d60 T0)
#0 0x55f72629b348 in pl011_get_baudrate hw/char/pl011.c:255:17
#1 0x55f726298d94 in pl011_trace_baudrate_change hw/char/pl011.c:260:33
#2 0x55f726296fc8 in pl011_write hw/char/pl011.c:378:9
Reproducer:
cat << EOF | qemu-system-aarch64 -display \
none -machine accel=qtest, -m 512M -machine realview-pb-a8 -qtest stdio
writeq 0x1000b024 0xf8000000
EOF
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Zheyu Ma <zheyuma97@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240702155752.3022007-1-zheyuma97@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7b11e7cf73fd637671c88c71c28204d157533193
https://github.com/qemu/qemu/commit/7b11e7cf73fd637671c88c71c28204d157533193
Author: Zheyu Ma <zheyuma97@gmail.com>
Date: 2024-07-11 (Thu, 11 Jul 2024)
Changed paths:
M hw/misc/bcm2835_thermal.c
Log Message:
-----------
hw/misc/bcm2835_thermal: Fix access size handling in bcm2835_thermal_ops
The current implementation of bcm2835_thermal_ops sets
impl.max_access_size and valid.min_access_size to 4, but leaves
impl.min_access_size and valid.max_access_size unset, defaulting to 1.
This causes issues when the memory system is presented with an access
of size 2 at an offset of 3, leading to an attempt to synthesize it as
a pair of byte accesses at offsets 3 and 4, which trips an assert.
Additionally, the lack of valid.max_access_size setting causes another
issue: the memory system tries to synthesize a read using a 4-byte
access at offset 3 even though the device doesn't allow unaligned
accesses.
This patch addresses these issues by explicitly setting both
impl.min_access_size and valid.max_access_size to 4, ensuring proper
handling of access sizes.
Error log:
ERROR:hw/misc/bcm2835_thermal.c:55:bcm2835_thermal_read: code should not be
reached
Bail out! ERROR:hw/misc/bcm2835_thermal.c:55:bcm2835_thermal_read: code should
not be reached
Aborted
Reproducer:
cat << EOF | qemu-system-aarch64 -display \
none -machine accel=qtest, -m 512M -machine raspi3b -m 1G -qtest stdio
readw 0x3f212003
EOF
Signed-off-by: Zheyu Ma <zheyuma97@gmail.com>
Message-id: 20240702154042.3018932-1-zheyuma97@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: efceb7d2bd5cb0f82045b7945810c5c029f60eb2
https://github.com/qemu/qemu/commit/efceb7d2bd5cb0f82045b7945810c5c029f60eb2
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-07-11 (Thu, 11 Jul 2024)
Changed paths:
M target/arm/cpu.h
Log Message:
-----------
target/arm: Use cpu_env in cpu_untagged_addr
In a completely artifical memset benchmark object_dynamic_cast_assert
dominates the profile, even above guest address resolution and
the underlying host memset.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240702154911.1667418-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: fcee3707eb0331a7270d9c93ba68e832e8ff8b98
https://github.com/qemu/qemu/commit/fcee3707eb0331a7270d9c93ba68e832e8ff8b98
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-07-11 (Thu, 11 Jul 2024)
Changed paths:
M target/arm/cpu.c
M target/arm/internals.h
M target/arm/tcg/cpu-v7m.c
Log Message:
-----------
target/arm: Set arm_v7m_tcg_ops cpu_exec_halt to arm_cpu_exec_halt()
In commit a96edb687e76 we set the cpu_exec_halt field of the
TCGCPUOps arm_tcg_ops to arm_cpu_exec_halt(), but we left the
arm_v7m_tcg_ops struct unchanged. That isn't wrong, because for
M-profile FEAT_WFxT doesn't exist and the default handling for "no
cpu_exec_halt method" is correct, but it's perhaps a little
confusing. We would also like to make setting the cpu_exec_halt
method mandatory.
Initialize arm_v7m_tcg_ops cpu_exec_halt to the same function we use
for A-profile. (On M-profile we never set up the wfxt timer so there
is no change in behaviour here.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 4f7b1ecba81c9dab8066e891ead8a4fff95781af
https://github.com/qemu/qemu/commit/4f7b1ecba81c9dab8066e891ead8a4fff95781af
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-07-11 (Thu, 11 Jul 2024)
Changed paths:
M target/alpha/cpu.c
M target/avr/cpu.c
M target/cris/cpu.c
M target/hppa/cpu.c
M target/loongarch/cpu.c
M target/m68k/cpu.c
M target/microblaze/cpu.c
M target/mips/cpu.c
M target/openrisc/cpu.c
M target/ppc/cpu_init.c
M target/riscv/cpu.c
M target/riscv/internals.h
M target/riscv/tcg/tcg-cpu.c
M target/rx/cpu.c
M target/s390x/cpu.c
M target/sh4/cpu.c
M target/sparc/cpu.c
M target/tricore/cpu.c
M target/xtensa/cpu.c
Log Message:
-----------
target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation
Currently the TCGCPUOps::cpu_exec_halt method is optional, and if it
is not set then the default is to call the CPUClass::has_work
method (which has an identical function signature).
We would like to make the cpu_exec_halt method mandatory so we can
remove the runtime check and fallback handling. In preparation for
that, make all the targets which don't need special handling in their
cpu_exec_halt set it to their cpu_has_work implementation instead of
leaving it unset. (This is every target except for arm and i386.)
In the riscv case this requires us to make the function not
be local to the source file it's defined in.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 0487c631801bf21e5e2ca8a54bf207fb78bd64bf
https://github.com/qemu/qemu/commit/0487c631801bf21e5e2ca8a54bf207fb78bd64bf
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-07-11 (Thu, 11 Jul 2024)
Changed paths:
M accel/tcg/cpu-exec.c
M include/hw/core/tcg-cpu-ops.h
Log Message:
-----------
accel/tcg: Make TCGCPUOps::cpu_exec_halt mandatory
Now that all targets set TCGCPUOps::cpu_exec_halt, we can make it
mandatory and remove the fallback handling that calls cpu_has_work.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 27d405301a676beffea4c13f5108c344fa6b8165
https://github.com/qemu/qemu/commit/27d405301a676beffea4c13f5108c344fa6b8165
Author: Inès Varhol <ines.varhol@telecom-paris.fr>
Date: 2024-07-11 (Thu, 11 Jul 2024)
Changed paths:
M hw/misc/stm32l4x5_exti.c
M include/hw/misc/stm32l4x5_exti.h
Log Message:
-----------
hw/misc: In STM32L4x5 EXTI, consolidate 2 constants
Up until now, the EXTI implementation had 16 inbound GPIOs connected to
the 16 outbound GPIOs of STM32L4x5 SYSCFG.
The EXTI actually handles 40 lines (namely 5 from STM32L4x5 USART
devices which are already implemented in QEMU).
In order to connect USART devices to EXTI, this commit consolidates
constants `EXTI_NUM_INTERRUPT_OUT_LINES` (40) and
`EXTI_NUM_GPIO_EVENT_IN_LINES` (16) into `EXTI_NUM_LINES` (40).
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240707085927.122867-2-ines.varhol@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: bc080002cea5893fcbb0e651f6482f27a19356fb
https://github.com/qemu/qemu/commit/bc080002cea5893fcbb0e651f6482f27a19356fb
Author: Inès Varhol <ines.varhol@telecom-paris.fr>
Date: 2024-07-11 (Thu, 11 Jul 2024)
Changed paths:
M hw/misc/stm32l4x5_exti.c
Log Message:
-----------
hw/misc: In STM32L4x5 EXTI, handle direct interrupts
The previous implementation for EXTI interrupts only handled
"configurable" interrupts, like those originating from STM32L4x5 SYSCFG
(the only device currently connected to the EXTI up until now).
In order to connect STM32L4x5 USART to the EXTI, this commit adds
handling for direct interrupts (interrupts without configurable edge).
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Message-id: 20240707085927.122867-3-ines.varhol@telecom-paris.fr
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 29f0bef71a80d05cd19b95fce93833383c2b9aa2
https://github.com/qemu/qemu/commit/29f0bef71a80d05cd19b95fce93833383c2b9aa2
Author: Inès Varhol <ines.varhol@telecom-paris.fr>
Date: 2024-07-11 (Thu, 11 Jul 2024)
Changed paths:
M hw/arm/stm32l4x5_soc.c
Log Message:
-----------
hw/arm: In STM32L4x5 SOC, connect USART devices to EXTI
The USART devices were previously connecting their outbound IRQs
directly to the CPU because the EXTI wasn't handling direct lines
interrupts.
Now the USART connects to the EXTI inbound GPIOs, and the EXTI connects
its IRQs to the CPU.
The existing QTest for the USART (tests/qtest/stm32l4x5_usart-test.c)
checks that USART1_IRQ in the CPU is pending when expected so it
confirms that the connection through the EXTI still works.
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240707085927.122867-4-ines.varhol@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 97b06ab705fcd1e4454ac6efba1abe0d72e444b2
https://github.com/qemu/qemu/commit/97b06ab705fcd1e4454ac6efba1abe0d72e444b2
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-07-11 (Thu, 11 Jul 2024)
Changed paths:
M target/arm/tcg/a64.decode
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Convert SMULL, UMULL, SMLAL, UMLAL, SMLSL, UMLSL to decodetree
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240709000610.382391-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: eb191187f68eed87cb694c98af985a8cd199af6a
https://github.com/qemu/qemu/commit/eb191187f68eed87cb694c98af985a8cd199af6a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-07-11 (Thu, 11 Jul 2024)
Changed paths:
M target/arm/tcg/a64.decode
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Convert SADDL, SSUBL, SABDL, SABAL, and unsigned to decodetree
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240709000610.382391-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7575c5710c2e269299534f598d1094fb4b30c87b
https://github.com/qemu/qemu/commit/7575c5710c2e269299534f598d1094fb4b30c87b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-07-11 (Thu, 11 Jul 2024)
Changed paths:
M target/arm/tcg/a64.decode
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Convert SQDMULL, SQDMLAL, SQDMLSL to decodetree
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240709000610.382391-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 26cb9dbed83ec1028d1dfac5ce7f37c8257e133b
https://github.com/qemu/qemu/commit/26cb9dbed83ec1028d1dfac5ce7f37c8257e133b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-07-11 (Thu, 11 Jul 2024)
Changed paths:
M target/arm/tcg/a64.decode
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Convert SADDW, SSUBW, UADDW, USUBW to decodetree
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240709000610.382391-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f7a8456586840d3ab83f63e023186e58ef9ae6cb
https://github.com/qemu/qemu/commit/f7a8456586840d3ab83f63e023186e58ef9ae6cb
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-07-11 (Thu, 11 Jul 2024)
Changed paths:
M target/arm/tcg/a64.decode
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Convert ADDHN, SUBHN, RADDHN, RSUBHN to decodetree
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240709000610.382391-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7f49089158a4db644fcbadfa90cd3d30a4868735
https://github.com/qemu/qemu/commit/7f49089158a4db644fcbadfa90cd3d30a4868735
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-07-11 (Thu, 11 Jul 2024)
Changed paths:
M target/arm/tcg/a64.decode
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Convert PMULL to decodetree
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240709000610.382391-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 23901b2b721c0576007ab7580da8aa855d6042a9
https://github.com/qemu/qemu/commit/23901b2b721c0576007ab7580da8aa855d6042a9
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-07-11 (Thu, 11 Jul 2024)
Changed paths:
M accel/tcg/cpu-exec.c
M hw/arm/stm32l4x5_soc.c
M hw/char/pl011.c
M hw/misc/bcm2835_thermal.c
M hw/misc/stm32l4x5_exti.c
M include/hw/core/tcg-cpu-ops.h
M include/hw/misc/stm32l4x5_exti.h
M target/alpha/cpu.c
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/internals.h
M target/arm/machine.c
M target/arm/tcg/a64.decode
M target/arm/tcg/cpu-v7m.c
M target/arm/tcg/mve_helper.c
M target/arm/tcg/translate-a32.h
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate-m-nocp.c
M target/arm/tcg/translate-vfp.c
M target/arm/tcg/translate.h
M target/arm/vfp_helper.c
M target/avr/cpu.c
M target/cris/cpu.c
M target/hppa/cpu.c
M target/loongarch/cpu.c
M target/m68k/cpu.c
M target/microblaze/cpu.c
M target/mips/cpu.c
M target/openrisc/cpu.c
M target/ppc/cpu_init.c
M target/riscv/cpu.c
M target/riscv/internals.h
M target/riscv/tcg/tcg-cpu.c
M target/rx/cpu.c
M target/s390x/cpu.c
M target/sh4/cpu.c
M target/sparc/cpu.c
M target/tricore/cpu.c
M target/xtensa/cpu.c
Log Message:
-----------
Merge tag 'pull-target-arm-20240711' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* Refactor FPCR/FPSR handling in preparation for FEAT_AFP
* More decodetree conversions
* target/arm: Use cpu_env in cpu_untagged_addr
* target/arm: Set arm_v7m_tcg_ops cpu_exec_halt to arm_cpu_exec_halt()
* hw/char/pl011: Avoid division-by-zero in pl011_get_baudrate()
* hw/misc/bcm2835_thermal: Fix access size handling in bcm2835_thermal_ops
* accel/tcg: Make TCGCPUOps::cpu_exec_halt mandatory
* STM32L4x5: Handle USART interrupts correctly
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# gpg: Signature made Thu 11 Jul 2024 06:17:55 AM PDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
* tag 'pull-target-arm-20240711' of
https://git.linaro.org/people/pmaydell/qemu-arm: (24 commits)
target/arm: Convert PMULL to decodetree
target/arm: Convert ADDHN, SUBHN, RADDHN, RSUBHN to decodetree
target/arm: Convert SADDW, SSUBW, UADDW, USUBW to decodetree
target/arm: Convert SQDMULL, SQDMLAL, SQDMLSL to decodetree
target/arm: Convert SADDL, SSUBL, SABDL, SABAL, and unsigned to decodetree
target/arm: Convert SMULL, UMULL, SMLAL, UMLAL, SMLSL, UMLSL to decodetree
hw/arm: In STM32L4x5 SOC, connect USART devices to EXTI
hw/misc: In STM32L4x5 EXTI, handle direct interrupts
hw/misc: In STM32L4x5 EXTI, consolidate 2 constants
accel/tcg: Make TCGCPUOps::cpu_exec_halt mandatory
target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation
target/arm: Set arm_v7m_tcg_ops cpu_exec_halt to arm_cpu_exec_halt()
target/arm: Use cpu_env in cpu_untagged_addr
hw/misc/bcm2835_thermal: Fix access size handling in bcm2835_thermal_ops
hw/char/pl011: Avoid division-by-zero in pl011_get_baudrate()
target/arm: Allow FPCR bits that aren't in FPSCR
target/arm: Rename FPSR_MASK and FPCR_MASK and define them symbolically
target/arm: Rename FPCR_ QC, NZCV macros to FPSR_
target/arm: Store FPSR and FPCR in separate CPU state fields
target/arm: Implement store_cpu_field_low32() macro
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/39a032cea23e...23901b2b721c
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