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[Qemu-commits] [qemu/qemu] 6eab27: target/riscv: Add zimop extension
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] 6eab27: target/riscv: Add zimop extension |
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Date: |
Thu, 18 Jul 2024 04:29:16 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 6eab278d389bc3569135773265e0d481d89ef82e
https://github.com/qemu/qemu/commit/6eab278d389bc3569135773265e0d481d89ef82e
Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Date: 2024-07-18 (Thu, 18 Jul 2024)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/insn32.decode
A target/riscv/insn_trans/trans_rvzimop.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Add zimop extension
Zimop extension defines an encoding space for 40 MOPs.The Zimop
extension defines 32 MOP instructions named MOP.R.n, where n is
an integer between 0 and 31, inclusive. The Zimop extension
additionally defines 8 MOP instructions named MOP.RR.n, where n
is an integer between 0 and 7.
These 40 MOPs initially are defined to simply write zero to x[rd],
but are designed to be redefined by later extensions to perform some
other action.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Deepak Gupta <debug@rivosinc.com>
Message-ID: <20240709113652.1239-2-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: d98883d127d0029532601e9ca6832dfcb3ee2ca0
https://github.com/qemu/qemu/commit/d98883d127d0029532601e9ca6832dfcb3ee2ca0
Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Date: 2024-07-18 (Thu, 18 Jul 2024)
Changed paths:
M disas/riscv.c
Log Message:
-----------
disas/riscv: Support zimop disassemble
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Deepak Gupta <debug@rivosinc.com>
Message-ID: <20240709113652.1239-3-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 197e4d29889453760c74763662e3812d0ec7a645
https://github.com/qemu/qemu/commit/197e4d29889453760c74763662e3812d0ec7a645
Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Date: 2024-07-18 (Thu, 18 Jul 2024)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/insn16.decode
A target/riscv/insn_trans/trans_rvzcmop.c.inc
M target/riscv/tcg/tcg-cpu.c
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Add zcmop extension
Zcmop defines eight 16-bit MOP instructions named C.MOP.n, where n is
an odd integer between 1 and 15, inclusive. C.MOP.n is encoded in
the reserved encoding space corresponding to C.LUI xn, 0.
Unlike the MOPs defined in the Zimop extension, the C.MOP.n instructions
are defined to not write any register.
In current implementation, C.MOP.n only has an check function, without any
other more behavior.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Deepak Gupta <debug@rivosinc.com>
Message-ID: <20240709113652.1239-4-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 67e98ebad063e8b028466a754578dd8386aaa5f6
https://github.com/qemu/qemu/commit/67e98ebad063e8b028466a754578dd8386aaa5f6
Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Date: 2024-07-18 (Thu, 18 Jul 2024)
Changed paths:
M disas/riscv.c
Log Message:
-----------
disas/riscv: Support zcmop disassemble
Although in QEMU disassemble, we usually lift compressed instruction
to an normal format when display the instruction name. For C.MOP.n,
it is more reasonable to directly display its compressed name, because
its behavior can be redefined by later extension.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Deepak Gupta <debug@rivosinc.com>
Message-ID: <20240709113652.1239-5-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a60ce58fd971bdcbec6ba96ce989fd399ca1f2d7
https://github.com/qemu/qemu/commit/a60ce58fd971bdcbec6ba96ce989fd399ca1f2d7
Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Date: 2024-07-18 (Thu, 18 Jul 2024)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/insn_trans/trans_rva.c.inc
M target/riscv/insn_trans/trans_rvd.c.inc
M target/riscv/insn_trans/trans_rvf.c.inc
M target/riscv/insn_trans/trans_rvi.c.inc
Log Message:
-----------
target/riscv: Support Zama16b extension
Zama16b is the property that misaligned load/stores/atomics within
a naturally aligned 16-byte region are atomic.
According to the specification, Zama16b applies only to AMOs, loads
and stores defined in the base ISAs, and loads and stores of no more
than XLEN bits defined in the F, D, and Q extensions. Thus it should
not apply to zacas or RVC instructions.
For an instruction in that set, if all accessed bytes lie within 16B granule,
the instruction will not raise an exception for reasons of address alignment,
and the instruction will give rise to only one memory operation for the
purposes of RVWMO—i.e., it will execute atomically.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240709113652.1239-6-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 24da9cbacacadaf95fbddc11da81ff68d3b1e795
https://github.com/qemu/qemu/commit/24da9cbacacadaf95fbddc11da81ff68d3b1e795
Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Date: 2024-07-18 (Thu, 18 Jul 2024)
Changed paths:
M target/riscv/insn_trans/trans_rva.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Move gen_amo before implement Zabha
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240709113652.1239-7-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: be4a8db7f304347395b081ae5848bad2f507d0c4
https://github.com/qemu/qemu/commit/be4a8db7f304347395b081ae5848bad2f507d0c4
Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Date: 2024-07-18 (Thu, 18 Jul 2024)
Changed paths:
M target/riscv/cpu_cfg.h
M target/riscv/insn32.decode
A target/riscv/insn_trans/trans_rvzabha.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Add AMO instructions for Zabha
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240709113652.1239-8-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 8d07887bcbf13749224bd10b0303f7a79a959edb
https://github.com/qemu/qemu/commit/8d07887bcbf13749224bd10b0303f7a79a959edb
Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Date: 2024-07-18 (Thu, 18 Jul 2024)
Changed paths:
M target/riscv/insn_trans/trans_rvzacas.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Move gen_cmpxchg before adding amocas.[b|h]
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240709113652.1239-9-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: d34e4066025378dff8d444104100d3b07e127fe6
https://github.com/qemu/qemu/commit/d34e4066025378dff8d444104100d3b07e127fe6
Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Date: 2024-07-18 (Thu, 18 Jul 2024)
Changed paths:
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvzabha.c.inc
Log Message:
-----------
target/riscv: Add amocas.[b|h] for Zabha
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240709113652.1239-10-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 8aebaa2591320619cbd3e75f91f6e088f2c3dcfa
https://github.com/qemu/qemu/commit/8aebaa2591320619cbd3e75f91f6e088f2c3dcfa
Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Date: 2024-07-18 (Thu, 18 Jul 2024)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Expose zabha extension as a cpu property
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240709113652.1239-11-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: ae4bdcef6fd3166264a47ed6a17cb9870e32306e
https://github.com/qemu/qemu/commit/ae4bdcef6fd3166264a47ed6a17cb9870e32306e
Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Date: 2024-07-18 (Thu, 18 Jul 2024)
Changed paths:
M disas/riscv.c
Log Message:
-----------
disas/riscv: Support zabha disassemble
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240709113652.1239-12-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 910c18a91738f9b77c5faf66e3534bb10d6e306e
https://github.com/qemu/qemu/commit/910c18a91738f9b77c5faf66e3534bb10d6e306e
Author: Jiayi Li <lijiayi@eswincomputing.com>
Date: 2024-07-18 (Thu, 18 Jul 2024)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Validate the mode in write_vstvec
Base on the riscv-privileged spec, vstvec substitutes for the usual stvec.
Therefore, the encoding of the MODE should also be restricted to 0 and 1.
Signed-off-by: Jiayi Li <lijiayi@eswincomputing.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20240701022553.1982-1-lijiayi@eswincomputing.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4d46d84ea7fbb694125b95c88e788caf6cd039fa
https://github.com/qemu/qemu/commit/4d46d84ea7fbb694125b95c88e788caf6cd039fa
Author: Balaji Ravikumar <bravikumar@rivosinc.com>
Date: 2024-07-18 (Thu, 18 Jul 2024)
Changed paths:
M disas/riscv.c
Log Message:
-----------
disas/riscv: Add decode for Zawrs extension
Add disassembly support for these instructions from Zawrs:
* wrs.sto
* wrs.nto
Signed-off-by: Balaji Ravikumar <bravikumar@rivosinc.com>
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240705165316.127494-1-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 3cb9f20499cd7da644387a17a79230f8ffd89993
https://github.com/qemu/qemu/commit/3cb9f20499cd7da644387a17a79230f8ffd89993
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-07-18 (Thu, 18 Jul 2024)
Changed paths:
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv/kvm: update KVM regs to Linux 6.10-rc5
Two new regs added: ztso and zacas.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240709085431.455541-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 68c05fb53036f59a55a54c943b713e8ac78fc627
https://github.com/qemu/qemu/commit/68c05fb53036f59a55a54c943b713e8ac78fc627
Author: Rajnesh Kanwal <rkanwal@rivosinc.com>
Date: 2024-07-18 (Thu, 18 Jul 2024)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/op_helper.c
Log Message:
-----------
target/riscv: Combine set_mode and set_virt functions.
Combining riscv_cpu_set_virt_enabled() and riscv_cpu_set_mode()
functions. This is to make complete mode change information
available through a single function.
This allows to easily differentiate between HS->VS, VS->HS
and VS->VS transitions when executing state update codes.
For example: One use-case which inspired this change is
to update mode-specific instruction and cycle counters
which requires information of both prev mode and current
mode.
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240711-smcntrpmf_v7-v8-1-b7c38ae7b263@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: be470e597708451e6fecb0631728fa759164d03e
https://github.com/qemu/qemu/commit/be470e597708451e6fecb0631728fa759164d03e
Author: Atish Patra <atishp@rivosinc.com>
Date: 2024-07-18 (Thu, 18 Jul 2024)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Fix the predicate functions for mhpmeventhX CSRs
mhpmeventhX CSRs are available for RV32. The predicate function
should check that first before checking sscofpmf extension.
Fixes: 14664483457b ("target/riscv: Add sscofpmf extension support")
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-ID: <20240711-smcntrpmf_v7-v8-2-b7c38ae7b263@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 251dccc09af363900436656461151681687e2470
https://github.com/qemu/qemu/commit/251dccc09af363900436656461151681687e2470
Author: Kaiwen Xue <kaiwenx@rivosinc.com>
Date: 2024-07-18 (Thu, 18 Jul 2024)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
Log Message:
-----------
target/riscv: Add cycle & instret privilege mode filtering properties
This adds the properties for ISA extension smcntrpmf. Patches
implementing it will follow.
Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240711-smcntrpmf_v7-v8-3-b7c38ae7b263@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 6d1e3893cfaeedb47a16edbb766fcc0c7907ab94
https://github.com/qemu/qemu/commit/6d1e3893cfaeedb47a16edbb766fcc0c7907ab94
Author: Kaiwen Xue <kaiwenx@rivosinc.com>
Date: 2024-07-18 (Thu, 18 Jul 2024)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
Log Message:
-----------
target/riscv: Add cycle & instret privilege mode filtering definitions
This adds the definitions for ISA extension smcntrpmf.
Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-ID: <20240711-smcntrpmf_v7-v8-4-b7c38ae7b263@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b54a84c15e389a4795022cc7edfe3a7e32dc065d
https://github.com/qemu/qemu/commit/b54a84c15e389a4795022cc7edfe3a7e32dc065d
Author: Kaiwen Xue <kaiwenx@rivosinc.com>
Date: 2024-07-18 (Thu, 18 Jul 2024)
Changed paths:
M target/riscv/cpu_bits.h
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Add cycle & instret privilege mode filtering support
QEMU only calculates dummy cycles and instructions, so there is no
actual means to stop the icount in QEMU. Hence this patch merely adds
the functionality of accessing the cfg registers, and cause no actual
effects on the counting of cycle and instret counters.
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240711-smcntrpmf_v7-v8-5-b7c38ae7b263@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 3b31b7baff02b357a6c921b26ae953e04d0cfdbb
https://github.com/qemu/qemu/commit/3b31b7baff02b357a6c921b26ae953e04d0cfdbb
Author: Atish Patra <atishp@rivosinc.com>
Date: 2024-07-18 (Thu, 18 Jul 2024)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Only set INH fields if priv mode is available
Currently, the INH fields are set in mhpmevent uncoditionally
without checking if a particular priv mode is supported or not.
Suggested-by: Alistair Francis <alistair23@gmail.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240711-smcntrpmf_v7-v8-6-b7c38ae7b263@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b2d7a7c7e4e30fb5341d38deac968de675f9419c
https://github.com/qemu/qemu/commit/b2d7a7c7e4e30fb5341d38deac968de675f9419c
Author: Atish Patra <atishp@rivosinc.com>
Date: 2024-07-18 (Thu, 18 Jul 2024)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/pmu.c
M target/riscv/pmu.h
Log Message:
-----------
target/riscv: Implement privilege mode filtering for cycle/instret
Privilege mode filtering can also be emulated for cycle/instret by
tracking host_ticks/icount during each privilege mode switch. This
patch implements that for both cycle/instret and mhpmcounters. The
first one requires Smcntrpmf while the other one requires Sscofpmf
to be enabled.
The cycle/instret are still computed using host ticks when icount
is not enabled. Otherwise, they are computed using raw icount which
is more accurate in icount mode.
Co-Developed-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-ID: <20240711-smcntrpmf_v7-v8-7-b7c38ae7b263@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 46023470e014234f3e15ec4497e003550bd7da0d
https://github.com/qemu/qemu/commit/46023470e014234f3e15ec4497e003550bd7da0d
Author: Atish Patra <atishp@rivosinc.com>
Date: 2024-07-18 (Thu, 18 Jul 2024)
Changed paths:
M target/riscv/cpu.h
M target/riscv/csr.c
M target/riscv/machine.c
Log Message:
-----------
target/riscv: Save counter values during countinhibit update
Currently, if a counter monitoring cycle/instret is stopped via
mcountinhibit we just update the state while the value is saved
during the next read. This is not accurate as the read may happen
many cycles after the counter is stopped. Ideally, the read should
return the value saved when the counter is stopped.
Thus, save the value of the counter during the inhibit update
operation and return that value during the read if corresponding bit
in mcountihibit is set.
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-ID: <20240711-smcntrpmf_v7-v8-8-b7c38ae7b263@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 8cff74c26dbdfc746d8f0165c233be3d396d4572
https://github.com/qemu/qemu/commit/8cff74c26dbdfc746d8f0165c233be3d396d4572
Author: Atish Patra <atishp@rivosinc.com>
Date: 2024-07-18 (Thu, 18 Jul 2024)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Enforce WARL behavior for scounteren/hcounteren
scounteren/hcountern are also WARL registers similar to mcountern.
Only set the bits for the available counters during the write to
preserve the WARL behavior.
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240711-smcntrpmf_v7-v8-9-b7c38ae7b263@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 22c721c34c1609b5ac53dfc0d34125ec479205a0
https://github.com/qemu/qemu/commit/22c721c34c1609b5ac53dfc0d34125ec479205a0
Author: Rajnesh Kanwal <rkanwal@rivosinc.com>
Date: 2024-07-18 (Thu, 18 Jul 2024)
Changed paths:
M target/riscv/csr.c
M target/riscv/pmu.c
Log Message:
-----------
target/riscv: Start counters from both mhpmcounter and mcountinhibit
Currently we start timer counter from write_mhpmcounter path only
without checking for mcountinhibit bit. This changes adds mcountinhibit
check and also programs the counter from write_mcountinhibit as well.
When a counter is stopped using mcountinhibit we simply update
the value of the counter based on current host ticks and save
it for future reads.
We don't need to disable running timer as pmu_timer_trigger_irq
will discard the interrupt if the counter has been inhibited.
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240711-smcntrpmf_v7-v8-10-b7c38ae7b263@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 74112400df659b0edb1da35db5c948313ffeffd0
https://github.com/qemu/qemu/commit/74112400df659b0edb1da35db5c948313ffeffd0
Author: Rajnesh Kanwal <rkanwal@rivosinc.com>
Date: 2024-07-18 (Thu, 18 Jul 2024)
Changed paths:
M target/riscv/csr.c
M target/riscv/pmu.c
M target/riscv/pmu.h
Log Message:
-----------
target/riscv: More accurately model priv mode filtering.
In case of programmable counters configured to count inst/cycles
we often end-up with counter not incrementing at all from kernel's
perspective.
For example:
- Kernel configures hpm3 to count instructions and sets hpmcounter
to -10000 and all modes except U mode are inhibited.
- In QEMU we configure a timer to expire after ~10000 instructions.
- Problem is, it's often the case that kernel might not even schedule
Umode task and we hit the timer callback in QEMU.
- In the timer callback we inject the interrupt into kernel, kernel
runs the handler and reads hpmcounter3 value.
- Given QEMU maintains individual counters to count for each privilege
mode, and given umode never ran, the umode counter didn't increment
and QEMU returns same value as was programmed by the kernel when
starting the counter.
- Kernel checks for overflow using previous and current value of the
counter and reprograms the counter given there wasn't an overflow
as per the counter value. (Which itself is a problem. We have QEMU
telling kernel that counter3 overflowed but the counter value
returned by QEMU doesn't seem to reflect that.).
This change makes sure that timer is reprogrammed from the handler
if the counter didn't overflow based on the counter value.
Second, this change makes sure that whenever the counter is read,
it's value is updated to reflect the latest count.
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240711-smcntrpmf_v7-v8-11-b7c38ae7b263@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: dd4c123636dbdabd7dcc4f76c97af90271cd5fb6
https://github.com/qemu/qemu/commit/dd4c123636dbdabd7dcc4f76c97af90271cd5fb6
Author: Atish Patra <atishp@rivosinc.com>
Date: 2024-07-18 (Thu, 18 Jul 2024)
Changed paths:
M target/riscv/pmu.c
Log Message:
-----------
target/riscv: Do not setup pmu timer if OF is disabled
The timer is setup function is invoked in both hpmcounter
write and mcountinhibit write path. If the OF bit set, the
LCOFI interrupt is disabled. There is no benefitting in
setting up the qemu timer until LCOFI is cleared to indicate
that interrupts can be fired again.
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-ID: <20240711-smcntrpmf_v7-v8-12-b7c38ae7b263@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 6f6592d62ebaffff353bdd27ec4480972695d24b
https://github.com/qemu/qemu/commit/6f6592d62ebaffff353bdd27ec4480972695d24b
Author: Atish Patra <atishp@rivosinc.com>
Date: 2024-07-18 (Thu, 18 Jul 2024)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Expose the Smcntrpmf config
Create a new config for Smcntrpmf extension so that it can be enabled/
disabled from the qemu commandline.
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240711-smcntrpmf_v7-v8-13-b7c38ae7b263@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 38c83e8d3a333b8b377367756a2b6c700c7d0084
https://github.com/qemu/qemu/commit/38c83e8d3a333b8b377367756a2b6c700c7d0084
Author: Yu-Ming Chang <yumin686@andestech.com>
Date: 2024-07-18 (Thu, 18 Jul 2024)
Changed paths:
M target/riscv/cpu.h
M target/riscv/csr.c
M target/riscv/op_helper.c
Log Message:
-----------
target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
Both CSRRS and CSRRC always read the addressed CSR and cause any read side
effects regardless of rs1 and rd fields. Note that if rs1 specifies a register
holding a zero value other than x0, the instruction will still attempt to write
the unmodified value back to the CSR and will cause any attendant side effects.
So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specifies
a register holding a zero value, an illegal instruction exception should be
raised.
Signed-off-by: Yu-Ming Chang <yumin686@andestech.com>
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <172100444279.18077.6893072378718059541-0@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 38facfa84328e4ee5a80f7082a01e10c768ee50a
https://github.com/qemu/qemu/commit/38facfa84328e4ee5a80f7082a01e10c768ee50a
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-07-18 (Thu, 18 Jul 2024)
Changed paths:
M docs/about/deprecated.rst
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt.c: re-insert and deprecate 'riscv,delegate'
Commit b1f1e9dcfa renamed 'riscv,delegate' to 'riscv,delegation' since
it is the correct name as per dt-bindings, and the absence of the
correct name will result in validation fails when dumping the dtb and
using dt-validate.
But this change has a side-effect: every other firmware available that
is AIA capable is using 'riscv,delegate', and it will fault/misbehave if
this property isn't present. The property was added back in QEMU 7.0,
meaning we have 2 years of firmware development using the wrong
property.
Re-introducing 'riscv,delegate' while keeping 'riscv,delegation' allows
older firmwares to keep booting with the 'virt' machine.
'riscv,delegate' is then marked for future deprecation with its use
being discouraged from now on.
Cc: Conor Dooley <conor@kernel.org>
Cc: Anup Patel <apatel@ventanamicro.com>
Fixes: b1f1e9dcfa ("hw/riscv/virt.c: aplic DT: rename prop to 'riscv,
delegation'")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240715090455.145888-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: daff9f7f7a457f78ce455e6abf19c2a37dfe7630
https://github.com/qemu/qemu/commit/daff9f7f7a457f78ce455e6abf19c2a37dfe7630
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2024-07-18 (Thu, 18 Jul 2024)
Changed paths:
M pc-bios/opensbi-riscv32-generic-fw_dynamic.bin
M pc-bios/opensbi-riscv64-generic-fw_dynamic.bin
M roms/opensbi
Log Message:
-----------
roms/opensbi: Update to v1.5
Update OpenSBI and the pre-built opensbi32 and opensbi64 images to
v1.5.
The following commits were included in v1.5:
455de67 include: Bump-up version to 1.5
23b7bad lib: sbi: check incoming dbtr shmem address
0e45b63 docs: Fix wrong filename
caae2f7 lib: sbi: fwft: return SBI_EINVAL rather than SBI_ERR_INVALID_PARAM
e8717d1 lib: sbi: fwft: check feature value to be exactly 1 or 0
ecef14d lib: sbi: implement SBI FWFT extension
e9ee967 lib: sbi: fwft: add support for SBI_FWFT_PTE_AD_HW_UPDATING
c97a1d5 lib: sbi: fwft: add support for SBI_FWFT_MISALIGNED_EXC_DELEG
aa5a859 lib: sbi: add support for firmware features extension
53844c9 lib: sbi: Add support for Svade and Svadu extensions
52dcf35 platform: generic: andes: Add support for RV32 to set up PMA
f09f164 platform: generic: andes: Refine Andes PMA related code
7830e98 lib: serial: fix RX path in litex-uart
62e178a lib: utils/reset: Try initializing all reset devices in dt
3a94a32 sbi: sbi_domain_context: Fix trap context for domain context switching
a73ff04 lib: utils/reset: Fix fdt_reset to search for more dt nodes
b5c984b lib: utils/reset: Skip initialize reset when dt is not enabled
86bbe6c lib: utils/serial: Fix fdt_serial to match more dt nodes
179e00a lib: utils/serial: Skip initialize serial when dt is not enabled
b1c7c75 lib: utils/irqchip: Skip initialize irqchip when dt is not enabled
5e3ad7d lib: utils/timer: Skip initialize timer when dt is not enabled
c5be0e1 lib: utils/ipi: Skip initialize ipi when dt is not enabled
df3db6a lib: utils/fdt: Fix DT property for APLIC delegation
d962db2 lib: utils/gpio: respect flag GPIO_FLAG_ACTIVE_LOW
ae5ef18 lib: sbi: sse: handle missing writable attributes
858754a lib: utils/irqchip: Add sanity checks in imsic_get_data() and
imsic_get_target_file()
96f0a2e firmware: Bring back FW_TEXT_START as an optional parameter
e3a30a2 lib: utils/irqchip: Check before initializing imsic
2bed4c1 platform: generic: thead: add Sophgo CV18XX/SG200X series
533067d lib: sbi: Put event after use in sbi_sse_exit() loop
ea9cf6a utils/reset: Add SG2042 hwmon MCU support.
1cb792d lib: sbi: simplify inline function in sbi_dtbr.c
7b37da3 lib: sbi: fix return type of sbi_dbtr_shmem_disabled
e065c3c lib: sbi: Fixed memory permission check in sbi_dbtr_setup_shmem
7f54527 lib: sbi: fix DBTR_SHMEM_MAKE_PHYS for RV64
744f495 lib: sbi: Removal unnecessary check dbtr_thishart_state_ptr
4953bd7 lib: sbi: fix hart_shmem_base
019a8e6 platform: generic: thead: add Canaan Kendryte K230
33e21c9 platform: generic: thead: separate T-Head PMU Errata
2b93ce0 platform: andes: Change all occurrences of andes45 to andes
f68b3ae platform: andes: Rename files with the prefix andes45
17e8291 sbi: sbi_domain_context: Add spinlock for updating domain assigned_harts
1d89a9d lib: sbi: Refine the settings for switching to Virtual Supervisor Mode.
033104d lib: sbi: sse: check handler entry to belong to supervisor mode
bd00765 lib: sbi: sse: use PRV_S instead of hardcoded value for mode
ce3c82c lib: sbi: sse: call enable callback before sending IPI
d528dbf lib: sbi: sse: remove superfluous sbi_list_empty() check
22ff750 lib: sbi: sse: simplify 32bits overflow check
7aa80ea lib: sbi: sse: rename sse_hart_unlock() to sse_enabled_event_unlock()
c21c99d lib: sbi: sse: fix typos, comments and spacing errors
7b1ed96 lib: tests: Add test for spinlocks
7bdf41a lib: tests: Add test for atomic_t
f6243d9 lib: tests: Add test suite init function
d4d2582 firmware: remove FW_TEXT_START
73344d4 lib: utils: check correct value in fdt_node_offset_by_compatible
37e1544 lib: sbi: sse_event_get() may return NULL
68bc031 lib: sbi: Add missing sscrind and sscfg extensions in sbi_hart_ext[]
a7c5c2c Makefile: Remove unnecessary dependencies
268feab Makefile: Respect manual changes to .config
29ecda9 sbi: sbi_domain_context: Check privilege spec version before accessing
S-mode CSRs
7862c24 lib: sbi: Wakeup non-coldboot HARTs early in the coldboot path
beb0cd1 lib: sbi: Simplify wait_for_coldboot() implementation
f5375bc platform: generic: allwinner: Optimize current hart scratch access
b94396c lib: utils/timer: Optimize current hart scratch access
5c9a735 include: sbi: Support byteorder macros in assembly
06fc453 lib: sbi: Add SSE support for PMU events
09ad214 lib: sbi: Implement SBI SSE extension
c8cdf01 lib: sbi: Add support for Supervisor Software Events extension
76d7e9b firmware: remove copy-base relocation
5186da6 platform: generic: allwinner: sun20i-d1: Remove duplicated CSR
definitions
3b2f89e docs: writing_tests: Make docs correspond the latest changes
f7d0050 lib: sbi: Extend sbi_trap_error() to dump state in a nested trap
5b11f16 lib: sbi: Pass trap context pointer to sbi_ecall_handler()
43d346c lib: sbi: Remove regs parameter from trap irq handling functions
d84e7eb lib: sbi: Remove regs paramter of sbi_irqchip_process()
f414cf9 lib: sbi: Simplify parameters of sbi_illegal_insn_handler()
fea33a9 lib: sbi: Simplify parameters of misaligned and access fault handlers
abea949 lib: sbi: Introduce trap context
60ffc15 include: sbi: Add trap_context pointer in struct sbi_scratch
ebb697a lib: sbi: Remove sbi_trap_exit() and related code
2e85178 lib: sbi: Remove epc from struct sbi_trap_info
86224ec docs/writing_tests: Update tests paths
5c992a1 lib: tests: Move tests to a separate directory
81e3ba7 lib: sbi: call platform load/store emulators
ddf3b64 include: sbi: add emulate_load/store handler to platform ops
4c11265 lib: sbi: abstract out insn decoding to unify mem fault handlers
9221fe5 lib: sbi: change prototype of sbi_misaligned_load/store_handler
a17600c lib: sbi: change prototype of sbi_trap_redirect
2471cf2 include: sbi: rename sbi_misaligned_ldst.h to sbi_trap_ldst.h
c0a6320 lib: sbi: rename sbi_misaligned_ldst.c to sbi_trap_ldst.c
e11025c lib: sbi: Add initial domain context management support
87d8fe7 lib: tests: Add sbi_console test
e5f53fd lib: tests: Add a test for sbi_bitmap
874fcef lib: Add SBIUnit testing macros and functions
b9e4de0 docs: Add documentation about tests and SBIUnit
526b9ce firmware: fw_base.S: fix _reset_regs
8151105 firmware: fw_base.S: Remove _relocate_lottery
187397f firmware: fw_dynamic.S: Remove _bad_dynamic_info
b27b7c6 firmware: fw_base: Simplified setup trap handler
fdf5589 firmware: fw_base.S: Simplify address get
748bef1 lib: sbi_misaligned_ldst: Add handling of C.LHU/C.LH and C.SH
bc36678 platform: andes: Drop andes_pmu_setup()
6bb6b61 lib: sbi: Add support for smcsrind and smcdeleg
322b598 lib: sbi_hsm: Restor hart state to stop when fails to start
96a35db docs/firmware: document new options for jump and payload firmwares
2cff7f3 platform: Apply relocatable address
f056939 firmware: Add relocatable FW_PAYLOAD_FDT_ADDR
7227cdd firmware: Add relocatable FW_JUMP_ADDR and FW_JUMP_FDT_ADDR
741e941 platform: starfive: call starfive_jh7110_inst_init() in pm_reset_init()
3edf044 platform: starfive: return error if needed devices are not present
80ae046 platform: starfive: rename "stf,axp15060-regulator" ->
"x-powers,axp15060"
5335340 platform: starfive: remove redundant compatibility check in pmic_ops
4d8569d platform: starfive: get I2C offset address from clocks property
034af1f platform: starfive: correct system clock device tree node
88273fe lib: sbi_pmu: Before using we should ensure PMU init done
46c8c65 docs: move documentation of system suspend test.
8df836d platform: generic: Parse system suspend test from config node.
23e7e48 docs: Add OpenSBI DT configuration guide.
67ce5a7 platform: generic: Add support for specify coldboot harts in DT
9c8b18e firmware: fw_base.S: remove _runtime_offset
4c6b7cb firmware: fw_base.S: Improve loading u32
92e8aff firmware: always create dynsym section
d1dad07 Makefile: check for --exclude-libs
4a76f79 Makefile: don't pass -mstrict-align if not supported
21caaa3 fw_base.S: Fix comment errors
1ec353d lib: sbi: Use mask to check the free bit during trigger allocation
bb90a9e lib: sbi: Print number of debug triggers found
76a2a15 lib: sbi: Implement SBI debug trigger extension
fa87ec9 include: sbi: Add SBI debug trigger extension related defines
97f234f lib: sbi: Introduce the SBI debug triggers extension support
40dac6b lib: sbi: Detect support of debug triggers
2499769 include: sbi: Introduce debug trigger register encodings
20ca19a include: sbi: Add TINFO debug trigger CSR
b752099 include: sbi: Introduce common endianess conversion macro
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240715171521.179517-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 0d9f1016d43302108d33d1268304a06cc3fb2021
https://github.com/qemu/qemu/commit/0d9f1016d43302108d33d1268304a06cc3fb2021
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-07-18 (Thu, 18 Jul 2024)
Changed paths:
M disas/riscv.c
M docs/about/deprecated.rst
M hw/riscv/virt.c
M pc-bios/opensbi-riscv32-generic-fw_dynamic.bin
M pc-bios/opensbi-riscv64-generic-fw_dynamic.bin
M roms/opensbi
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
M target/riscv/cpu_cfg.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/insn16.decode
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rva.c.inc
M target/riscv/insn_trans/trans_rvd.c.inc
M target/riscv/insn_trans/trans_rvf.c.inc
M target/riscv/insn_trans/trans_rvi.c.inc
A target/riscv/insn_trans/trans_rvzabha.c.inc
M target/riscv/insn_trans/trans_rvzacas.c.inc
A target/riscv/insn_trans/trans_rvzcmop.c.inc
A target/riscv/insn_trans/trans_rvzimop.c.inc
M target/riscv/kvm/kvm-cpu.c
M target/riscv/machine.c
M target/riscv/op_helper.c
M target/riscv/pmu.c
M target/riscv/pmu.h
M target/riscv/tcg/tcg-cpu.c
M target/riscv/translate.c
Log Message:
-----------
Merge tag 'pull-riscv-to-apply-20240718-1' of
https://github.com/alistair23/qemu into staging
RISC-V PR for 9.1
* Support the zimop, zcmop, zama16b and zabha extensions
* Validate the mode when setting vstvec CSR
* Add decode support for Zawrs extension
* Update the KVM regs to Linux 6.10-rc5
* Add smcntrpmf extension support
* Raise an exception when CSRRS/CSRRC writes a read-only CSR
* Re-insert and deprecate 'riscv,delegate' in virt machine device tree
* roms/opensbi: Update to v1.5
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# =pM6B
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 18 Jul 2024 12:09:11 PM AEST
# gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013
* tag 'pull-riscv-to-apply-20240718-1' of https://github.com/alistair23/qemu:
(30 commits)
roms/opensbi: Update to v1.5
hw/riscv/virt.c: re-insert and deprecate 'riscv,delegate'
target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
target/riscv: Expose the Smcntrpmf config
target/riscv: Do not setup pmu timer if OF is disabled
target/riscv: More accurately model priv mode filtering.
target/riscv: Start counters from both mhpmcounter and mcountinhibit
target/riscv: Enforce WARL behavior for scounteren/hcounteren
target/riscv: Save counter values during countinhibit update
target/riscv: Implement privilege mode filtering for cycle/instret
target/riscv: Only set INH fields if priv mode is available
target/riscv: Add cycle & instret privilege mode filtering support
target/riscv: Add cycle & instret privilege mode filtering definitions
target/riscv: Add cycle & instret privilege mode filtering properties
target/riscv: Fix the predicate functions for mhpmeventhX CSRs
target/riscv: Combine set_mode and set_virt functions.
target/riscv/kvm: update KVM regs to Linux 6.10-rc5
disas/riscv: Add decode for Zawrs extension
target/riscv: Validate the mode in write_vstvec
disas/riscv: Support zabha disassemble
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/d74ec4d7dda6...0d9f1016d433
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- [Qemu-commits] [qemu/qemu] 6eab27: target/riscv: Add zimop extension,
Richard Henderson <=