[Qemu-commits] [qemu/qemu] 13951c: aspeed/smc: Fix possible integer overflow

[Richard Henderson]

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 13951ccfcdf0f31902a93859506ccf8c0ef66583
      
https://github.com/qemu/qemu/commit/13951ccfcdf0f31902a93859506ccf8c0ef66583
  Author: Cédric Le Goater <clg@redhat.com>
  Date:   2024-07-21 (Sun, 21 Jul 2024)

  Changed paths:
    M hw/ssi/aspeed_smc.c

  Log Message:
  -----------
  aspeed/smc: Fix possible integer overflow

Coverity reports a possible integer overflow because routine
aspeeed_smc_hclk_divisor() has a codepath returning 0, which could
lead to an integer overflow when computing variable 'hclk_shift' in
the caller aspeed_smc_dma_calibration().

The value passed to aspeed_smc_hclk_divisor() is always between 0 and
15 and, in this case, there is always a matching hclk divisor. Remove
the return 0 and use g_assert_not_reached() instead.

Fixes: Coverity CID 1547822
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: dddfc771e034887560c30fd2720b7798c04f5642
      
https://github.com/qemu/qemu/commit/dddfc771e034887560c30fd2720b7798c04f5642
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2024-07-21 (Sun, 21 Jul 2024)

  Changed paths:
    M hw/arm/aspeed.c

  Log Message:
  -----------
  aspeed: Change type of eMMC device

The QEMU device model representing the eMMC device of the machine is
currently created with type SD_CARD. Change the type to EMMC now that
it is available.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Tested-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>


  Commit: 255aed8134190966d0bd090c97391f6512c2fbc6
      
https://github.com/qemu/qemu/commit/255aed8134190966d0bd090c97391f6512c2fbc6
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2024-07-21 (Sun, 21 Jul 2024)

  Changed paths:
    M hw/arm/aspeed.c

  Log Message:
  -----------
  aspeed: Load eMMC first boot area as a boot rom

The first boot area partition (64K) of the eMMC device should contain
an initial boot loader (u-boot SPL). Load it as a ROM only if an eMMC
device is available to boot from but no flash device is.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Tested-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>


  Commit: cc8bae6f6270c52c8f9854a83f9cefec3e5ec108
      
https://github.com/qemu/qemu/commit/cc8bae6f6270c52c8f9854a83f9cefec3e5ec108
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2024-07-21 (Sun, 21 Jul 2024)

  Changed paths:
    M include/hw/misc/aspeed_scu.h

  Log Message:
  -----------
  aspeed/scu: Add boot-from-eMMC HW strapping bit for AST2600 SoC

Bit SCU500[2] of the AST2600 controls the boot device of the SoC.

Future changes will configure this bit to boot from eMMC disk images
specially built for this purpose.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Tested-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>


  Commit: eea55625df839813c66c5e2e8f41d9131d591f6c
      
https://github.com/qemu/qemu/commit/eea55625df839813c66c5e2e8f41d9131d591f6c
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2024-07-21 (Sun, 21 Jul 2024)

  Changed paths:
    M hw/arm/aspeed_ast2600.c
    M hw/arm/aspeed_soc_common.c
    M include/hw/arm/aspeed_soc.h

  Log Message:
  -----------
  aspeed: Introduce a AspeedSoCClass 'boot_from_emmc' handler

Report support on the AST2600 SoC if the boot-from-eMMC HW strapping
bit is set at the board level. AST2700 also has support but it is not
yet ready in QEMU and others SoCs do not have support, so return false
always for these.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Tested-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>


  Commit: e554e45b447880e37538d300ac6e12111788ac4f
      
https://github.com/qemu/qemu/commit/e554e45b447880e37538d300ac6e12111788ac4f
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2024-07-21 (Sun, 21 Jul 2024)

  Changed paths:
    M hw/arm/aspeed.c

  Log Message:
  -----------
  aspeed: Tune eMMC device properties to reflect HW strapping

When the boot-from-eMMC HW strapping bit is set, use the 'boot-config'
property to set the boot config register to boot from the first boot
area partition of the eMMC device. Also set the boot partition size
of the device.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Tested-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>


  Commit: 01ea09eb7a6e8369a98fb360d2ed3bf1ecfc1753
      
https://github.com/qemu/qemu/commit/01ea09eb7a6e8369a98fb360d2ed3bf1ecfc1753
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2024-07-21 (Sun, 21 Jul 2024)

  Changed paths:
    M hw/arm/aspeed.c

  Log Message:
  -----------
  aspeed: Add boot-from-eMMC HW strapping bit to rainier-bmc machine

This value is taken from a running Rainier machine.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Tested-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>


  Commit: 621845a9e38215977432cff8c946b78f6820c6b5
      
https://github.com/qemu/qemu/commit/621845a9e38215977432cff8c946b78f6820c6b5
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2024-07-21 (Sun, 21 Jul 2024)

  Changed paths:
    M hw/arm/aspeed.c

  Log Message:
  -----------
  aspeed: Introduce a 'hw_strap1' machine attribute

To change default behavior of a machine and boot from eMMC, future
changes will add a machine option to let the user configure the
boot-from-eMMC HW strapping bit. Add a new machine attribute first.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Tested-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>


  Commit: 056b779eaf10ab84e8ca9d02662a975f4de3d3b1
      
https://github.com/qemu/qemu/commit/056b779eaf10ab84e8ca9d02662a975f4de3d3b1
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2024-07-21 (Sun, 21 Jul 2024)

  Changed paths:
    M docs/system/arm/aspeed.rst
    M hw/arm/aspeed.c

  Log Message:
  -----------
  aspeed: Introduce a 'boot-emmc' machine option

The default behavior of some Aspeed machines is to boot from the eMMC
device, like the rainier-bmc. Others like ast2600-evb could also boot
from eMMC if the HW strapping boot-from-eMMC bit was set. Add a
property to set or unset this bit. This is useful to test boot images.

For now, only activate this property on the ast2600-evb and rainier-bmc
machines for which eMMC images are available or can be built.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Tested-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>


  Commit: a82e7e9eca7396ca39b0eb07d52e58d406d15728
      
https://github.com/qemu/qemu/commit/a82e7e9eca7396ca39b0eb07d52e58d406d15728
  Author: Cédric Le Goater <clg@redhat.com>
  Date:   2024-07-21 (Sun, 21 Jul 2024)

  Changed paths:
    M tests/avocado/machine_aspeed.py

  Log Message:
  -----------
  tests/avocado/machine_aspeed.py: Add eMMC boot tests

The image was built using the process described in commit c8cb19876d3e
("hw/sd/sdcard: Support boot area in emmc image") with artefacts from
the latest successful build of the IBM P10 BMC platform available on:

  
https://jenkins.openbmc.org/job/ci-openbmc/distro=ubuntu,label=docker-builder,target=p10bmc/lastSuccessfulBuild/

Signed-off-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>


  Commit: 13b5ae94ed4d03d4992af867d0edb075651a4da9
      
https://github.com/qemu/qemu/commit/13b5ae94ed4d03d4992af867d0edb075651a4da9
  Author: Jamin Lin <jamin_lin@aspeedtech.com>
  Date:   2024-07-21 (Sun, 21 Jul 2024)

  Changed paths:
    M hw/adc/aspeed_adc.c
    M include/hw/adc/aspeed_adc.h

  Log Message:
  -----------
  aspeed/adc: Add AST2700 support

AST2700 and AST2600 ADC controllers are identical.
Introduce ast2700 class and set 2 engines.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>


  Commit: 11bea810f7c1215e36824ed291a64e8f4e6f28df
      
https://github.com/qemu/qemu/commit/11bea810f7c1215e36824ed291a64e8f4e6f28df
  Author: Jamin Lin <jamin_lin@aspeedtech.com>
  Date:   2024-07-21 (Sun, 21 Jul 2024)

  Changed paths:
    M hw/arm/aspeed_ast27x0.c

  Log Message:
  -----------
  aspeed/soc: support ADC for AST2700

Add ADC model for AST2700 ADC support.
The ADC controller registers base address is start at
0x14C0_0000 and its address space is 0x1000.
The ADC controller interrupt is connected to
GICINT130_INTC group at bit 16. The GIC IRQ is 130.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>


  Commit: f2202be27852eeb18d05ee6cebaba6f09ea74e55
      
https://github.com/qemu/qemu/commit/f2202be27852eeb18d05ee6cebaba6f09ea74e55
  Author: Jamin Lin <jamin_lin@aspeedtech.com>
  Date:   2024-07-21 (Sun, 21 Jul 2024)

  Changed paths:
    M hw/i2c/aspeed_i2c.c
    M include/hw/i2c/aspeed_i2c.h

  Log Message:
  -----------
  hw/i2c/aspeed: support to set the different memory size

According to the datasheet of ASPEED SOCs,
an I2C controller owns 8KB of register space for AST2700,
owns 4KB of register space for AST2600, AST2500 and AST2400,
and owns 64KB of register space for AST1030.

It set the memory region size 4KB by default and it does not compatible
register space for AST2700.

Introduce a new class attribute to set the I2C controller memory size
for different ASPEED SOCs.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>


  Commit: 5d337540c417997b589d71020497e0c127d1c4e1
      
https://github.com/qemu/qemu/commit/5d337540c417997b589d71020497e0c127d1c4e1
  Author: Jamin Lin <jamin_lin@aspeedtech.com>
  Date:   2024-07-21 (Sun, 21 Jul 2024)

  Changed paths:
    M hw/i2c/aspeed_i2c.c
    M include/hw/i2c/aspeed_i2c.h

  Log Message:
  -----------
  hw/i2c/aspeed: rename the I2C class pool attribute to share_pool

According to the datasheet of ASPEED SOCs,
each I2C bus has their own pool buffer since AST2500.

Only AST2400 utilized a pool buffer share to all I2C bus.
And firmware required to set the offset of pool buffer
by writing "Function Control Register(I2CD 00)"

To make this model more readable, will change to introduce
a new bus pool buffer attribute in AspeedI2Cbus.
So, it does not need to calculate the pool buffer offset
for different I2C bus.

This patch rename the I2C class pool attribute to share_pool.
It make user more understand share pool and bus pool
are different.

Incrementing the version of aspeed_i2c_vmstate to 3.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>


  Commit: 4db1c16441923fc152142ae4bcc1cba23064cb8b
      
https://github.com/qemu/qemu/commit/4db1c16441923fc152142ae4bcc1cba23064cb8b
  Author: Jamin Lin <jamin_lin@aspeedtech.com>
  Date:   2024-07-21 (Sun, 21 Jul 2024)

  Changed paths:
    M hw/arm/aspeed.c

  Log Message:
  -----------
  aspeed: fix coding style

Fix coding style issues from checkpatch.pl

Test command:
./scripts/checkpatch.pl --no-tree -f hw/arm/aspeed.c

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>


  Commit: a7ddb48bd1363c8bcdf42776d320289c42191f01
      
https://github.com/qemu/qemu/commit/a7ddb48bd1363c8bcdf42776d320289c42191f01
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-07-22 (Mon, 22 Jul 2024)

  Changed paths:
    M docs/system/arm/aspeed.rst
    M hw/adc/aspeed_adc.c
    M hw/arm/aspeed.c
    M hw/arm/aspeed_ast2600.c
    M hw/arm/aspeed_ast27x0.c
    M hw/arm/aspeed_soc_common.c
    M hw/i2c/aspeed_i2c.c
    M hw/ssi/aspeed_smc.c
    M include/hw/adc/aspeed_adc.h
    M include/hw/arm/aspeed_soc.h
    M include/hw/i2c/aspeed_i2c.h
    M include/hw/misc/aspeed_scu.h
    M tests/avocado/machine_aspeed.py

  Log Message:
  -----------
  Merge tag 'pull-aspeed-20240721' of https://github.com/legoater/qemu into 
staging

aspeed queue:

* SMC model fix (Coverity)
* AST2600 boot for eMMC support and test
* AST2700 ADC model
* I2C model changes preparing AST2700 I2C support

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# gpg: Signature made Sun 21 Jul 2024 06:07:48 PM AEST
# gpg:                using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
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# Primary key fingerprint: A0F6 6548 F048 95EB FE6B  0B60 51A3 43C7 CFFB ECA1

* tag 'pull-aspeed-20240721' of https://github.com/legoater/qemu:
  aspeed: fix coding style
  hw/i2c/aspeed: rename the I2C class pool attribute to share_pool
  hw/i2c/aspeed: support to set the different memory size
  aspeed/soc: support ADC for AST2700
  aspeed/adc: Add AST2700 support
  tests/avocado/machine_aspeed.py: Add eMMC boot tests
  aspeed: Introduce a 'boot-emmc' machine option
  aspeed: Introduce a 'hw_strap1' machine attribute
  aspeed: Add boot-from-eMMC HW strapping bit to rainier-bmc machine
  aspeed: Tune eMMC device properties to reflect HW strapping
  aspeed: Introduce a AspeedSoCClass 'boot_from_emmc' handler
  aspeed/scu: Add boot-from-eMMC HW strapping bit for AST2600 SoC
  aspeed: Load eMMC first boot area as a boot rom
  aspeed: Change type of eMMC device
  aspeed/smc: Fix possible integer overflow

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/a87a7c449e53...a7ddb48bd136

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