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[Qemu-commits] [qemu/qemu] 409b9e: tcg: Return TCGOp from tcg_gen_op[1-6
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 409b9e: tcg: Return TCGOp from tcg_gen_op[1-6] |
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Date: |
Fri, 27 Sep 2024 02:38:14 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 409b9e39bec1b43de982c4708832bac13d4a20ab
https://github.com/qemu/qemu/commit/409b9e39bec1b43de982c4708832bac13d4a20ab
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-09-22 (Sun, 22 Sep 2024)
Changed paths:
M tcg/tcg-internal.h
M tcg/tcg-op.c
Log Message:
-----------
tcg: Return TCGOp from tcg_gen_op[1-6]
TCGOp to be propagated further in the next patch.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 83ac625c2bb14cc2991adedc9ac4f3f9ab3b096d
https://github.com/qemu/qemu/commit/83ac625c2bb14cc2991adedc9ac4f3f9ab3b096d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-09-22 (Sun, 22 Sep 2024)
Changed paths:
M tcg/tcg-op.c
Log Message:
-----------
tcg: Propagate new TCGOp to add_as_label_use
The use of tcg_last_op does not interact well with
TCGContext.emit_before_op, resulting in the label
being linked to something other than the branch op.
In this case it is easier to simply collect the emitted
branch op and pass it directly to add_as_label_use.
Reported-by: Elisha Hollander <just4now666666@gmail.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 9d8d5a5b9078a16b4c0862fe54248c5cc8435648
https://github.com/qemu/qemu/commit/9d8d5a5b9078a16b4c0862fe54248c5cc8435648
Author: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Date: 2024-09-22 (Sun, 22 Sep 2024)
Changed paths:
M tcg/tcg-op-gvec.c
Log Message:
-----------
tcg: Fix iteration step in 32-bit gvec operation
The loop in the 32-bit case of the vector compare operation
was incorrectly incrementing by 8 bytes per iteration instead
of 4 bytes. This caused the function to process only half of
the intended elements.
Cc: qemu-stable@nongnu.org
Fixes: 9622c697d1 (tcg: Add gvec compare with immediate and scalar operand)
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240904142739.854-2-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 8dd2ea75154d406c1d6e5fed797eef522c293a86
https://github.com/qemu/qemu/commit/8dd2ea75154d406c1d6e5fed797eef522c293a86
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-09-22 (Sun, 22 Sep 2024)
Changed paths:
M tcg/tcg-internal.h
M tcg/tcg-op-vec.c
Log Message:
-----------
tcg: Export vec_gen_6
Add declaration to tcg-internal.h, making it available for
use from tcg backend vector expanders.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: bc97b3ad313baf01ff7800c472c2a6931ff71dfb
https://github.com/qemu/qemu/commit/bc97b3ad313baf01ff7800c472c2a6931ff71dfb
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-09-22 (Sun, 22 Sep 2024)
Changed paths:
M tcg/i386/tcg-target.c.inc
Log Message:
-----------
tcg/i386: Split out tcg_out_vex_modrm_type
Helper function to handle setting of VEXL based
on the type of the operation.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: b8a567039af94790b1994bac12238added097fea
https://github.com/qemu/qemu/commit/b8a567039af94790b1994bac12238added097fea
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-09-22 (Sun, 22 Sep 2024)
Changed paths:
M tcg/i386/tcg-target.c.inc
Log Message:
-----------
tcg/i386: Do not expand cmp_vec early
Move most of expansion to opcode generation, leaving the
conversion of unsigned to signed to be done in the early phase.
Small inefficiencies, but not incorrect results, are introduced
until cmpsel_vec is converted in the next patch.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: db4121d20715caa74c5863da64754bdf4baeeda6
https://github.com/qemu/qemu/commit/db4121d20715caa74c5863da64754bdf4baeeda6
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-09-22 (Sun, 22 Sep 2024)
Changed paths:
M tcg/i386/tcg-target-con-set.h
M tcg/i386/tcg-target.c.inc
M tcg/i386/tcg-target.h
M tcg/i386/tcg-target.opc.h
Log Message:
-----------
tcg/i386: Do not expand cmpsel_vec early
Expand during output instead of during opcode generation.
Remove x86_vpblendvb_vec opcode, this this removes the only user.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 2cd118ca4ada265cf5b3ceab807dda7a07437d43
https://github.com/qemu/qemu/commit/2cd118ca4ada265cf5b3ceab807dda7a07437d43
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-09-22 (Sun, 22 Sep 2024)
Changed paths:
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
tcg/ppc: Do not expand cmp_vec early
Move expansion to opcode generation.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: fcc54e7bf56ba627f9b6ac4a32c6b446d2591ccf
https://github.com/qemu/qemu/commit/fcc54e7bf56ba627f9b6ac4a32c6b446d2591ccf
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-09-22 (Sun, 22 Sep 2024)
Changed paths:
M tcg/s390x/tcg-target.c.inc
Log Message:
-----------
tcg/s390x: Do not expand cmp_vec early
Move expansion to opcode generation.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 141125e08cf422e22d40b0114a265c83d888767a
https://github.com/qemu/qemu/commit/141125e08cf422e22d40b0114a265c83d888767a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-09-22 (Sun, 22 Sep 2024)
Changed paths:
M tcg/optimize.c
Log Message:
-----------
tcg/optimize: Fold movcond with true and false values identical
Fold "x = cond ? y : y" to "x = y".
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 1f106544fd87fd12566c8c5e12251067e2bc9f78
https://github.com/qemu/qemu/commit/1f106544fd87fd12566c8c5e12251067e2bc9f78
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-09-22 (Sun, 22 Sep 2024)
Changed paths:
M tcg/optimize.c
Log Message:
-----------
tcg/optimize: Optimize cmp_vec and cmpsel_vec
Place immediate values second in the comparison.
Place destination matches first in the true/false values.
All of this mirrors what we do for integer setcond and movcond.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: e58b977238e3120cba3190e1107a111a44202a24
https://github.com/qemu/qemu/commit/e58b977238e3120cba3190e1107a111a44202a24
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-09-22 (Sun, 22 Sep 2024)
Changed paths:
M tcg/optimize.c
Log Message:
-----------
tcg/optimize: Optimize bitsel_vec
Fold matching true/false operands.
Fold true/false operands with 0/-1 to simpler logicals.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: d8387f0ee0862985dc481db1fca78dced54e183a
https://github.com/qemu/qemu/commit/d8387f0ee0862985dc481db1fca78dced54e183a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-09-22 (Sun, 22 Sep 2024)
Changed paths:
M tcg/i386/tcg-target-con-set.h
M tcg/i386/tcg-target-con-str.h
M tcg/i386/tcg-target.c.inc
Log Message:
-----------
tcg/i386: Optimize cmpsel with constant 0 operand 3.
These can be simplified to and/andc, avoiding the load of
the zero into a register.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 717da87d38937e0573aeb5b9c24e3e296a24fab8
https://github.com/qemu/qemu/commit/717da87d38937e0573aeb5b9c24e3e296a24fab8
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-09-22 (Sun, 22 Sep 2024)
Changed paths:
M tcg/i386/tcg-target.c.inc
Log Message:
-----------
tcg/i386: Implement cmp_vec with avx512 insns
The sse/avx instruction set only has EQ and GT as direct comparisons.
Other signed comparisons can be generated from swapping and inversion.
However unsigned comparisons are not available and must be transformed
to signed comparisons by biasing the inputs.
The avx512 instruction set has a complete set of comparisons, with
results placed into a predicate register. We can produce the normal
cmp_vec result by using VPMOVM2*.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: c044ec0d85cd94d1a986297c2e1f228408dddd76
https://github.com/qemu/qemu/commit/c044ec0d85cd94d1a986297c2e1f228408dddd76
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-09-22 (Sun, 22 Sep 2024)
Changed paths:
M tcg/i386/tcg-target.c.inc
Log Message:
-----------
tcg/i386: Add predicate parameters to tcg_out_evex_opc
Extend tcg_out_evex_opc to handle the predicate and
zero-merging parameters of the evex prefix.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: d58967490238f8d4c941102ade649314785d3f48
https://github.com/qemu/qemu/commit/d58967490238f8d4c941102ade649314785d3f48
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-09-22 (Sun, 22 Sep 2024)
Changed paths:
M tcg/i386/tcg-target.c.inc
Log Message:
-----------
tcg/i386: Implement cmpsel_vec with avx512 insns
The avx512 vpblendm* instructions exactly implement cmpsel,
using a predicate input. Of course this matches nicely with
the avx512 predicate comparison instructions.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 782cffa4ce00f447e662fa377aebf9cfb19b016b
https://github.com/qemu/qemu/commit/782cffa4ce00f447e662fa377aebf9cfb19b016b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-09-22 (Sun, 22 Sep 2024)
Changed paths:
M tcg/i386/tcg-target.c.inc
M tcg/i386/tcg-target.h
Log Message:
-----------
tcg/i386: Implement vector TST{EQ,NE} for avx512
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: d0dabf9ec5bc8d4252cc7f166c28542a492eaaad
https://github.com/qemu/qemu/commit/d0dabf9ec5bc8d4252cc7f166c28542a492eaaad
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-09-22 (Sun, 22 Sep 2024)
Changed paths:
M tcg/ppc/tcg-target-con-set.h
M tcg/ppc/tcg-target.c.inc
M tcg/ppc/tcg-target.h
Log Message:
-----------
tcg/ppc: Implement cmpsel_vec
Do not allow cmpsel_vec to be expanded early, so that we can
make the correct decision wrt the sense of the comparison.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: ce8e5f2f2f585fbbf507d96477b7dd75bf9182eb
https://github.com/qemu/qemu/commit/ce8e5f2f2f585fbbf507d96477b7dd75bf9182eb
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-09-22 (Sun, 22 Sep 2024)
Changed paths:
M tcg/ppc/tcg-target-con-set.h
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
tcg/ppc: Optimize cmpsel with constant 0/-1 arguments
These can be simplified to and/or/andc/orc,
avoiding the load of the constantinto a register.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 1c7d05ff70f09367ab8b519cbbb69dd5491f85f1
https://github.com/qemu/qemu/commit/1c7d05ff70f09367ab8b519cbbb69dd5491f85f1
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-09-22 (Sun, 22 Sep 2024)
Changed paths:
M tcg/s390x/tcg-target-con-set.h
M tcg/s390x/tcg-target.c.inc
M tcg/s390x/tcg-target.h
Log Message:
-----------
tcg/s390x: Implement cmpsel_vec
Do not allow cmpsel_vec to be expanded early, so that we can
make the correct decision wrt the sense of the comparison.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 50695fb83e22ad011708b738d24c6c67d6296aaa
https://github.com/qemu/qemu/commit/50695fb83e22ad011708b738d24c6c67d6296aaa
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-09-22 (Sun, 22 Sep 2024)
Changed paths:
M tcg/s390x/tcg-target-con-set.h
M tcg/s390x/tcg-target-con-str.h
M tcg/s390x/tcg-target.c.inc
Log Message:
-----------
tcg/s390x: Optimize cmpsel with constant 0/-1 arguments
These can be simplified to and/or/andc/orc,
avoiding the load of the constantinto a register.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 8bded2e73e80823a67f730140788a3c5e60bf4b5
https://github.com/qemu/qemu/commit/8bded2e73e80823a67f730140788a3c5e60bf4b5
Author: Fabiano Rosas <farosas@suse.de>
Date: 2024-09-22 (Sun, 22 Sep 2024)
Changed paths:
M target/ppc/translate/vsx-impl.c.inc
Log Message:
-----------
target/ppc: Fix lxvx/stxvx facility check
The XT check for the lxvx/stxvx instructions is currently
inverted. This was introduced during the move to decodetree.
>From the ISA:
Chapter 7. Vector-Scalar Extension Facility
Load VSX Vector Indexed X-form
lxvx XT,RA,RB
if TX=0 & MSR.VSX=0 then VSX_Unavailable()
if TX=1 & MSR.VEC=0 then Vector_Unavailable()
...
Let XT be the value 32×TX + T.
The code currently does the opposite:
if (paired || a->rt >= 32) {
REQUIRE_VSX(ctx);
} else {
REQUIRE_VECTOR(ctx);
}
This was already fixed for lxv/stxv at commit "2cc0e449d1 (target/ppc:
Fix lxv/stxv MSR facility check)", but the indexed forms were missed.
Cc: qemu-stable@nongnu.org
Fixes: 70426b5bb7 ("target/ppc: moved stxvx and lxvx from legacy to decodtree")
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Claudio Fontana <cfontana@suse.de>
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Message-ID: <20240911141651.6914-1-farosas@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 3f89ff9b60c3edc8e20a3909060ddcde0358eaa6
https://github.com/qemu/qemu/commit/3f89ff9b60c3edc8e20a3909060ddcde0358eaa6
Author: Laurent Vivier <laurent@vivier.eu>
Date: 2024-09-22 (Sun, 22 Sep 2024)
Changed paths:
M linux-user/aarch64/syscall_nr.h
M linux-user/hexagon/syscall_nr.h
M linux-user/loongarch64/syscall_nr.h
M linux-user/openrisc/syscall_nr.h
M linux-user/riscv/syscall32_nr.h
M linux-user/riscv/syscall64_nr.h
Log Message:
-----------
linux-user: update syscall_nr.h to Linux v6.10
Automatically generated using scripts/gensyscalls.sh
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Brian Cain <bcain@quicinc.com>
Message-ID: <20240918074256.720617-2-laurent@vivier.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: c0d3050d276f3a48a6648ce4eeffc246f94b344d
https://github.com/qemu/qemu/commit/c0d3050d276f3a48a6648ce4eeffc246f94b344d
Author: Laurent Vivier <laurent@vivier.eu>
Date: 2024-09-22 (Sun, 22 Sep 2024)
Changed paths:
M linux-user/mips/syscall-args-o32.c.inc
Log Message:
-----------
linux-user, mips: update syscall-args-o32.c.inc to Linux v6.10
Updated running scripts/update-mips-syscall-args.sh
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Message-ID: <20240918074256.720617-3-laurent@vivier.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: e12fbc36f92acc556ac03ae6497e7ac9db309c84
https://github.com/qemu/qemu/commit/e12fbc36f92acc556ac03ae6497e7ac9db309c84
Author: Laurent Vivier <laurent@vivier.eu>
Date: 2024-09-22 (Sun, 22 Sep 2024)
Changed paths:
M linux-user/alpha/syscall.tbl
M linux-user/arm/syscall.tbl
M linux-user/hppa/syscall.tbl
M linux-user/i386/syscall_32.tbl
M linux-user/m68k/syscall.tbl
M linux-user/microblaze/syscall.tbl
M linux-user/mips/syscall_o32.tbl
M linux-user/mips64/syscall_n32.tbl
M linux-user/mips64/syscall_n64.tbl
M linux-user/ppc/syscall.tbl
M linux-user/s390x/syscall.tbl
M linux-user/sh4/syscall.tbl
M linux-user/sparc/syscall.tbl
M linux-user/x86_64/syscall_64.tbl
M linux-user/xtensa/syscall.tbl
Log Message:
-----------
linux-user: update syscall.tbl to Linux v6.10
Updated running scripts/update-syscalltbl.sh
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Message-ID: <20240918074256.720617-4-laurent@vivier.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: f5afe739a22839498774fb2e9b4d4bd47d968acf
https://github.com/qemu/qemu/commit/f5afe739a22839498774fb2e9b4d4bd47d968acf
Author: Laurent Vivier <laurent@vivier.eu>
Date: 2024-09-22 (Sun, 22 Sep 2024)
Changed paths:
M configs/targets/aarch64-linux-user.mak
M configs/targets/aarch64_be-linux-user.mak
M linux-user/aarch64/meson.build
A linux-user/aarch64/syscall_64.tbl
M linux-user/aarch64/syscall_nr.h
A linux-user/aarch64/syscallhdr.sh
M scripts/gensyscalls.sh
M scripts/update-syscalltbl.sh
Log Message:
-----------
linux-user,aarch64: move to syscalltbl file
Since kernel v6.11 aarch64 has moved from syscall_nr.h file
to syscall_64.tbl (See e632bca07c8e ("arm64: generate 64-bit
syscall.tbl"))
Update linux-user scripts to be able to retrieve syscall numbers
from linux syscall_64.tbl instead of syscall_nr.h.
New syscall_64.tbl is imported from linux v6.11 using
updated scripts/update-syscalltbl.sh
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Message-ID: <20240920151034.859533-2-laurent@vivier.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 656a46fbdab7db025dc372ea27660b4d657ee910
https://github.com/qemu/qemu/commit/656a46fbdab7db025dc372ea27660b4d657ee910
Author: Laurent Vivier <laurent@vivier.eu>
Date: 2024-09-22 (Sun, 22 Sep 2024)
Changed paths:
M configs/targets/or1k-linux-user.mak
M linux-user/meson.build
A linux-user/openrisc/meson.build
A linux-user/openrisc/syscall.tbl
R linux-user/openrisc/syscall_nr.h
A linux-user/openrisc/syscallhdr.sh
M scripts/gensyscalls.sh
M scripts/update-syscalltbl.sh
Log Message:
-----------
linux-user,openrisc: move to syscalltbl file
Since kernel v6.11 openrisc has moved from syscall_nr.h file
to syscall.tbl (See 77122bf9e3df ("openrisc: convert to generic syscall
table"))
Update linux-user scripts to be able to retrieve syscall numbers
from linux syscall.tbl instead of syscall_nr.h.
New syscall.tbl is imported from linux v6.11 using updated
scripts/update-syscalltbl.sh
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Message-ID: <20240920151034.859533-3-laurent@vivier.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 5281a1975c4fa4be87e76b2f77b14eb3e9432a0e
https://github.com/qemu/qemu/commit/5281a1975c4fa4be87e76b2f77b14eb3e9432a0e
Author: Laurent Vivier <laurent@vivier.eu>
Date: 2024-09-22 (Sun, 22 Sep 2024)
Changed paths:
M configs/targets/riscv32-linux-user.mak
M configs/targets/riscv64-linux-user.mak
M linux-user/riscv/cpu_loop.c
M linux-user/riscv/meson.build
A linux-user/riscv/syscall.tbl
R linux-user/riscv/syscall32_nr.h
R linux-user/riscv/syscall64_nr.h
R linux-user/riscv/syscall_nr.h
A linux-user/riscv/syscallhdr.sh
M scripts/gensyscalls.sh
M scripts/update-syscalltbl.sh
Log Message:
-----------
linux-user,riscv: move to syscalltbl file
Since kernel v6.11 riscv has moved from syscall_nr.h file
to syscall.tbl (3db80c999deb ("riscv: convert to generic syscall
table"))
Update linux-user scripts to be able to retrieve syscall numbers
from linux syscall.tbl instead of syscall_nr.h.
New syscall.tbl is imported from linux v6.11 using updated
scripts/update-syscalltbl.sh
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Message-ID: <20240920151034.859533-4-laurent@vivier.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: e7e6cc50219a8ba57fc3a8d34de5243bd83c69e4
https://github.com/qemu/qemu/commit/e7e6cc50219a8ba57fc3a8d34de5243bd83c69e4
Author: Laurent Vivier <laurent@vivier.eu>
Date: 2024-09-22 (Sun, 22 Sep 2024)
Changed paths:
M configs/targets/hexagon-linux-user.mak
A linux-user/hexagon/meson.build
A linux-user/hexagon/syscall.tbl
R linux-user/hexagon/syscall_nr.h
A linux-user/hexagon/syscallhdr.sh
M linux-user/meson.build
M scripts/gensyscalls.sh
M scripts/update-syscalltbl.sh
Log Message:
-----------
linux-user,hexagon: move to syscalltbl file
Since kernel v6.11 hexagon has moved from syscall_nr.h file
to syscall.tbl (36d69c29759e ("hexagon: use new system call table"))
Update linux-user scripts to be able to retrieve syscall numbers
from linux syscall.tbl instead of syscall_nr.h.
New syscall.tbl is imported from linux v6.11 using updated
scripts/update-syscalltbl.sh
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Message-ID: <20240920151034.859533-5-laurent@vivier.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: c52e405968341b1d10c618f23bdbb841e39f9255
https://github.com/qemu/qemu/commit/c52e405968341b1d10c618f23bdbb841e39f9255
Author: Laurent Vivier <laurent@vivier.eu>
Date: 2024-09-22 (Sun, 22 Sep 2024)
Changed paths:
M configs/targets/loongarch64-linux-user.mak
M linux-user/loongarch64/meson.build
A linux-user/loongarch64/syscall.tbl
R linux-user/loongarch64/syscall_nr.h
A linux-user/loongarch64/syscallhdr.sh
M linux-user/syscall_defs.h
R scripts/gensyscalls.sh
M scripts/update-syscalltbl.sh
Log Message:
-----------
linux-user,loongarch: move to syscalltbl file
Since kernel v6.11 loongarch has moved from syscall_nr.h file
to syscall.tbl (26a3b85bac08 ("loongarch: convert to generic syscall
table"))
Update linux-user scripts to be able to retrieve syscall numbers
from linux syscall.tbl instead of syscall_nr.h.
New syscall.tbl is imported from linux v6.11 using updated
scripts/update-syscalltbl.sh
Remove scripts/gensyscalls.sh that is now useless.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Message-ID: <20240920151034.859533-6-laurent@vivier.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: c4d80fa63e823dc8dbf094b29e39b6978a3073b6
https://github.com/qemu/qemu/commit/c4d80fa63e823dc8dbf094b29e39b6978a3073b6
Author: Laurent Vivier <laurent@vivier.eu>
Date: 2024-09-22 (Sun, 22 Sep 2024)
Changed paths:
M linux-user/arm/syscall.tbl
M linux-user/i386/syscall_32.tbl
M linux-user/x86_64/syscall_64.tbl
Log Message:
-----------
linux-user: update syscall.tbl to Linux v6.11
Updated running scripts/update-syscalltbl.sh
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Message-ID: <20240920151034.859533-7-laurent@vivier.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 4ae7d11b70a840eec7aa27269093b15d04ebc84e
https://github.com/qemu/qemu/commit/4ae7d11b70a840eec7aa27269093b15d04ebc84e
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-09-27 (Fri, 27 Sep 2024)
Changed paths:
M configs/targets/aarch64-linux-user.mak
M configs/targets/aarch64_be-linux-user.mak
M configs/targets/hexagon-linux-user.mak
M configs/targets/loongarch64-linux-user.mak
M configs/targets/or1k-linux-user.mak
M configs/targets/riscv32-linux-user.mak
M configs/targets/riscv64-linux-user.mak
M linux-user/aarch64/meson.build
A linux-user/aarch64/syscall_64.tbl
M linux-user/aarch64/syscall_nr.h
A linux-user/aarch64/syscallhdr.sh
M linux-user/alpha/syscall.tbl
M linux-user/arm/syscall.tbl
A linux-user/hexagon/meson.build
A linux-user/hexagon/syscall.tbl
R linux-user/hexagon/syscall_nr.h
A linux-user/hexagon/syscallhdr.sh
M linux-user/hppa/syscall.tbl
M linux-user/i386/syscall_32.tbl
M linux-user/loongarch64/meson.build
A linux-user/loongarch64/syscall.tbl
R linux-user/loongarch64/syscall_nr.h
A linux-user/loongarch64/syscallhdr.sh
M linux-user/m68k/syscall.tbl
M linux-user/meson.build
M linux-user/microblaze/syscall.tbl
M linux-user/mips/syscall-args-o32.c.inc
M linux-user/mips/syscall_o32.tbl
M linux-user/mips64/syscall_n32.tbl
M linux-user/mips64/syscall_n64.tbl
A linux-user/openrisc/meson.build
A linux-user/openrisc/syscall.tbl
R linux-user/openrisc/syscall_nr.h
A linux-user/openrisc/syscallhdr.sh
M linux-user/ppc/syscall.tbl
M linux-user/riscv/cpu_loop.c
M linux-user/riscv/meson.build
A linux-user/riscv/syscall.tbl
R linux-user/riscv/syscall32_nr.h
R linux-user/riscv/syscall64_nr.h
R linux-user/riscv/syscall_nr.h
A linux-user/riscv/syscallhdr.sh
M linux-user/s390x/syscall.tbl
M linux-user/sh4/syscall.tbl
M linux-user/sparc/syscall.tbl
M linux-user/syscall_defs.h
M linux-user/x86_64/syscall_64.tbl
M linux-user/xtensa/syscall.tbl
R scripts/gensyscalls.sh
M scripts/update-syscalltbl.sh
M target/ppc/translate/vsx-impl.c.inc
M tcg/i386/tcg-target-con-set.h
M tcg/i386/tcg-target-con-str.h
M tcg/i386/tcg-target.c.inc
M tcg/i386/tcg-target.h
M tcg/i386/tcg-target.opc.h
M tcg/optimize.c
M tcg/ppc/tcg-target-con-set.h
M tcg/ppc/tcg-target.c.inc
M tcg/ppc/tcg-target.h
M tcg/s390x/tcg-target-con-set.h
M tcg/s390x/tcg-target-con-str.h
M tcg/s390x/tcg-target.c.inc
M tcg/s390x/tcg-target.h
M tcg/tcg-internal.h
M tcg/tcg-op-gvec.c
M tcg/tcg-op-vec.c
M tcg/tcg-op.c
Log Message:
-----------
Merge tag 'pull-tcg-20240922' of https://gitlab.com/rth7680/qemu into staging
target/ppc: Fix lxvx/stxvx facility check
linux-user: update syscall_nr.h to Linux v6.10
linux-user: update syscall.tbl to Linux v6.11
tcg: Fix iteration step in 32-bit gvec operation
tcg: Propagate new TCGOp to add_as_label_use
tcg/*: Do not expand cmp_vec, cmpsel_vec early
tcg/optimize: Fold movcond with true and false values identical
tcg/optimize: Optimize cmp_vec and cmpsel_vec
tcg/optimize: Optimize bitsel_vec
tcg/i386: Optimize cmpsel with constant 0 operand 3.
tcg/i386: Implement cmp_vec with avx512 insns
tcg/i386: Implement cmpsel_vec with avx512 insns
tcg/i386: Implement vector TST{EQ,NE} for avx512
tcg/ppc: Implement cmpsel_vec and optimize with constant 0/-1 arguments
tcg/s390x: Implement cmpsel_vec and optimize with constant 0/-1 arguments
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# gpg: Signature made Sun 22 Sep 2024 13:00:02 BST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-tcg-20240922' of https://gitlab.com/rth7680/qemu: (31 commits)
linux-user: update syscall.tbl to Linux v6.11
linux-user,loongarch: move to syscalltbl file
linux-user,hexagon: move to syscalltbl file
linux-user,riscv: move to syscalltbl file
linux-user,openrisc: move to syscalltbl file
linux-user,aarch64: move to syscalltbl file
linux-user: update syscall.tbl to Linux v6.10
linux-user, mips: update syscall-args-o32.c.inc to Linux v6.10
linux-user: update syscall_nr.h to Linux v6.10
target/ppc: Fix lxvx/stxvx facility check
tcg/s390x: Optimize cmpsel with constant 0/-1 arguments
tcg/s390x: Implement cmpsel_vec
tcg/ppc: Optimize cmpsel with constant 0/-1 arguments
tcg/ppc: Implement cmpsel_vec
tcg/i386: Implement vector TST{EQ,NE} for avx512
tcg/i386: Implement cmpsel_vec with avx512 insns
tcg/i386: Add predicate parameters to tcg_out_evex_opc
tcg/i386: Implement cmp_vec with avx512 insns
tcg/i386: Optimize cmpsel with constant 0 operand 3.
tcg/optimize: Optimize bitsel_vec
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/e10cd93872c3...4ae7d11b70a8
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