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[Qemu-devel] [PATCH] sparc32: hw/slavio_misc.c sysctrl register is 32 bi
From: |
Robert Reif |
Subject: |
[Qemu-devel] [PATCH] sparc32: hw/slavio_misc.c sysctrl register is 32 bits |
Date: |
Sun, 04 Nov 2007 10:27:00 -0500 |
User-agent: |
Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.4.2) Gecko/20040308 |
The sysctrl register is actually 32 bits. Add code to access it as 32 bits.
Index: hw/slavio_misc.c
===================================================================
RCS file: /sources/qemu/qemu/hw/slavio_misc.c,v
retrieving revision 1.10
diff -p -u -r1.10 slavio_misc.c
--- hw/slavio_misc.c 6 Oct 2007 11:28:21 -0000 1.10
+++ hw/slavio_misc.c 4 Nov 2007 15:21:17 -0000
@@ -44,10 +44,12 @@ typedef struct MiscState {
qemu_irq irq;
uint8_t config;
uint8_t aux1, aux2;
- uint8_t diag, mctrl, sysctrl;
+ uint8_t diag, mctrl;
+ uint32_t sysctrl;
} MiscState;
#define MISC_SIZE 1
+#define SYSCTRL_SIZE 4
static void slavio_misc_update_irq(void *opaque)
{
@@ -116,13 +118,6 @@ static void slavio_misc_mem_writeb(void
MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff);
s->mctrl = val & 0xff;
break;
- case 0x1f00000:
- MISC_DPRINTF("Write system control %2.2x\n", val & 0xff);
- if (val & 1) {
- s->sysctrl = 0x2;
- qemu_system_reset_request();
- }
- break;
case 0xa000000:
MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);
cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
@@ -156,10 +151,6 @@ static uint32_t slavio_misc_mem_readb(vo
ret = s->mctrl;
MISC_DPRINTF("Read modem control %2.2x\n", ret);
break;
- case 0x1f00000:
- MISC_DPRINTF("Read system control %2.2x\n", ret);
- ret = s->sysctrl;
- break;
case 0xa000000:
MISC_DPRINTF("Read power management %2.2x\n", ret);
break;
@@ -178,6 +169,47 @@ static CPUWriteMemoryFunc *slavio_misc_m
slavio_misc_mem_writeb,
slavio_misc_mem_writeb,
};
+
+static uint32_t slavio_misc_mem_readl(void *opaque, target_phys_addr_t addr)
+{
+ MiscState *s = opaque;
+ uint32_t ret = 0;
+
+ switch (addr) {
+ case 0x1f00000:
+ MISC_DPRINTF("Read system control %08x\n", ret);
+ ret = s->sysctrl;
+ break;
+ }
+ return ret;
+}
+
+static void slavio_misc_mem_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
+{
+ MiscState *s = opaque;
+
+ switch (addr) {
+ case 0x1f00000:
+ MISC_DPRINTF("Write system control %08x\n", val);
+ if (val & 1) {
+ s->sysctrl = 0x2;
+ qemu_system_reset_request();
+ }
+ break;
+ }
+}
+
+static CPUReadMemoryFunc *slavio_misc_mem_read32[3] = {
+ slavio_misc_mem_readl,
+ slavio_misc_mem_readl,
+ slavio_misc_mem_readl,
+};
+
+static CPUWriteMemoryFunc *slavio_misc_mem_write32[3] = {
+ slavio_misc_mem_writel,
+ slavio_misc_mem_writel,
+ slavio_misc_mem_writel,
+};
static void slavio_misc_save(QEMUFile *f, void *opaque)
{
@@ -191,7 +223,7 @@ static void slavio_misc_save(QEMUFile *f
qemu_put_8s(f, &s->aux2);
qemu_put_8s(f, &s->diag);
qemu_put_8s(f, &s->mctrl);
- qemu_put_8s(f, &s->sysctrl);
+ qemu_put_be32s(f, &s->sysctrl);
}
static int slavio_misc_load(QEMUFile *f, void *opaque, int version_id)
@@ -208,20 +240,21 @@ static int slavio_misc_load(QEMUFile *f,
qemu_get_8s(f, &s->aux2);
qemu_get_8s(f, &s->diag);
qemu_get_8s(f, &s->mctrl);
- qemu_get_8s(f, &s->sysctrl);
+ qemu_get_be32s(f, &s->sysctrl);
return 0;
}
void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
qemu_irq irq)
{
- int slavio_misc_io_memory;
+ int slavio_misc_io_memory, slavio_misc_io_memory32;
MiscState *s;
s = qemu_mallocz(sizeof(MiscState));
if (!s)
return NULL;
+ /* 8 bit registers */
slavio_misc_io_memory = cpu_register_io_memory(0, slavio_misc_mem_read,
slavio_misc_mem_write, s);
// Slavio control
cpu_register_physical_memory(base + 0x1800000, MISC_SIZE,
@@ -238,12 +271,15 @@ void *slavio_misc_init(target_phys_addr_
// Modem control
cpu_register_physical_memory(base + 0x1b00000, MISC_SIZE,
slavio_misc_io_memory);
- // System control
- cpu_register_physical_memory(base + 0x1f00000, MISC_SIZE,
- slavio_misc_io_memory);
// Power management
cpu_register_physical_memory(power_base, MISC_SIZE, slavio_misc_io_memory);
+ /* 32 bit registers */
+ slavio_misc_io_memory32 = cpu_register_io_memory(0,
slavio_misc_mem_read32, slavio_misc_mem_write32, s);
+ // System control
+ cpu_register_physical_memory(base + 0x1f00000, SYSCTRL_SIZE,
+ slavio_misc_io_memory32);
+
s->irq = irq;
register_savevm("slavio_misc", base, 1, slavio_misc_save,
slavio_misc_load, s);
- [Qemu-devel] [PATCH] sparc32: hw/slavio_misc.c sysctrl register is 32 bits,
Robert Reif <=