commit ffcb0cc661325b87995ae62dcdefa448e0b7296a Author: Vladimir Prus
Date: Mon Dec 1 19:28:32 2008 +0300 SH: Implement FD bit * target-sh4/cpu.h (cpu_get_tb_cpu_state): Include SR's FD bit in the flags. * target-sh4/helper.h (raise_fpu_disable, raise_slot_fpu_disable): New helpers. * targets-sh4/op_helper.c (helper_raise_fpu_disable) (helper_raise_slot_fpu_disable): New. * target-sh4/translate.c (CHECK_NOT_DELAY_SLOT, CHECK_PRIVILEGED): Set PC to the right value. (CHECK_FPU_ENABLED): New. (_decode_opc): Use CHECK_FPU_ENABLED for FP instructions. diff --git a/target-sh4/translate.c b/target-sh4/translate.c index d6cfb7c..23a5d34 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -481,6 +481,15 @@ static void _decode_opc(DisasContext * ctx) #if 0 fprintf(stderr, "Translating opcode 0x%04x\n", ctx->opcode); #endif + + /* The 0xfffd instruction is underfined, so we don't want to + raise fpu disable exception on it. */ + if (((ctx->opcode & 0xf000) == 0xf000) + && (ctx->opcode != 0xfffd)) + { + CHECK_FPU_ENABLED + } + switch (ctx->opcode) { case 0x0019: /* div0u */ tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(SR_M | SR_Q | SR_T));