[Qemu-devel] [RFC] MIPS CP0 random register strategy

[Hervé Poussineau]

Hello,

MIPS TLBWR instruction asks the CPU to randomly overwrite a TLB entry by 
the one we want to write. The TLB index needs to be between number of 
wired TLB entries and TLB count - 1.
However, algorithm to choose which one to overwrite is implementation 
dependant.

After checking MIPS CPU documentations, 4 algorithms are emerging:
- Random register is decremented once at each clock tick
- Random register is decremented once after 'number of wired TLB 
entries' clock ticks
- Random register is decremented only after TLBWR instruction
- Random register uses a Not Last Used algorithm, ie whatever value 
which is not the previous one

At the moment, Qemu implementation seems to be more the 4th one, but can 
return the same value more than once.
Due to this, NetBSD 1.6.2 on MIPS Magnum emulation crashes.

Attached patch tries to fix the problem by adding 4 methods to update 
Random value.
Each CPU needs to define which Random algorithm it is using.
Patch also optimizes CP0_Random access, by not requiring call to a 
helper function
Finally, it initializes CP0_Random even in user mode emulation, which 
was not the case before.

Signed-off-by: Hervé Poussineau <address@hidden>

Please comment

Hervé

cp0_random.diff
Description: plain/text