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[Qemu-devel] [PATCH 27/62] tcg-s390: Implement bswap operations.
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 27/62] tcg-s390: Implement bswap operations. |
Date: |
Thu, 27 May 2010 13:46:09 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/s390/tcg-target.c | 24 ++++++++++++++++++++++++
tcg/s390/tcg-target.h | 10 +++++-----
2 files changed, 29 insertions(+), 5 deletions(-)
diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c
index 3f7d08d..7c7adb3 100644
--- a/tcg/s390/tcg-target.c
+++ b/tcg/s390/tcg-target.c
@@ -78,6 +78,8 @@ typedef enum S390Opcode {
RRE_LLGCR = 0xb984,
RRE_LLGFR = 0xb916,
RRE_LLGHR = 0xb985,
+ RRE_LRVR = 0xb91f,
+ RRE_LRVGR = 0xb90f,
RRE_MSGR = 0xb90c,
RRE_MSR = 0xb252,
RRE_NGR = 0xb980,
@@ -1117,6 +1119,21 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc,
tgen_ext32u(s, args[0], args[1]);
break;
+ case INDEX_op_bswap16_i32:
+ case INDEX_op_bswap16_i64:
+ /* The TCG bswap definition requires bits 0-47 already be zero.
+ Thus we don't need the G-type insns to implement bswap16_i64. */
+ tcg_out_insn(s, RRE, LRVR, args[0], args[1]);
+ tcg_out_insn(s, RS, SRL, args[0], 0, SH32_REG_NONE, 16);
+ break;
+ case INDEX_op_bswap32_i32:
+ case INDEX_op_bswap32_i64:
+ tcg_out_insn(s, RRE, LRVR, args[0], args[1]);
+ break;
+ case INDEX_op_bswap64_i64:
+ tcg_out_insn(s, RRE, LRVGR, args[0], args[1]);
+ break;
+
case INDEX_op_br:
tgen_branch(s, S390_CC_ALWAYS, args[0]);
break;
@@ -1229,6 +1246,9 @@ static const TCGTargetOpDef s390_op_defs[] = {
{ INDEX_op_ext16s_i32, { "r", "r" } },
{ INDEX_op_ext16u_i32, { "r", "r" } },
+ { INDEX_op_bswap16_i32, { "r", "r" } },
+ { INDEX_op_bswap32_i32, { "r", "r" } },
+
{ INDEX_op_brcond_i32, { "r", "r" } },
{ INDEX_op_setcond_i32, { "r", "r", "r" } },
@@ -1286,6 +1306,10 @@ static const TCGTargetOpDef s390_op_defs[] = {
{ INDEX_op_ext32s_i64, { "r", "r" } },
{ INDEX_op_ext32u_i64, { "r", "r" } },
+ { INDEX_op_bswap16_i64, { "r", "r" } },
+ { INDEX_op_bswap32_i64, { "r", "r" } },
+ { INDEX_op_bswap64_i64, { "r", "r" } },
+
{ INDEX_op_brcond_i64, { "r", "r" } },
{ INDEX_op_setcond_i64, { "r", "r", "r" } },
#endif
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index 76a13fc..76f1d03 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -54,8 +54,8 @@ typedef enum TCGReg {
#define TCG_TARGET_HAS_ext16s_i32
#define TCG_TARGET_HAS_ext8u_i32
#define TCG_TARGET_HAS_ext16u_i32
-// #define TCG_TARGET_HAS_bswap16_i32
-// #define TCG_TARGET_HAS_bswap32_i32
+#define TCG_TARGET_HAS_bswap16_i32
+#define TCG_TARGET_HAS_bswap32_i32
// #define TCG_TARGET_HAS_not_i32
#define TCG_TARGET_HAS_neg_i32
// #define TCG_TARGET_HAS_andc_i32
@@ -72,9 +72,9 @@ typedef enum TCGReg {
#define TCG_TARGET_HAS_ext8u_i64
#define TCG_TARGET_HAS_ext16u_i64
#define TCG_TARGET_HAS_ext32u_i64
-// #define TCG_TARGET_HAS_bswap16_i64
-// #define TCG_TARGET_HAS_bswap32_i64
-// #define TCG_TARGET_HAS_bswap64_i64
+#define TCG_TARGET_HAS_bswap16_i64
+#define TCG_TARGET_HAS_bswap32_i64
+#define TCG_TARGET_HAS_bswap64_i64
// #define TCG_TARGET_HAS_not_i64
#define TCG_TARGET_HAS_neg_i64
// #define TCG_TARGET_HAS_andc_i64
--
1.7.0.1
- [Qemu-devel] [PATCH 18/62] tcg-s390: Use matching constraints., (continued)
- [Qemu-devel] [PATCH 18/62] tcg-s390: Use matching constraints., Richard Henderson, 2010/05/27
- [Qemu-devel] [PATCH 20/62] tcg-s390: Implement setcond., Richard Henderson, 2010/05/27
- [Qemu-devel] [PATCH 15/62] tcg-s390: Update disassembler from binutils head., Richard Henderson, 2010/05/27
- [Qemu-devel] [PATCH 17/62] tcg-s390: Reorganize instruction emission, Richard Henderson, 2010/05/27
- [Qemu-devel] [PATCH 21/62] tcg-s390: Generalize the direct load/store emission., Richard Henderson, 2010/05/27
- [Qemu-devel] [PATCH 22/62] tcg-s390: Tidy branches., Richard Henderson, 2010/05/27
- [Qemu-devel] [PATCH 23/62] tcg-s390: Add tgen_calli., Richard Henderson, 2010/05/27
- [Qemu-devel] [PATCH 25/62] tcg-s390: Re-implement tcg_out_movi., Richard Henderson, 2010/05/27
- [Qemu-devel] [PATCH 24/62] tcg-s390: Implement div2., Richard Henderson, 2010/05/27
- [Qemu-devel] [PATCH 26/62] tcg-s390: Implement sign and zero-extension operations., Richard Henderson, 2010/05/27
- [Qemu-devel] [PATCH 27/62] tcg-s390: Implement bswap operations.,
Richard Henderson <=
- [Qemu-devel] [PATCH 28/62] tcg-s390: Implement rotates., Richard Henderson, 2010/05/27
- [Qemu-devel] [PATCH 29/62] tcg-s390: Use LOAD COMPLIMENT for negate., Richard Henderson, 2010/05/27
- [Qemu-devel] [PATCH 30/62] tcg-s390: Tidy unimplemented opcodes., Richard Henderson, 2010/05/27
- [Qemu-devel] [PATCH 31/62] tcg-s390: Use the extended-immediate facility for add/sub., Richard Henderson, 2010/05/27
- [Qemu-devel] [PATCH 32/62] tcg-s390: Implement immediate ANDs., Richard Henderson, 2010/05/27
- [Qemu-devel] [PATCH 33/62] tcg-s390: Implement immediate ORs., Richard Henderson, 2010/05/27
- [Qemu-devel] [PATCH 34/62] tcg-s390: Implement immediate MULs., Richard Henderson, 2010/05/27
- [Qemu-devel] [PATCH 35/62] tcg-s390: Implement immediate XORs., Richard Henderson, 2010/05/27
- [Qemu-devel] [PATCH 37/62] tcg-s390: Define TCG_TMP0., Richard Henderson, 2010/05/27
- [Qemu-devel] [PATCH 38/62] tcg-s390: Tidy regset initialization; use R14 as temporary., Richard Henderson, 2010/05/27