[Qemu-devel] [PATCH_v2 8/9] target-openrisc: Complete remove of npc and ppc variables

[Sebastian Macke]

According to the specification the registers "npc" (next pc) and
ppc (previous pc) are only meant for external debuggers.
They have undefined behavior when you read and especially write to it.

Additionally in the current implementation they show different behavior
when in singlestep mode.

Because they are no longer needed and decrease the performance by using
two tcg instructions per opcode they are removed.

Signed-off-by: Sebastian Macke <address@hidden>
---
 target-openrisc/cpu.h              |  2 --
 target-openrisc/gdbstub.c          | 16 ++--------------
 target-openrisc/interrupt_helper.c |  1 -
 target-openrisc/machine.c          |  2 --
 target-openrisc/sys_helper.c       | 14 --------------
 target-openrisc/translate.c        | 17 ++---------------
 6 files changed, 4 insertions(+), 48 deletions(-)

diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
index ab87cd2..24afe6f 100644
--- a/target-openrisc/cpu.h
+++ b/target-openrisc/cpu.h
@@ -283,8 +283,6 @@ typedef struct CPUOpenRISCTLBContext {
 typedef struct CPUOpenRISCState {
     target_ulong gpr[32];     /* General registers */
     target_ulong pc;          /* Program counter */
-    target_ulong npc;         /* Next PC */
-    target_ulong ppc;         /* Prev PC */
     target_ulong jmp_pc;      /* Jump PC */
 
     target_ulong machi;       /* Multiply register MACHI */
diff --git a/target-openrisc/gdbstub.c b/target-openrisc/gdbstub.c
index 81acf2d..c1f9561 100644
--- a/target-openrisc/gdbstub.c
+++ b/target-openrisc/gdbstub.c
@@ -30,13 +30,8 @@ int openrisc_cpu_gdb_read_register(CPUState *cs, uint8_t 
*mem_buf, int n)
         return gdb_get_reg32(mem_buf, env->gpr[n]);
     } else {
         switch (n) {
-        case 32:    /* PPC */
-            return gdb_get_reg32(mem_buf, env->ppc);
 
-        case 33:    /* NPC */
-            return gdb_get_reg32(mem_buf, env->npc);
-
-        case 34:    /* SR */
+        case 32:    /* SR */
             return gdb_get_reg32(mem_buf, ENV_GET_SR(env));
 
         default:
@@ -63,15 +58,8 @@ int openrisc_cpu_gdb_write_register(CPUState *cs, uint8_t 
*mem_buf, int n)
         env->gpr[n] = tmp;
     } else {
         switch (n) {
-        case 32: /* PPC */
-            env->ppc = tmp;
-            break;
-
-        case 33: /* NPC */
-            env->npc = tmp;
-            break;
 
-        case 34: /* SR */
+        case 32: /* SR */
             ENV_SET_SR(env, tmp);
             break;
 
diff --git a/target-openrisc/interrupt_helper.c 
b/target-openrisc/interrupt_helper.c
index 8a07b09..ae187f5 100644
--- a/target-openrisc/interrupt_helper.c
+++ b/target-openrisc/interrupt_helper.c
@@ -30,7 +30,6 @@ void HELPER(rfe)(CPUOpenRISCState *env)
                          (cpu->env.esr & (SR_SM | SR_IME | SR_DME));
 #endif
     cpu->env.pc = cpu->env.epcr;
-    cpu->env.npc = cpu->env.epcr;
     ENV_SET_SR(&(cpu->env), cpu->env.esr);
 
 #ifndef CONFIG_USER_ONLY
diff --git a/target-openrisc/machine.c b/target-openrisc/machine.c
index 2bdd40f..6846e14 100644
--- a/target-openrisc/machine.c
+++ b/target-openrisc/machine.c
@@ -34,8 +34,6 @@ static const VMStateDescription vmstate_env = {
         VMSTATE_UINT32(esr, CPUOpenRISCState),
         VMSTATE_UINT32(fpcsr, CPUOpenRISCState),
         VMSTATE_UINT32(pc, CPUOpenRISCState),
-        VMSTATE_UINT32(npc, CPUOpenRISCState),
-        VMSTATE_UINT32(ppc, CPUOpenRISCState),
         VMSTATE_END_OF_LIST()
     }
 };
diff --git a/target-openrisc/sys_helper.c b/target-openrisc/sys_helper.c
index 1d0651a..3eda0e1 100644
--- a/target-openrisc/sys_helper.c
+++ b/target-openrisc/sys_helper.c
@@ -38,10 +38,6 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
         env->vr = rb;
         break;
 
-    case TO_SPR(0, 16): /* NPC */
-        env->npc = rb;
-        break;
-
     case TO_SPR(0, 17): /* SR */
         if ((env->sr & (SR_IME | SR_DME | SR_SM)) ^
             (rb & (SR_IME | SR_DME | SR_SM))) {
@@ -66,10 +62,6 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
         }
         break;
 
-    case TO_SPR(0, 18): /* PPC */
-        env->ppc = rb;
-        break;
-
     case TO_SPR(0, 32): /* EPCR */
         env->epcr = rb;
         break;
@@ -194,15 +186,9 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
     case TO_SPR(0, 4): /* IMMUCFGR */
         return env->immucfgr;
 
-    case TO_SPR(0, 16): /* NPC */
-        return env->npc;
-
     case TO_SPR(0, 17): /* SR */
         return ENV_GET_SR(env);
 
-    case TO_SPR(0, 18): /* PPC */
-        return env->ppc;
-
     case TO_SPR(0, 32): /* EPCR */
         return env->epcr;
 
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 1ae807f..8fc679b 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -41,7 +41,7 @@
 
 typedef struct DisasContext {
     TranslationBlock *tb;
-    target_ulong pc, ppc, npc;
+    target_ulong pc;
     uint32_t tb_flags, synced_flags, flags;
     uint32_t is_jmp;
     uint32_t mem_idx;
@@ -55,8 +55,6 @@ static TCGv cpu_srf;
 static TCGv cpu_R[32];
 static TCGv cpu_pc;
 static TCGv jmp_pc;            /* l.jr/l.jalr temp pc */
-static TCGv cpu_npc;
-static TCGv cpu_ppc;
 static TCGv_i32 fpcsr;
 static TCGv machi, maclo;
 static TCGv fpmaddhi, fpmaddlo;
@@ -83,10 +81,6 @@ void openrisc_translate_init(void)
                                        "flags");
     cpu_pc = tcg_global_mem_new(TCG_AREG0,
                                 offsetof(CPUOpenRISCState, pc), "pc");
-    cpu_npc = tcg_global_mem_new(TCG_AREG0,
-                                 offsetof(CPUOpenRISCState, npc), "npc");
-    cpu_ppc = tcg_global_mem_new(TCG_AREG0,
-                                 offsetof(CPUOpenRISCState, ppc), "ppc");
     jmp_pc = tcg_global_mem_new(TCG_AREG0,
                                 offsetof(CPUOpenRISCState, jmp_pc), "jmp_pc");
     fpcsr = tcg_global_mem_new_i32(TCG_AREG0,
@@ -1662,7 +1656,6 @@ static inline void 
gen_intermediate_code_internal(OpenRISCCPU *cpu,
 
     gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
     dc->is_jmp = DISAS_NEXT;
-    dc->ppc = pc_start;
     dc->pc = pc_start;
     dc->flags = cpu->env.cpucfgr;
     dc->mem_idx = cpu_mmu_index(&cpu->env);
@@ -1707,12 +1700,8 @@ static inline void 
gen_intermediate_code_internal(OpenRISCCPU *cpu,
         if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
             gen_io_start();
         }
-        dc->ppc = dc->pc - 4;
-        dc->npc = dc->pc + 4;
-        tcg_gen_movi_tl(cpu_ppc, dc->ppc);
-        tcg_gen_movi_tl(cpu_npc, dc->npc);
         disas_openrisc_insn(dc, cpu);
-        dc->pc = dc->npc;
+        dc->pc += 4;
         num_insns++;
         /* delay slot */
         if (dc->delayed_branch) {
@@ -1721,8 +1710,6 @@ static inline void 
gen_intermediate_code_internal(OpenRISCCPU *cpu,
                 dc->tb_flags &= ~D_FLAG;
                 gen_sync_flags(dc);
                 tcg_gen_mov_tl(cpu_pc, jmp_pc);
-                tcg_gen_mov_tl(cpu_npc, jmp_pc);
-                tcg_gen_movi_tl(jmp_pc, 0);
                 tcg_gen_exit_tb(0);
                 dc->is_jmp = DISAS_JUMP;
                 break;
-- 
1.8.4.1