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[Qemu-devel] [PULL 094/130] target-ppc: Altivec 2.07: Add Support for Du
From: |
Alexander Graf |
Subject: |
[Qemu-devel] [PULL 094/130] target-ppc: Altivec 2.07: Add Support for Dual Altivec Instructions |
Date: |
Fri, 7 Mar 2014 00:33:41 +0100 |
From: Tom Musta <address@hidden>
Some Alitvec instructions introduced in Power ISA Version 2.07 use bit 31
(aka the "Rc" bit) as an opcode bit. However, QEMU for PowerPC uses
bits 0-5 and 21-30 for opcodes and not bit 31.
This patch introduces macros that will handle this situation by injecting
an auxiliary handler which decodes bit 31 in invokes one of two standard
handlers. Since the instructions are not, in general, from the same version
of the ISA, two sets of PPC_*/PPC2_* instruction tags are supported.
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
target-ppc/translate.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 85dad7f..ffcee7f 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6904,6 +6904,26 @@ static void glue(gen_, name)(DisasContext *ctx)
\
tcg_temp_free_ptr(rd); \
}
+/*
+ * Support for Altivec instruction pairs that use bit 31 (Rc) as
+ * an opcode bit. In general, these pairs come from different
+ * versions of the ISA, so we must also support a pair of flags for
+ * each instruction.
+ */
+#define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
+static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
+{ \
+ if ((Rc(ctx->opcode) == 0) && \
+ ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
+ gen_##name0(ctx); \
+ } else if ((Rc(ctx->opcode) == 1) && \
+ ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
+ gen_##name1(ctx); \
+ } else { \
+ gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
+ } \
+}
+
GEN_VXFORM(vaddubm, 0, 0);
GEN_VXFORM(vadduhm, 0, 1);
GEN_VXFORM(vadduwm, 0, 2);
@@ -10260,6 +10280,10 @@ GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
#undef GEN_VXFORM
#define GEN_VXFORM(name, opc2, opc3) \
GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
+#undef GEN_VXFORM_DUAL
+#define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
+GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
+
GEN_VXFORM(vaddubm, 0, 0),
GEN_VXFORM(vadduhm, 0, 1),
GEN_VXFORM(vadduwm, 0, 2),
--
1.8.1.4
- Re: [Qemu-devel] [PULL 073/130] Add Enhanced Three-Speed Ethernet Controller (eTSEC), (continued)
- [Qemu-devel] [PULL 088/130] target-ppc: Store Quadword, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 086/130] target-ppc: Add is_user_mode Utility Routine, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 087/130] target-ppc: Load Quadword, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 092/130] target-ppc: Altivec 2.07: Update AVR Structure, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 091/130] target-ppc: Altivec 2.07: Add Instruction Flag, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 095/130] target-ppc: Altivec 2.07: Add Opcode Macro for VX Form Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 090/130] target-ppc: Add Store Quadword Conditional, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 097/130] target-ppc: Altivec 2.07: Vector Logical Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 098/130] target-ppc: Altivec 2.07: Add/Subtract Unsigned Doubleword Modulo, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 094/130] target-ppc: Altivec 2.07: Add Support for Dual Altivec Instructions,
Alexander Graf <=
- [Qemu-devel] [PULL 096/130] target-ppc: Altivec 2.07: Add Support for R-Form Dual Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 093/130] target-ppc: Altivec 2.07: Add GEN_VXFORM3, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 101/130] target-ppc: Altivec 2.07: vmuluw Instruction, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 104/130] target-ppc: Altivec 2.07: Vector Min/Max Doubleword Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 100/130] target-ppc: Altivec 2.07: Multiply Even/Odd Word Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 099/130] target-ppc: Altivec 2.07: Change VMUL_DO to Support 64-bit Integers, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 106/130] target-ppc: Altivec 2.07: Unpack Signed Word Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 102/130] target-ppc: Altivec 2.07: Add Vector Count Leading Zeroes, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 103/130] target-ppc: Altivec 2.07: Vector Population Count Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 107/130] target-ppc: Altivec 2.07: Vector Merge Instructions, Alexander Graf, 2014/03/06