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[Qemu-devel] [PULL 039/130] target-ppc: VSX Stage 4: Add xsaddsp and xss
From: |
Alexander Graf |
Subject: |
[Qemu-devel] [PULL 039/130] target-ppc: VSX Stage 4: Add xsaddsp and xssubsp |
Date: |
Fri, 7 Mar 2014 00:32:46 +0100 |
From: Tom Musta <address@hidden>
This patch adds the VSX Scalar Add Single-Precision (xsaddsp) and
VSX Scalar Subtract Single-Precision (xssubsp) instructions.
The existing VSX_ADD_SUB macro is modified to support the rounding
of the (intermediate) result to single-precision.
Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
target-ppc/fpu_helper.c | 20 +++++++++++++-------
target-ppc/helper.h | 3 +++
target-ppc/translate.c | 6 ++++++
3 files changed, 22 insertions(+), 7 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 3165ef0..f047640 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -1768,7 +1768,7 @@ static void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState
*env)
* fld - vsr_t field (f32 or f64)
* sfprf - set FPRF
*/
-#define VSX_ADD_SUB(name, op, nels, tp, fld, sfprf) \
+#define VSX_ADD_SUB(name, op, nels, tp, fld, sfprf, r2sp) \
void helper_##name(CPUPPCState *env, uint32_t opcode) \
{ \
ppc_vsr_t xt, xa, xb; \
@@ -1794,6 +1794,10 @@ void helper_##name(CPUPPCState *env, uint32_t opcode)
\
} \
} \
\
+ if (r2sp) { \
+ xt.fld[i] = helper_frsp(env, xt.fld[i]); \
+ } \
+ \
if (sfprf) { \
helper_compute_fprf(env, xt.fld[i], sfprf); \
} \
@@ -1802,12 +1806,14 @@ void helper_##name(CPUPPCState *env, uint32_t opcode)
\
helper_float_check_status(env); \
}
-VSX_ADD_SUB(xsadddp, add, 1, float64, f64, 1)
-VSX_ADD_SUB(xvadddp, add, 2, float64, f64, 0)
-VSX_ADD_SUB(xvaddsp, add, 4, float32, f32, 0)
-VSX_ADD_SUB(xssubdp, sub, 1, float64, f64, 1)
-VSX_ADD_SUB(xvsubdp, sub, 2, float64, f64, 0)
-VSX_ADD_SUB(xvsubsp, sub, 4, float32, f32, 0)
+VSX_ADD_SUB(xsadddp, add, 1, float64, f64, 1, 0)
+VSX_ADD_SUB(xsaddsp, add, 1, float64, f64, 1, 1)
+VSX_ADD_SUB(xvadddp, add, 2, float64, f64, 0, 0)
+VSX_ADD_SUB(xvaddsp, add, 4, float32, f32, 0, 0)
+VSX_ADD_SUB(xssubdp, sub, 1, float64, f64, 1, 0)
+VSX_ADD_SUB(xssubsp, sub, 1, float64, f64, 1, 1)
+VSX_ADD_SUB(xvsubdp, sub, 2, float64, f64, 0, 0)
+VSX_ADD_SUB(xvsubsp, sub, 4, float32, f32, 0, 0)
/* VSX_MUL - VSX floating point multiply
* op - instruction mnemonic
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 0276b02..696b9d3 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -286,6 +286,9 @@ DEF_HELPER_2(xsrdpim, void, env, i32)
DEF_HELPER_2(xsrdpip, void, env, i32)
DEF_HELPER_2(xsrdpiz, void, env, i32)
+DEF_HELPER_2(xsaddsp, void, env, i32)
+DEF_HELPER_2(xssubsp, void, env, i32)
+
DEF_HELPER_2(xvadddp, void, env, i32)
DEF_HELPER_2(xvsubdp, void, env, i32)
DEF_HELPER_2(xvmuldp, void, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index d67bf2d..f0925d5 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7358,6 +7358,9 @@ GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
+GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
+
GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
@@ -10164,6 +10167,9 @@ GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
+GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
+GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
+
GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
--
1.8.1.4
- [Qemu-devel] [PULL 017/130] target-ppc: Add set_fprf Argument to fload_invalid_op_excp(), (continued)
- [Qemu-devel] [PULL 017/130] target-ppc: Add set_fprf Argument to fload_invalid_op_excp(), Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 020/130] target-ppc: Add VSX ISA2.06 xmul Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 034/130] target-ppc: VSX Stage 4: Add VSX 2.07 Flag, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 008/130] kvm: Add a new machine option kvm-type, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 026/130] target-ppc: Add VSX ISA2.06 xtsqrt Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 036/130] target-ppc: VSX Stage 4: Add lxsiwax, lxsiwzx and lxsspx, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 018/130] target-ppc: General Support for VSX Helpers, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 024/130] target-ppc: Add VSX ISA2.06 xrsqrte Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 037/130] target-ppc: VSX Stage 4: Refactor stxsdx, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 038/130] target-ppc: VSX Stage 4: Add stxsiwx and stxsspx, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 039/130] target-ppc: VSX Stage 4: Add xsaddsp and xssubsp,
Alexander Graf <=
- [Qemu-devel] [PULL 033/130] target-ppc: Add VSX Rounding Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 040/130] target-ppc: VSX Stage 4: Add xsmulsp, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 028/130] target-ppc: Add VSX xscmp*dp Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 042/130] target-ppc: VSX Stage 4: Add xsresp, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 022/130] target-ppc: Add VSX ISA2.06 xre Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 045/130] target-ppc: VSX Stage 4: Add Scalar SP Fused Multiply-Adds, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 030/130] target-ppc: Add VSX Vector Compare Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 041/130] target-ppc: VSX Stage 4: Add xsdivsp, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 047/130] target-ppc: VSX Stage 4: Add xxleqv, xxlnand and xxlorc, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 049/130] target-ppc: Floating Merge Word Instructions, Alexander Graf, 2014/03/06