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[Qemu-devel] [PULL 058/130] target-ppc: Add Flag for ISA2.06 Atomic Inst
From: |
Alexander Graf |
Subject: |
[Qemu-devel] [PULL 058/130] target-ppc: Add Flag for ISA2.06 Atomic Instructions |
Date: |
Fri, 7 Mar 2014 00:33:05 +0100 |
From: Tom Musta <address@hidden>
This patch adds a flag for the atomic instructions introduced
in Power ISA V2.06B.
Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
target-ppc/cpu.h | 5 ++++-
target-ppc/translate_init.c | 9 ++++++---
2 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index ab900a4..bf2b64f 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1881,10 +1881,13 @@ enum {
PPC2_PERM_ISA206 = 0x0000000000000080ULL,
/* ISA 2.06B divide extended variants */
PPC2_DIVE_ISA206 = 0x0000000000000100ULL,
+ /* ISA 2.06B larx/stcx. instructions */
+ PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
+
#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
- PPC2_DIVE_ISA206)
+ PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206)
};
/*****************************************************************************/
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 76f326d..abe0a21 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7069,7 +7069,8 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
PPC_SEGMENT_64B | PPC_SLBI |
PPC_POPCNTB | PPC_POPCNTWD;
pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
- PPC2_PERM_ISA206 | PPC2_DIVE_ISA206;
+ PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
+ PPC2_ATOMIC_ISA206;
pcc->msr_mask = 0x800000000284FF37ULL;
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
@@ -7108,7 +7109,8 @@ POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data)
PPC_SEGMENT_64B | PPC_SLBI |
PPC_POPCNTB | PPC_POPCNTWD;
pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
- PPC2_PERM_ISA206 | PPC2_DIVE_ISA206;
+ PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
+ PPC2_ATOMIC_ISA206;
pcc->msr_mask = 0x800000000204FF37ULL;
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
@@ -7147,7 +7149,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
PPC_SEGMENT_64B | PPC_SLBI |
PPC_POPCNTB | PPC_POPCNTWD;
pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
- PPC2_PERM_ISA206 | PPC2_DIVE_ISA206;
+ PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
+ PPC2_ATOMIC_ISA206;
pcc->msr_mask = 0x800000000284FF36ULL;
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
--
1.8.1.4
- [Qemu-devel] [PULL 047/130] target-ppc: VSX Stage 4: Add xxleqv, xxlnand and xxlorc, (continued)
- [Qemu-devel] [PULL 047/130] target-ppc: VSX Stage 4: Add xxleqv, xxlnand and xxlorc, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 049/130] target-ppc: Floating Merge Word Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 043/130] target-ppc: VSX Stage 4: Add xssqrtsp, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 046/130] target-ppc: VSX Stage 4: Add xscvsxdsp and xscvuxdsp, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 056/130] target-ppc: Add ISA 2.06 divweu[o] Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 053/130] target-ppc: Add Flag for ISA2.06 Divide Extended Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 057/130] target-ppc: Add ISA 2.06 divwe[o] Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 050/130] target-ppc: Scalar Round to Single Precision, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 048/130] target-ppc: Move To/From VSR Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 044/130] target-ppc: VSX Stage 4: add xsrsqrtesp, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 058/130] target-ppc: Add Flag for ISA2.06 Atomic Instructions,
Alexander Graf <=
- [Qemu-devel] [PULL 055/130] target-ppc: Add ISA2.06 divde[o] Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 052/130] target-ppc: Add ISA2.06 bpermd Instruction, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 068/130] target-ppc: Enable frsqrtes on Power7 and Power8, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 069/130] target-ppc: Add ISA2.06 lfiwzx Instruction, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 054/130] target-ppc: Add ISA2.06 divdeu[o] Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 051/130] target-ppc: Scalar Non-Signalling Conversions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 071/130] virtex_ml507: Add support for loading initrd images, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 061/130] target-ppc: Add Flag for ISA V2.06 Floating Point Conversion, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 065/130] target-ppc: Add Flag for Power ISA V2.06 Floating Point Test Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 067/130] target-ppc: Add ISA 2.06 ftsqrt, Alexander Graf, 2014/03/06