[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 30/30] scripts/qemu-binfmt-conf.sh: Add AArch64 regis
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 30/30] scripts/qemu-binfmt-conf.sh: Add AArch64 registration |
Date: |
Mon, 17 Mar 2014 22:12:21 +0000 |
Add the binfmt-misc magic needed to register QEMU for handling AArch64
ELF binaries.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
scripts/qemu-binfmt-conf.sh | 3 +++
1 file changed, 3 insertions(+)
diff --git a/scripts/qemu-binfmt-conf.sh b/scripts/qemu-binfmt-conf.sh
index 0da2618..289b1a3 100644
--- a/scripts/qemu-binfmt-conf.sh
+++ b/scripts/qemu-binfmt-conf.sh
@@ -41,6 +41,9 @@ if [ $cpu != "arm" ] ; then
echo
':arm:M::\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x28\x00:\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff:/usr/local/bin/qemu-arm:'
> /proc/sys/fs/binfmt_misc/register
echo
':armeb:M::\x7fELF\x01\x02\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x28:\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff:/usr/local/bin/qemu-armeb:'
> /proc/sys/fs/binfmt_misc/register
fi
+if [ $cpu != "aarch64" ] ; then
+ echo
':aarch64:M::\x7fELF\x02\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\xb7\x00:\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff:/usr/local/bin/qemu-aarch64:'
> /proc/sys/fs/binfmt_misc/register
+fi
if [ $cpu != "sparc" ] ; then
echo
':sparc:M::\x7fELF\x01\x02\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x02:\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff:/usr/local/bin/qemu-sparc:'
> /proc/sys/fs/binfmt_misc/register
fi
--
1.9.0
- [Qemu-devel] [PULL for-2.0rc1 00/30] target-arm queue, Peter Maydell, 2014/03/17
- [Qemu-devel] [PULL 12/30] target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP, Peter Maydell, 2014/03/17
- [Qemu-devel] [PULL 10/30] target-arm: A64: Add remaining CLS/Z vector ops, Peter Maydell, 2014/03/17
- [Qemu-devel] [PULL 23/30] target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categories, Peter Maydell, 2014/03/17
- [Qemu-devel] [PULL 17/30] target-arm: A64: List unsupported shift-imm opcodes, Peter Maydell, 2014/03/17
- [Qemu-devel] [PULL 27/30] target-arm: A64: Implement scalar saturating narrow ops, Peter Maydell, 2014/03/17
- [Qemu-devel] [PULL 30/30] scripts/qemu-binfmt-conf.sh: Add AArch64 registration,
Peter Maydell <=
- [Qemu-devel] [PULL 11/30] target-arm: A64: Saturating and narrowing shift ops, Peter Maydell, 2014/03/17
- [Qemu-devel] [PULL 20/30] target-arm: A64: Implement FRINT*, Peter Maydell, 2014/03/17
- [Qemu-devel] [PULL 29/30] target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate), Peter Maydell, 2014/03/17
- [Qemu-devel] [PULL 15/30] target-arm: A64: Implement FCVTN, Peter Maydell, 2014/03/17
- [Qemu-devel] [PULL 08/30] target-arm: A64: Add last AdvSIMD Integer to FP ops, Peter Maydell, 2014/03/17
- [Qemu-devel] [PULL 24/30] softfloat: export squash_input_denormal functions, Peter Maydell, 2014/03/17
- [Qemu-devel] [PULL 01/30] vexpress: Set reset-cbar property for CPUs, Peter Maydell, 2014/03/17
- [Qemu-devel] [PULL 18/30] target-arm: A64: Add FRECPX (reciprocal exponent), Peter Maydell, 2014/03/17
- [Qemu-devel] [PULL 28/30] target-arm: A64: Implement FCVTXN, Peter Maydell, 2014/03/17
- [Qemu-devel] [PULL 25/30] target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPE, Peter Maydell, 2014/03/17