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[Qemu-devel] [PATCH v5 26/37] target-arm: Implement ISR_EL1 register
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v5 26/37] target-arm: Implement ISR_EL1 register |
Date: |
Fri, 28 Mar 2014 16:10:13 +0000 |
Implement the ISR_EL1 register. This is actually present in
ARMv7 as well but was previously unimplemented. It is a
read-only register that indicates whether interrupts are
currently pending.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index f2e6f17..398c8f5 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -665,6 +665,21 @@ static void csselr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
env->cp15.c0_cssel = value & 0xf;
}
+static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+ CPUState *cs = ENV_GET_CPU(env);
+ uint64_t ret = 0;
+
+ if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
+ ret |= CPSR_I;
+ }
+ if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
+ ret |= CPSR_F;
+ }
+ /* External aborts are not possible in QEMU so A bit is always clear */
+ return ret;
+}
+
static const ARMCPRegInfo v7_cp_reginfo[] = {
/* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
* debug components
@@ -782,6 +797,9 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
.cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
.fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el1),
.resetfn = arm_cp_reset_ignore },
+ { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
+ .type = ARM_CP_NO_MIGRATE, .access = PL1_R, .readfn = isr_read },
REGINFO_SENTINEL
};
--
1.9.0
- [Qemu-devel] [PATCH v5 02/37] target-arm: Implement AArch64 DAIF system register, (continued)
- [Qemu-devel] [PATCH v5 02/37] target-arm: Implement AArch64 DAIF system register, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 20/37] target-arm: Implement ARMv8 MVFR registers, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 09/37] target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 08/37] target-arm: A64: Add assertion that FP access was checked, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 06/37] target-arm: Provide syndrome information for MMU faults, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 19/37] target-arm: Implement AArch64 EL1 exception handling, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 36/37] target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pc, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 27/37] target-arm: Remove THUMB2EE feature from AArch64 'any' CPU, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 30/37] target-arm: Implement auxiliary fault status registers, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 18/37] target-arm: Move arm_log_exception() into internals.h, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 26/37] target-arm: Implement ISR_EL1 register,
Peter Maydell <=