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Re: [Qemu-devel] [PATCH v2 04/23] target-arm: preserve RAO/WI bits of AR
From: |
Sergey Fedorov |
Subject: |
Re: [Qemu-devel] [PATCH v2 04/23] target-arm: preserve RAO/WI bits of ARMv7 SCTLR |
Date: |
Wed, 14 May 2014 09:43:35 +0400 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 |
On 13.05.2014 20:15, Fabian Aggeler wrote:
> From: Svetlana Fedoseeva <address@hidden>
>
> Signed-off-by: Svetlana Fedoseeva <address@hidden>
> Signed-off-by: Sergey Fedorov <address@hidden>
> Signed-off-by: Fabian Aggeler <address@hidden>
> ---
> target-arm/helper.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 9c3269f..2b57ad9 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -2083,6 +2083,11 @@ static void sctlr_write(CPUARMState *env, const
> ARMCPRegInfo *ri,
> {
> ARMCPU *cpu = arm_env_get_cpu(env);
>
> + if (arm_feature(env, ARM_FEATURE_V7)) {
> + value |= SCTLR_XP | SCTLR_U | SCTLR_nTWE | SCTLR_nTWI | SCTLR_L
> + | SCTLR_CP15BEN | SCTLR_P; /* These bits are RAO/WI */
Actually, some of these bits are RAO/WI since v6. Also, there are some
RAZ/WI bits varying over architecture variants. There is some overview
at ARM ARM v7-AP section L.7.4. Maybe it is worth to fix more precisely
over supported architecture variants? By the way, this patch could be
separated from security extensions support patch set.
Thanks,
Sergey.
> + }
> +
> env->cp15.c1_sys = value;
> /* ??? Lots of these bits are not implemented. */
> /* This may enable/disable the MMU, so do a TLB flush. */
- Re: [Qemu-devel] [PATCH v2 10/23] target-arm: implement CPACR register logic, (continued)
Re: [Qemu-devel] [PATCH v2 10/23] target-arm: implement CPACR register logic, Peter Crosthwaite, 2014/05/14
[Qemu-devel] [PATCH v2 03/23] target-arm: adjust TTBCR for Security Extension feature, Fabian Aggeler, 2014/05/13
[Qemu-devel] [PATCH v2 12/23] target-arm: add SDER definition, Fabian Aggeler, 2014/05/13
[Qemu-devel] [PATCH v2 07/23] target-arm: reject switching to monitor mode from non-secure state, Fabian Aggeler, 2014/05/13
[Qemu-devel] [PATCH v2 08/23] target-arm: adjust arm_current_pl() for Security Extensions, Fabian Aggeler, 2014/05/13
[Qemu-devel] [PATCH v2 05/23] target-arm: add CPU Monitor mode, Fabian Aggeler, 2014/05/13
[Qemu-devel] [PATCH v2 04/23] target-arm: preserve RAO/WI bits of ARMv7 SCTLR, Fabian Aggeler, 2014/05/13
- Re: [Qemu-devel] [PATCH v2 04/23] target-arm: preserve RAO/WI bits of ARMv7 SCTLR,
Sergey Fedorov <=
[Qemu-devel] [PATCH v2 22/23] target-arm: implement IRQ/FIQ routing to Monitor mode, Fabian Aggeler, 2014/05/13
[Qemu-devel] [PATCH v2 11/23] target-arm: add NSACR support, Fabian Aggeler, 2014/05/13
[Qemu-devel] [PATCH v2 14/23] target-arm: add banked coprocessor register type and macros, Fabian Aggeler, 2014/05/13