This puts a limit to the number of threads per core based on the current
compatibility mode. Although PowerISA specs do not specify the maximum
threads per core number, the linux guest still expects that
PowerISA2.05-compatible CPU supports only 2 threads per core as this
is what POWER6 (2.05 compliant CPU) implements, same is true for
POWER7 (2.06, 4 threads) and POWER8 (2.07, 8 threads).
Signed-off-by: Alexey Kardashevskiy <address@hidden>
---
hw/ppc/spapr.c | 31 ++++++++++++++++++++++++++++---
1 file changed, 28 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index cf53a7a..a2c9106 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -34,6 +34,7 @@
#include "sysemu/kvm.h"
#include "kvm_ppc.h"
#include "mmu-hash64.h"
+#include "cpu-models.h"
#include "hw/boards.h"
#include "hw/ppc/ppc.h"
@@ -203,6 +204,29 @@ static XICSState *xics_system_init(int nr_servers, int
nr_irqs)
return icp;
}
+static int spapr_get_compat_smp_threads(PowerPCCPU *cpu)
+{
+ int ret = -1;
+
+ switch (cpu->cpu_version) {
+ case CPU_POWERPC_LOGICAL_2_05:
+ ret = 2;
+ break;
+ case CPU_POWERPC_LOGICAL_2_06:
+ ret = 4;
+ break;
+ case CPU_POWERPC_LOGICAL_2_07:
+ ret = 8;
+ break;
+ default:
+ ret = smp_threads;
+ break;
+ }
+ ret = MIN(ret, smp_threads);