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[Qemu-devel] [PATCH v5 22/23] target-arm: A64: Register VBAR_EL2
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v5 22/23] target-arm: A64: Register VBAR_EL2 |
Date: |
Sun, 25 May 2014 11:08:51 +1000 |
From: "Edgar E. Iglesias" <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target-arm/cpu.h | 2 +-
target-arm/helper.c | 21 +++++++++++++++++++++
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index b14fac5..3ccbd95 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -198,7 +198,7 @@ typedef struct CPUARMState {
uint32_t c9_pmuserenr; /* perf monitor user enable */
uint32_t c9_pminten; /* perf monitor interrupt enables */
uint64_t mair_el1;
- uint64_t vbar_el[2]; /* vector base address register */
+ uint64_t vbar_el[3]; /* vector base address register */
uint32_t c13_fcse; /* FCSE PID. */
uint64_t contextidr_el1; /* Context ID. */
uint64_t tpidr_el0; /* User RW Thread register. */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 5a2073e..ebe735b 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2077,6 +2077,15 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
REGINFO_SENTINEL
};
+/* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
+static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = {
+ { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
+ .access = PL2_RW,
+ .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
+ REGINFO_SENTINEL
+};
+
static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
{ .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
.type = ARM_CP_NO_MIGRATE,
@@ -2087,6 +2096,11 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
.type = ARM_CP_NO_MIGRATE,
.opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
.access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[6]) },
+ { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
+ .access = PL2_RW, .writefn = vbar_write,
+ .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
+ .resetvalue = 0 },
REGINFO_SENTINEL
};
@@ -2356,6 +2370,13 @@ void register_cp_regs_for_features(ARMCPU *cpu)
}
if (arm_feature(env, ARM_FEATURE_EL2)) {
define_arm_cp_regs(cpu, v8_el2_cp_reginfo);
+ } else {
+ /* If EL2 is missing but higher ELs are enabled, we need to
+ * register the no_el2 reginfos.
+ */
+ if (arm_feature(env, ARM_FEATURE_EL3)) {
+ define_arm_cp_regs(cpu, v8_el3_no_el2_cp_reginfo);
+ }
}
if (arm_feature(env, ARM_FEATURE_EL3)) {
define_arm_cp_regs(cpu, v8_el3_cp_reginfo);
--
1.8.3.2
- [Qemu-devel] [PATCH v5 12/23] target-arm: A64: Introduce aarch64_banked_spsr_index(), (continued)
- [Qemu-devel] [PATCH v5 12/23] target-arm: A64: Introduce aarch64_banked_spsr_index(), Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 13/23] target-arm: Add a feature flag for EL2, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 14/23] target-arm: Add a feature flag for EL3, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 15/23] target-arm: Register EL2 versions of ELR and SPSR, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 16/23] target-arm: Register EL3 versions of ELR and SPSR, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 17/23] target-arm: A64: Forbid ERET to higher or unimplemented ELs, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 18/23] target-arm: A64: Trap ERET from EL0 at translation time, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 19/23] target-arm: A64: Generalize ERET to various ELs, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 20/23] target-arm: A64: Generalize update_spsel for the various ELs, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 21/23] target-arm: Make vbar_write writeback to any CPREG, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 22/23] target-arm: A64: Register VBAR_EL2,
Edgar E. Iglesias <=
- [Qemu-devel] [PATCH v5 23/23] target-arm: A64: Register VBAR_EL3, Edgar E. Iglesias, 2014/05/24