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[Qemu-devel] [PULL 02/26] hw/display/pxa2xx_lcd: Fix 16bpp+alpha and 18b
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 02/26] hw/display/pxa2xx_lcd: Fix 16bpp+alpha and 18bpp+alpha palette formats |
Date: |
Tue, 27 May 2014 17:28:10 +0100 |
The pxa2xx palette entry "16bpp plus transparency" format is
xxxxxxxTRRRRR000GGGGGG00BBBBB000, and "18bpp plus transparency" is
xxxxxxxTRRRRRR00GGGGGG00BBBBBB00.
Correct errors in the code for reading these and converting
them to the internal format. In particular, the buggy code
was attempting to mask out bit 24 of a uint16_t, which
Coverity spotted as an error.
Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
---
hw/display/pxa2xx_lcd.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/display/pxa2xx_lcd.c b/hw/display/pxa2xx_lcd.c
index 80edb70..611fb17 100644
--- a/hw/display/pxa2xx_lcd.c
+++ b/hw/display/pxa2xx_lcd.c
@@ -620,24 +620,24 @@ static void pxa2xx_palette_parse(PXA2xxLCDState *s, int
ch, int bpp)
src += 2;
break;
case 1: /* 16 bpp plus transparency */
- alpha = *(uint16_t *) src & (1 << 24);
+ alpha = *(uint32_t *) src & (1 << 24);
if (s->control[0] & LCCR0_CMS)
- r = g = b = *(uint16_t *) src & 0xff;
+ r = g = b = *(uint32_t *) src & 0xff;
else {
- r = (*(uint16_t *) src & 0xf800) >> 8;
- g = (*(uint16_t *) src & 0x07e0) >> 3;
- b = (*(uint16_t *) src & 0x001f) << 3;
+ r = (*(uint32_t *) src & 0xf80000) >> 16;
+ g = (*(uint32_t *) src & 0x00fc00) >> 8;
+ b = (*(uint32_t *) src & 0x0000f8);
}
- src += 2;
+ src += 4;
break;
case 2: /* 18 bpp plus transparency */
alpha = *(uint32_t *) src & (1 << 24);
if (s->control[0] & LCCR0_CMS)
r = g = b = *(uint32_t *) src & 0xff;
else {
- r = (*(uint32_t *) src & 0xf80000) >> 16;
+ r = (*(uint32_t *) src & 0xfc0000) >> 16;
g = (*(uint32_t *) src & 0x00fc00) >> 8;
- b = (*(uint32_t *) src & 0x0000f8);
+ b = (*(uint32_t *) src & 0x0000fc);
}
src += 4;
break;
--
1.9.2
- [Qemu-devel] [PULL 16/26] target-arm: Add a feature flag for EL2, (continued)
- [Qemu-devel] [PULL 16/26] target-arm: Add a feature flag for EL2, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 15/26] target-arm: A64: Introduce aarch64_banked_spsr_index(), Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 23/26] target-arm: A64: Generalize update_spsel for the various ELs, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 25/26] target-arm: A64: Register VBAR_EL2, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 14/26] target-arm: Add SPSR entries for EL2/HYP and EL3/MON, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 08/26] target-arm: Use a 1:1 mapping between EL and MMU index, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 13/26] target-arm: A64: Add ELR entries for EL2 and 3, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 20/26] target-arm: A64: Forbid ERET to higher or unimplemented ELs, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 05/26] target-arm/translate.c: Clean up mmu index handling for ldrt/strt, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 06/26] target-arm/translate.c: Use get_mem_index() for SRS memory accesses, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 02/26] hw/display/pxa2xx_lcd: Fix 16bpp+alpha and 18bpp+alpha palette formats,
Peter Maydell <=
- [Qemu-devel] [PULL 07/26] target-arm: A32: Use get_mem_index for load/stores, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 09/26] target-arm: Make elr_el1 an array, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 03/26] target-arm: implement CPACR register logic for ARMv7, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 04/26] target-arm: Move get_mem_index to translate.h, Peter Maydell, 2014/05/27
- Re: [Qemu-devel] [PULL 00/26] target-arm queue, Peter Maydell, 2014/05/28