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[Qemu-devel] [PATCH v3 25/32] target-arm: make c2_mask and c2_base_mask
From: |
Fabian Aggeler |
Subject: |
[Qemu-devel] [PATCH v3 25/32] target-arm: make c2_mask and c2_base_mask banked |
Date: |
Wed, 11 Jun 2014 01:55:07 +0200 |
Since TTBCR is banked we will bank c2_mask and c2_base_mask too. This
avoids recalculating them on switches from secure to non-secure world.
Signed-off-by: Fabian Aggeler <address@hidden>
---
target-arm/cpu.h | 10 ++++++++--
target-arm/helper.c | 19 ++++++++++++-------
2 files changed, 20 insertions(+), 9 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index f26baac..09f658b 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -232,8 +232,14 @@ typedef struct CPUARMState {
uint64_t tcr_el3;
};
};
- uint32_t c2_mask; /* MMU translation table base selection mask. */
- uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
+ struct { /* MMU translation table base selection mask. */
+ uint32_t c2_mask_ns;
+ uint32_t c2_mask_s;
+ };
+ struct { /* MMU translation table base 0 mask. */
+ uint32_t c2_base_mask_ns;
+ uint32_t c2_base_mask_s;
+ };
uint32_t c2_data; /* MPU data cachable bits. */
uint32_t c2_insn; /* MPU instruction cachable bits. */
uint32_t c3; /* MMU domain access control register
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 85de791..2c48895 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1435,8 +1435,11 @@ static void vmsa_ttbcr_raw_write(CPUARMState *env, const
ARMCPRegInfo *ri,
* and the c2_mask and c2_base_mask values are meaningless.
*/
raw_write(env, ri, value);
- env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift);
- env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift);
+
+ A32_BANKED_CURRENT_REG_SET(env, c2_mask,
+ ~(((uint32_t)0xffffffffu) >> maskshift));
+ A32_BANKED_CURRENT_REG_SET(env, c2_base_mask,
+ ~((uint32_t)0x3fffu >> maskshift));
}
static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -1455,9 +1458,9 @@ static void vmsa_ttbcr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
{
- env->cp15.c2_base_mask = 0xffffc000u;
+ A32_BANKED_CURRENT_REG_SET(env, c2_base_mask, 0xffffc000u);
raw_write(env, ri, 0);
- env->cp15.c2_mask = 0;
+ A32_BANKED_CURRENT_REG_SET(env, c2_mask, 0);
}
static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -3984,10 +3987,12 @@ static uint32_t get_level1_table_address(CPUARMState
*env, uint32_t address)
* Aarch32 there is a secure and non-secure instance of the translation
* table registers.
*/
- if (address & env->cp15.c2_mask)
+ if (address & A32_BANKED_CURRENT_REG_GET(env, c2_mask)) {
table = A32_BANKED_CURRENT_REG_GET(env, ttbr1) & 0xffffc000;
- else
- table = A32_BANKED_CURRENT_REG_GET(env, ttbr0) &
env->cp15.c2_base_mask;
+ } else {
+ table = A32_BANKED_CURRENT_REG_GET(env, ttbr0) &
+ A32_BANKED_CURRENT_REG_GET(env, c2_base_mask);
+ }
table |= (address >> 18) & 0x3ffc;
return table;
--
1.8.3.2
- [Qemu-devel] [PATCH v3 17/32] target-arm: add MVBAR support, (continued)
- [Qemu-devel] [PATCH v3 17/32] target-arm: add MVBAR support, Fabian Aggeler, 2014/06/10
- [Qemu-devel] [PATCH v3 18/32] target-arm: add macros to access banked registers, Fabian Aggeler, 2014/06/10
- [Qemu-devel] [PATCH v3 19/32] target-arm: insert Aarch32 cpregs twice into hashtable, Fabian Aggeler, 2014/06/10
- [Qemu-devel] [PATCH v3 20/32] target-arm: arrayfying fieldoffset for banking, Fabian Aggeler, 2014/06/10
- [Qemu-devel] [PATCH v3 21/32] target-arm: add SCTLR_EL3 and make SCTLR banked, Fabian Aggeler, 2014/06/10
- [Qemu-devel] [PATCH v3 22/32] target-arm: make CSSELR banked, Fabian Aggeler, 2014/06/10
- [Qemu-devel] [PATCH v3 23/32] target-arm: add TTBR0_EL3 and make TTBR0/1 banked, Fabian Aggeler, 2014/06/10
- [Qemu-devel] [PATCH v3 24/32] target-arm: add TCR_EL3 and make TTBCR banked, Fabian Aggeler, 2014/06/10
- [Qemu-devel] [PATCH v3 25/32] target-arm: make c2_mask and c2_base_mask banked,
Fabian Aggeler <=
- [Qemu-devel] [PATCH v3 28/32] target-arm: make DFSR banked, Fabian Aggeler, 2014/06/10
- [Qemu-devel] [PATCH v3 26/32] target-arm: make DACR banked, Fabian Aggeler, 2014/06/10
- [Qemu-devel] [PATCH v3 27/32] target-arm: make IFSR banked, Fabian Aggeler, 2014/06/10
- [Qemu-devel] [PATCH v3 29/32] target-arm: make IFAR/DFAR banked, Fabian Aggeler, 2014/06/10
- [Qemu-devel] [PATCH v3 32/32] target-arm: make c13 cp regs banked (FCSEIDR, ...), Fabian Aggeler, 2014/06/10