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[Qemu-devel] [PULL 17/19] target-i386: Support "invariant tsc" flag
From: |
Andreas Färber |
Subject: |
[Qemu-devel] [PULL 17/19] target-i386: Support "invariant tsc" flag |
Date: |
Thu, 26 Jun 2014 00:12:17 +0200 |
From: Marcelo Tosatti <address@hidden>
Expose "Invariant TSC" flag, if KVM is enabled. From Intel documentation:
17.13.1 Invariant TSC The time stamp counter in newer processors may
support an enhancement, referred to as invariant TSC. Processor’s
support for invariant TSC is indicated by CPUID.80000007H:EDX[8].
The invariant TSC will run at a constant rate in all ACPI P-, C-.
and T-states. This is the architectural behavior moving forward. On
processors with invariant TSC support, the OS may use the TSC for wall
clock timer services (instead of ACPI or HPET timers). TSC reads are
much more efficient and do not incur the overhead associated with a ring
transition or access to a platform resource.
Signed-off-by: Marcelo Tosatti <address@hidden>
[ehabkost: redo feature filtering to use .tcg_features]
[ehabkost: add CPUID_APM_INVTSC macro, add it to .unmigratable_flags]
Signed-off-by: Eduardo Habkost <address@hidden>
Signed-off-by: Andreas Färber <address@hidden>
---
target-i386/cpu.c | 25 +++++++++++++++++++++++++
target-i386/cpu.h | 4 ++++
2 files changed, 29 insertions(+)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index b651a94..4cfb9a3 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -263,6 +263,17 @@ static const char *cpuid_7_0_ebx_feature_name[] = {
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
};
+static const char *cpuid_apm_edx_feature_name[] = {
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ "invtsc", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+};
+
#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
@@ -317,6 +328,7 @@ static const char *cpuid_7_0_ebx_feature_name[] = {
CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
CPUID_7_0_EBX_RDSEED */
+#define TCG_APM_FEATURES 0
typedef struct FeatureWordInfo {
@@ -372,6 +384,13 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
.cpuid_reg = R_EBX,
.tcg_features = TCG_7_0_EBX_FEATURES,
},
+ [FEAT_8000_0007_EDX] = {
+ .feat_names = cpuid_apm_edx_feature_name,
+ .cpuid_eax = 0x80000007,
+ .cpuid_reg = R_EDX,
+ .tcg_features = TCG_APM_FEATURES,
+ .unmigratable_flags = CPUID_APM_INVTSC,
+ },
};
typedef struct X86RegisterInfo32 {
@@ -2385,6 +2404,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
(AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
(L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
break;
+ case 0x80000007:
+ *eax = 0;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = env->features[FEAT_8000_0007_EDX];
+ break;
case 0x80000008:
/* virtual & phys address size in low 2 bytes. */
/* XXX: This value must match the one used in the MMU code. */
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index b5e1b41..e634d83 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -402,6 +402,7 @@ typedef enum FeatureWord {
FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */
FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */
FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */
+ FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */
FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */
FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
FEAT_SVM, /* CPUID[8000_000A].EDX */
@@ -561,6 +562,9 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_7_0_EBX_ADX (1U << 19)
#define CPUID_7_0_EBX_SMAP (1U << 20)
+/* CPUID[0x80000007].EDX flags: */
+#define CPUID_APM_INVTSC (1U << 8)
+
#define CPUID_VENDOR_SZ 12
#define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
--
1.8.4.5
- [Qemu-devel] [PULL 07/19] target-i386: Filter FEAT_7_0_EBX TCG features too, (continued)
- [Qemu-devel] [PULL 07/19] target-i386: Filter FEAT_7_0_EBX TCG features too, Andreas Färber, 2014/06/25
- [Qemu-devel] [PULL 09/19] target-i386: Define TCG_*_FEATURES earlier in cpu.c, Andreas Färber, 2014/06/25
- [Qemu-devel] [PULL 05/19] target-i386: Isolate KVM-specific code on CPU feature filtering logic, Andreas Färber, 2014/06/25
- [Qemu-devel] [PULL 10/19] target-i386: Loop-based copying and setting/unsetting of feature words, Andreas Färber, 2014/06/25
- [Qemu-devel] [PULL 04/19] target-i386: Pass FeatureWord argument to report_unavailable_features(), Andreas Färber, 2014/06/25
- [Qemu-devel] [PULL 13/19] target-i386: Add "migratable" property to "host" CPU model, Andreas Färber, 2014/06/25
- [Qemu-devel] [PULL 11/19] target-i386: Loop-based feature word filtering in TCG mode, Andreas Färber, 2014/06/25
- [Qemu-devel] [PULL 08/19] target-i386: Filter KVM and 0xC0000001 features on TCG, Andreas Färber, 2014/06/25
- [Qemu-devel] [PULL 16/19] target-i386: block migration and savevm if invariant tsc is exposed, Andreas Färber, 2014/06/25
- [Qemu-devel] [PULL 14/19] target-i386: Set migratable=yes by default on "host" CPU mooel, Andreas Färber, 2014/06/25
- [Qemu-devel] [PULL 17/19] target-i386: Support "invariant tsc" flag,
Andreas Färber <=
- [Qemu-devel] [PULL 19/19] target-i386: Broadwell CPU model, Andreas Färber, 2014/06/25
- [Qemu-devel] [PULL 15/19] savevm: check vmsd for migratability status, Andreas Färber, 2014/06/25
- [Qemu-devel] [PULL 18/19] target-i386: Fix indentation of CPU model definitions, Andreas Färber, 2014/06/25
- Re: [Qemu-devel] [PULL 00/19] QOM CPUState patch queue 2014-06-26, Peter Maydell, 2014/06/26