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[Qemu-devel] [PATCH target-arm v2 1/1] arm: cortex-a9: Fix cache-line si
From: |
Peter Crosthwaite |
Subject: |
[Qemu-devel] [PATCH target-arm v2 1/1] arm: cortex-a9: Fix cache-line size and associativity |
Date: |
Mon, 18 Aug 2014 00:14:34 -0700 |
For A9, The cache associativity is 4 and the lines size is 16B.
Self identify in CCSIDR accordingly. Cache size remains at 16k.
QEMU doesn't emulate caches, but we should still report the correct
cache-line size to the guest. Some guests (like u-boot) complain if
the cache-line size mismatches a requested flush or invalidate
operation.
Signed-off-by: Peter Crosthwaite <address@hidden>
---
changed since v1:
Clarify innacuries in commit message (Edgar review).
Fix associativity (Edgar review).
target-arm/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 7cebb76..1a1634b 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -713,8 +713,8 @@ static void cortex_a9_initfn(Object *obj)
cpu->id_isar3 = 0x11112131;
cpu->id_isar4 = 0x00111142;
cpu->clidr = (1 << 27) | (1 << 24) | 3;
- cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
- cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
+ cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
+ cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
}
--
2.0.1.1.gfbfc394
- [Qemu-devel] [PATCH target-arm v2 1/1] arm: cortex-a9: Fix cache-line size and associativity,
Peter Crosthwaite <=