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[Qemu-devel] [PATCH target-arm v3 1/8] target-arm: Make the ARM PMCCNTR
From: |
Peter Crosthwaite |
Subject: |
[Qemu-devel] [PATCH target-arm v3 1/8] target-arm: Make the ARM PMCCNTR register 64-bit |
Date: |
Mon, 18 Aug 2014 01:12:17 -0700 |
From: Alistair Francis <address@hidden>
This makes the PMCCNTR register 64-bit to allow for the
64-bit ARMv8 version.
Signed-off-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
---
changed since v2:
Fixed indentation of muldiv64s
target-arm/cpu.h | 2 +-
target-arm/helper.c | 19 +++++++++----------
2 files changed, 10 insertions(+), 11 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 79205ba..b903558 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -223,7 +223,7 @@ typedef struct CPUARMState {
/* If the counter is enabled, this stores the last time the counter
* was reset. Otherwise it stores the counter value
*/
- uint32_t c15_ccnt;
+ uint64_t c15_ccnt;
} cp15;
struct {
diff --git a/target-arm/helper.c b/target-arm/helper.c
index f630d96..42368db 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -550,11 +550,10 @@ static CPAccessResult pmreg_access(CPUARMState *env,
const ARMCPRegInfo *ri)
static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- /* Don't computer the number of ticks in user mode */
- uint32_t temp_ticks;
+ uint64_t temp_ticks;
- temp_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
- get_ticks_per_sec() / 1000000;
+ temp_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
+ get_ticks_per_sec(), 1000000);
if (env->cp15.c9_pmcr & PMCRE) {
/* If the counter is enabled */
@@ -586,15 +585,15 @@ static void pmcr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
- uint32_t total_ticks;
+ uint64_t total_ticks;
if (!(env->cp15.c9_pmcr & PMCRE)) {
/* Counter is disabled, do not change value */
return env->cp15.c15_ccnt;
}
- total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
- get_ticks_per_sec() / 1000000;
+ total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
+ get_ticks_per_sec(), 1000000);
if (env->cp15.c9_pmcr & PMCRD) {
/* Increment once every 64 processor clock cycles */
@@ -606,7 +605,7 @@ static uint64_t pmccntr_read(CPUARMState *env, const
ARMCPRegInfo *ri)
static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- uint32_t total_ticks;
+ uint64_t total_ticks;
if (!(env->cp15.c9_pmcr & PMCRE)) {
/* Counter is disabled, set the absolute value */
@@ -614,8 +613,8 @@ static void pmccntr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
return;
}
- total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
- get_ticks_per_sec() / 1000000;
+ total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
+ get_ticks_per_sec(), 1000000);
if (env->cp15.c9_pmcr & PMCRD) {
/* Increment once every 64 processor clock cycles */
--
2.0.1.1.gfbfc394
- [Qemu-devel] [PATCH target-arm v3 0/8] target-arm: Extend PMCCNTR for ARMv8, Peter Crosthwaite, 2014/08/18
- [Qemu-devel] [PATCH target-arm v3 1/8] target-arm: Make the ARM PMCCNTR register 64-bit,
Peter Crosthwaite <=
- [Qemu-devel] [PATCH target-arm v3 2/8] arm: Implement PMCCNTR 32b read-modify-write, Peter Crosthwaite, 2014/08/18
- [Qemu-devel] [PATCH target-arm v3 3/8] target-arm: Implement PMCCNTR_EL0 and related registers, Peter Crosthwaite, 2014/08/18
- [Qemu-devel] [PATCH target-arm v3 4/8] target-arm: Add arm_ccnt_enabled function, Peter Crosthwaite, 2014/08/18
- [Qemu-devel] [PATCH target-arm v3 5/8] target-arm: Implement pmccntr_sync function, Peter Crosthwaite, 2014/08/18
- [Qemu-devel] [PATCH target-arm v3 6/8] target-arm: Remove old code and replace with new functions, Peter Crosthwaite, 2014/08/18
- [Qemu-devel] [PATCH target-arm v3 7/8] target-arm: Implement pmccfiltr_write function, Peter Crosthwaite, 2014/08/18
- [Qemu-devel] [PATCH target-arm v3 8/8] target-arm: Call pmccntr_sync() when swapping ELs, Peter Crosthwaite, 2014/08/18