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[Qemu-devel] [PATCH target-arm v4 6/7] target-arm: Remove old code and r
From: |
Peter Crosthwaite |
Subject: |
[Qemu-devel] [PATCH target-arm v4 6/7] target-arm: Remove old code and replace with new functions |
Date: |
Mon, 25 Aug 2014 21:12:37 -0700 |
From: Alistair Francis <address@hidden>
Remove the old PMCCNTR code and replace it with calls to the new
pmccntr_sync() and arm_ccnt_enabled() functions.
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
---
Changed since v2:
Commit msg tweaks.
target-arm/helper.c | 27 ++++-----------------------
1 file changed, 4 insertions(+), 23 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index fa79dfa..d213ed1 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -580,20 +580,7 @@ void pmccntr_sync(CPUARMState *env)
static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- uint64_t temp_ticks;
-
- temp_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
- get_ticks_per_sec(), 1000000);
-
- if (env->cp15.c9_pmcr & PMCRE) {
- /* If the counter is enabled */
- if (env->cp15.c9_pmcr & PMCRD) {
- /* Increment once every 64 processor clock cycles */
- env->cp15.c15_ccnt = (temp_ticks/64) - env->cp15.c15_ccnt;
- } else {
- env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
- }
- }
+ pmccntr_sync(env);
if (value & PMCRC) {
/* The counter has been reset */
@@ -604,20 +591,14 @@ static void pmcr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
env->cp15.c9_pmcr &= ~0x39;
env->cp15.c9_pmcr |= (value & 0x39);
- if (env->cp15.c9_pmcr & PMCRE) {
- if (env->cp15.c9_pmcr & PMCRD) {
- /* Increment once every 64 processor clock cycles */
- temp_ticks /= 64;
- }
- env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
- }
+ pmccntr_sync(env);
}
static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
uint64_t total_ticks;
- if (!(env->cp15.c9_pmcr & PMCRE)) {
+ if (!arm_ccnt_enabled(env)) {
/* Counter is disabled, do not change value */
return env->cp15.c15_ccnt;
}
@@ -637,7 +618,7 @@ static void pmccntr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
{
uint64_t total_ticks;
- if (!(env->cp15.c9_pmcr & PMCRE)) {
+ if (!arm_ccnt_enabled(env)) {
/* Counter is disabled, set the absolute value */
env->cp15.c15_ccnt = value;
return;
--
2.1.0.1.g27b9230
- [Qemu-devel] [PATCH target-arm v4 0/7] target-arm: Extend PMCCNTR for ARMv8, Peter Crosthwaite, 2014/08/26
- [Qemu-devel] [PATCH target-arm v4 1/7] target-arm: Make the ARM PMCCNTR register 64-bit, Peter Crosthwaite, 2014/08/26
- [Qemu-devel] [PATCH target-arm v4 2/7] arm: Implement PMCCNTR 32b read-modify-write, Peter Crosthwaite, 2014/08/26
- [Qemu-devel] [PATCH target-arm v4 3/7] target-arm: Implement PMCCNTR_EL0 and related registers, Peter Crosthwaite, 2014/08/26
- [Qemu-devel] [PATCH target-arm v4 4/7] target-arm: Add arm_ccnt_enabled function, Peter Crosthwaite, 2014/08/26
- [Qemu-devel] [PATCH target-arm v4 5/7] target-arm: Implement pmccntr_sync function, Peter Crosthwaite, 2014/08/26
- [Qemu-devel] [PATCH target-arm v4 6/7] target-arm: Remove old code and replace with new functions,
Peter Crosthwaite <=
- [Qemu-devel] [PATCH target-arm v4 7/7] target-arm: Implement pmccfiltr_write function, Peter Crosthwaite, 2014/08/26
- Re: [Qemu-devel] [PATCH target-arm v4 0/7] target-arm: Extend PMCCNTR for ARMv8, Peter Maydell, 2014/08/29