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Re: [Qemu-devel] [PULL 00/16] target-arm queue
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PULL 00/16] target-arm queue |
Date: |
Fri, 29 Aug 2014 16:46:53 +0100 |
On 29 August 2014 15:37, Peter Maydell <address@hidden> wrote:
>
> target-arm queue: I wanted to send out some of the easier stuff in
> my review queue, at least. I'll try to work through the meatier
> review work next week...
>
> thanks
> -- PMM
>
> The following changes since commit d9aa68855724752a5684c6acfb17d8db15cec2f8:
>
> Merge remote-tracking branch 'remotes/kraxel/tags/pull-usb-20140829-1' into
> staging (2014-08-29 13:08:04 +0100)
>
> are available in the git repository at:
>
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git
> tags/pull-target-arm-20140829
>
> for you to fetch changes up to 0614601cecc8e5d9c6c5fa606b39fe388a18583a:
>
> target-arm: Implement pmccfiltr_write function (2014-08-29 15:00:30 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * support PMCCNTR in ARMv8
> * various GIC fixes and cleanups
> * Correct Cortex-A57 ISAR5 and AA64ISAR0 ID register values
> * Fix regression that disabled VFP for ARMv5 CPUs
> * Update to upstream VIXL 1.5
>
> ----------------------------------------------------------------
Applied, thanks.
-- PMM
- [Qemu-devel] [PULL 09/16] hw/intc/arm_gic: honor target mask in gic_update(), (continued)
- [Qemu-devel] [PULL 09/16] hw/intc/arm_gic: honor target mask in gic_update(), Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 02/16] target-arm: Fix regression that disabled VFP for ARMv5 CPUs, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 03/16] target-arm: Correct Cortex-A57 ISAR5 and AA64ISAR0 ID register values, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 07/16] arm_gic: Use GIC_NR_SGIS constant, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 04/16] arm_gic: Fix read of GICD_ICFGR, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 10/16] target-arm: Make the ARM PMCCNTR register 64-bit, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 08/16] aarch64: raise max_cpus to 8, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 05/16] arm_gic: GICD_ICFGR: Write model only for pre v1 GICs, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 15/16] target-arm: Remove old code and replace with new functions, Peter Maydell, 2014/08/29
- [Qemu-devel] [PULL 06/16] arm_gic: Do not force PPIs to edge-triggered mode, Peter Maydell, 2014/08/29
- Re: [Qemu-devel] [PULL 00/16] target-arm queue,
Peter Maydell <=