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[Qemu-devel] [PATCH v6 06/10] target-arm: A64: Correct updates to FAR an
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v6 06/10] target-arm: A64: Correct updates to FAR and ESR on exceptions |
Date: |
Sat, 13 Sep 2014 14:29:20 +1000 |
From: "Edgar E. Iglesias" <address@hidden>
Not all exception types update both FAR and ESR.
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Greg Bellows <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target-arm/helper-a64.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index 4be0784..c6ef8e9 100644
--- a/target-arm/helper-a64.c
+++ b/target-arm/helper-a64.c
@@ -466,18 +466,17 @@ void aarch64_cpu_do_interrupt(CPUState *cs)
env->exception.syndrome);
}
- env->cp15.esr_el[new_el] = env->exception.syndrome;
- env->cp15.far_el[new_el] = env->exception.vaddress;
-
switch (cs->exception_index) {
case EXCP_PREFETCH_ABORT:
case EXCP_DATA_ABORT:
+ env->cp15.far_el[new_el] = env->exception.vaddress;
qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n",
env->cp15.far_el[new_el]);
- break;
+ /* fall through */
case EXCP_BKPT:
case EXCP_UDEF:
case EXCP_SWI:
+ env->cp15.esr_el[new_el] = env->exception.syndrome;
break;
case EXCP_IRQ:
addr += 0x80;
--
1.9.1
- [Qemu-devel] [PATCH v6 02/10] target-arm: Add SCR_EL3, (continued)
[Qemu-devel] [PATCH v6 03/10] target-arm: A64: Refactor aarch64_cpu_do_interrupt, Edgar E. Iglesias, 2014/09/13
[Qemu-devel] [PATCH v6 04/10] target-arm: Break out exception masking to a separate func, Edgar E. Iglesias, 2014/09/13
[Qemu-devel] [PATCH v6 05/10] target-arm: Don't take interrupts targeting lower ELs, Edgar E. Iglesias, 2014/09/13
[Qemu-devel] [PATCH v6 06/10] target-arm: A64: Correct updates to FAR and ESR on exceptions,
Edgar E. Iglesias <=
[Qemu-devel] [PATCH v6 07/10] target-arm: A64: Emulate the HVC insn, Edgar E. Iglesias, 2014/09/13
[Qemu-devel] [PATCH v6 08/10] target-arm: A64: Emulate the SMC insn, Edgar E. Iglesias, 2014/09/13