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[Qemu-devel] [PATCH 09/14] ppc: introduce ppc_get_crf and ppc_set_crf
From: |
Paolo Bonzini |
Subject: |
[Qemu-devel] [PATCH 09/14] ppc: introduce ppc_get_crf and ppc_set_crf |
Date: |
Mon, 15 Sep 2014 17:03:36 +0200 |
These two functions will group together four CR bits into a single
value, once we change the representation of condition registers.
Signed-off-by: Paolo Bonzini <address@hidden>
---
linux-user/main.c | 2 +-
target-ppc/cpu.h | 10 ++++++++++
target-ppc/excp_helper.c | 2 +-
target-ppc/fpu_helper.c | 6 ++++--
target-ppc/int_helper.c | 14 +++++++-------
target-ppc/translate.c | 13 +++++++------
6 files changed, 30 insertions(+), 17 deletions(-)
diff --git a/linux-user/main.c b/linux-user/main.c
index 472a16d..152c031 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -1550,7 +1550,7 @@ static int do_store_exclusive(CPUPPCState *env)
}
}
}
- env->crf[0] = (stored << 1) | xer_so;
+ ppc_set_crf(env, 0, (stored << 1) | xer_so);
env->reserve_addr = (target_ulong)-1;
}
if (!segv) {
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 0c0196d..91eac17 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1217,6 +1217,16 @@ static inline void ppc_set_cr(CPUPPCState *env, uint32_t
cr)
}
}
+static inline uint32_t ppc_get_crf(const CPUPPCState *env, int i)
+{
+ return env->crf[i];
+}
+
+static inline void ppc_set_crf(CPUPPCState *env, int i, uint32_t val)
+{
+ env->crf[i] = val;
+}
+
static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
{
uint64_t gprv;
diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
index 96ad9d7..08637c1 100644
--- a/target-ppc/excp_helper.c
+++ b/target-ppc/excp_helper.c
@@ -504,7 +504,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
excp_model, int excp)
env->error_code);
}
#endif
- msr |= env->crf[0] << 28;
+ msr |= ppc_get_crf(env, 0) << 28;
msr |= env->error_code; /* key, D/I, S/L bits */
/* Set way using a LRU mechanism */
msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index b4e6d72..8cf321b 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -1099,7 +1099,8 @@ void helper_fcmpu(CPUPPCState *env, uint64_t arg1,
uint64_t arg2,
env->fpscr &= ~(0x0F << FPSCR_FPRF);
env->fpscr |= (0x01 << FPSCR_FPRF) << fpcc;
- env->crf[crfD] = (1 << fpcc);
+ ppc_set_crf(env, crfD, 1 << fpcc);
+
if (unlikely(fpcc == CRF_SO
&& (float64_is_signaling_nan(farg1.d) ||
float64_is_signaling_nan(farg2.d)))) {
@@ -1130,7 +1131,8 @@ void helper_fcmpo(CPUPPCState *env, uint64_t arg1,
uint64_t arg2,
env->fpscr &= ~(0x0F << FPSCR_FPRF);
env->fpscr |= (0x01 << FPSCR_FPRF) << fpcc;
- env->crf[crfD] = (1 << fpcc);
+ ppc_set_crf(env, crfD, 1 << fpcc);
+
if (unlikely(fpcc == CRF_SO)) {
if (float64_is_signaling_nan(farg1.d) ||
float64_is_signaling_nan(farg2.d)) {
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 54e8998..b76a895 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -294,7 +294,7 @@ void helper_mtocrf(CPUPPCState *env, target_ulong cr,
uint32_t mask)
int i;
for (i = ARRAY_SIZE(env->crf); --i >= 0; ) {
if (mask & 1) {
- env->crf[i] = cr & 0x0F;
+ ppc_set_crf(env, i, cr & 0x0F);
}
cr >>= 4;
mask >>= 1;
@@ -657,7 +657,7 @@ VCF(sx, int32_to_float32, s32)
none |= result; \
} \
if (record) { \
- env->crf[6] = ((all != 0) << 3) | ((none == 0) << 1); \
+ ppc_set_crf(env, 6, ((all != 0) << 3) | ((none == 0) << 1)); \
} \
}
#define VCMP(suffix, compare, element) \
@@ -703,7 +703,7 @@ VCMP(gtsd, >, s64)
none |= result; \
} \
if (record) { \
- env->crf[6] = ((all != 0) << 3) | ((none == 0) << 1); \
+ ppc_set_crf(env, 6, ((all != 0) << 3) | ((none == 0) << 1)); \
} \
}
#define VCMPFP(suffix, compare, order) \
@@ -737,7 +737,7 @@ static inline void vcmpbfp_internal(CPUPPCState *env,
ppc_avr_t *r,
}
}
if (record) {
- env->crf[6] = (all_in == 0) << 1;
+ ppc_set_crf(env, 6, (all_in == 0) << 1);
}
}
@@ -2558,7 +2558,7 @@ target_ulong helper_dlmzb(CPUPPCState *env, target_ulong
high,
for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
if ((high & mask) == 0) {
if (update_Rc) {
- env->crf[0] = 0x4;
+ ppc_set_crf(env, 0, 0x4);
}
goto done;
}
@@ -2567,7 +2567,7 @@ target_ulong helper_dlmzb(CPUPPCState *env, target_ulong
high,
for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
if ((low & mask) == 0) {
if (update_Rc) {
- env->crf[0] = 0x8;
+ ppc_set_crf(env, 0, 0x8);
}
goto done;
}
@@ -2575,7 +2575,7 @@ target_ulong helper_dlmzb(CPUPPCState *env, target_ulong
high,
}
i = 8;
if (update_Rc) {
- env->crf[0] = 0x2;
+ ppc_set_crf(env, 0, 0x2);
}
done:
env->xer = (env->xer & ~0x7F) | i;
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 52062a8..9ff8763 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -11102,18 +11102,19 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f,
fprintf_function cpu_fprintf,
cpu_fprintf(f, "\n");
}
cpu_fprintf(f, "CR ");
- for (i = 0; i < 8; i++)
- cpu_fprintf(f, "%01x", env->crf[i]);
+ for (i = 0; i < 8; i++) {
+ cpu_fprintf(f, "%01x", ppc_get_crf(env, i));
+ }
cpu_fprintf(f, " [");
for (i = 0; i < 8; i++) {
char a = '-';
- if (env->crf[i] & 0x08)
+ if (ppc_get_crf(env, i) & 0x08)
a = 'L';
- else if (env->crf[i] & 0x04)
+ else if (ppc_get_crf(env, i) & 0x04)
a = 'G';
- else if (env->crf[i] & 0x02)
+ else if (ppc_get_crf(env, i) & 0x02)
a = 'E';
- cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
+ cpu_fprintf(f, " %c%c", a, ppc_get_crf(env, i) & 0x01 ? 'O' : ' ');
}
cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
env->reserve_addr);
--
1.8.3.1
- Re: [Qemu-devel] [PATCH 03/14] target-ppc: use separate indices for various translation modes, (continued)
- [Qemu-devel] [PATCH 06/14] ppc: introduce helpers for mfocrf/mtocrf, Paolo Bonzini, 2014/09/15
- [Qemu-devel] [PATCH 07/14] ppc: reorganize gen_compute_fprf, Paolo Bonzini, 2014/09/15
- [Qemu-devel] [PATCH 08/14] ppc: introduce gen_op_mfcr/gen_op_mtcr, Paolo Bonzini, 2014/09/15
- [Qemu-devel] [PATCH 09/14] ppc: introduce ppc_get_crf and ppc_set_crf,
Paolo Bonzini <=
- [Qemu-devel] [PATCH 10/14] ppc: use movcond for isel, Paolo Bonzini, 2014/09/15
- [Qemu-devel] [PATCH 11/14] ppc: store CR registers in 32 1-bit registers, Paolo Bonzini, 2014/09/15
- [Qemu-devel] [PATCH 12/14] ppc: use movcond to implement evsel, Paolo Bonzini, 2014/09/15
- [Qemu-devel] [PATCH 13/14] ppc: inline ppc_set_crf when clearer, Paolo Bonzini, 2014/09/15