[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 06/11] tcg-sparc: Use UMULXHI instruction
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 06/11] tcg-sparc: Use UMULXHI instruction |
Date: |
Mon, 22 Sep 2014 13:57:36 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
disas/sparc.c | 1 +
tcg/sparc/tcg-target.c | 5 +++++
tcg/sparc/tcg-target.h | 2 +-
3 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/disas/sparc.c b/disas/sparc.c
index 22ceac3..8e755d1 100644
--- a/disas/sparc.c
+++ b/disas/sparc.c
@@ -2034,6 +2034,7 @@ IMPDEP ("impdep2", 0x37),
{ "addxc", F3F(2, 0x36, 0x011), F3F(~2, ~0x36, ~0x011), "1,2,d", 0, v9b },
{ "addxccc", F3F(2, 0x36, 0x013), F3F(~2, ~0x36, ~0x013), "1,2,d", 0, v9b },
+{ "umulxhi", F3F(2, 0x36, 0x016), F3F(~2, ~0x36, ~0x016), "1,2,d", 0, v9b },
};
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index 0a8c26a..0c4b028 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -210,6 +210,7 @@ static const int tcg_target_call_oarg_regs[] = {
#define ARITH_MOVR (INSN_OP(2) | INSN_OP3(0x2f))
#define ARITH_ADDXC (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x11))
+#define ARITH_UMULXHI (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x16))
#define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25))
#define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26))
@@ -1435,6 +1436,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_addsub2_i64(s, args[0], args[1], args[2], args[3], args[4],
const_args[4], args[5], const_args[5], true);
break;
+ case INDEX_op_muluh_i64:
+ tcg_out_arith(s, args[0], args[1], args[2], ARITH_UMULXHI);
+ break;
gen_arith:
tcg_out_arithc(s, a0, a1, a2, c2, c);
@@ -1535,6 +1539,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
{ INDEX_op_add2_i64, { "R", "R", "RZ", "RZ", "RJ", "RI" } },
{ INDEX_op_sub2_i64, { "R", "R", "RZ", "RZ", "RJ", "RI" } },
+ { INDEX_op_muluh_i64, { "R", "RZ", "RZ" } },
{ INDEX_op_qemu_ld_i32, { "r", "A" } },
{ INDEX_op_qemu_ld_i64, { "R", "A" } },
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index 099b308..0c4c8af 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -143,7 +143,7 @@ extern bool use_vis3_instructions;
#define TCG_TARGET_HAS_sub2_i64 1
#define TCG_TARGET_HAS_mulu2_i64 0
#define TCG_TARGET_HAS_muls2_i64 0
-#define TCG_TARGET_HAS_muluh_i64 0
+#define TCG_TARGET_HAS_muluh_i64 use_vis3_instructions
#define TCG_TARGET_HAS_mulsh_i64 0
#define TCG_AREG0 TCG_REG_I0
--
1.9.3
- [Qemu-devel] [PULL 01/11] tcg-sparc: Support addsub2_i64, (continued)
- [Qemu-devel] [PULL 01/11] tcg-sparc: Support addsub2_i64, Richard Henderson, 2014/09/22
- [Qemu-devel] [PULL 02/11] tcg-sparc: Use ADDXC in addsub2_i64, Richard Henderson, 2014/09/22
- [Qemu-devel] [PULL 04/11] tcg-sparc: Use ADDXC in setcond_i64, Richard Henderson, 2014/09/22
- [Qemu-devel] [PULL 03/11] tcg-sparc: Fix setcond_i32 uninitialized value, Richard Henderson, 2014/09/22
- [Qemu-devel] [PULL 05/11] tcg-sparc: Rename ADDX/SUBX insns, Richard Henderson, 2014/09/22
- [Qemu-devel] [PULL 07/11] tcg: Compress TCGLabelQemuLdst, Richard Henderson, 2014/09/22
[Qemu-devel] [PULL 06/11] tcg-sparc: Use UMULXHI instruction,
Richard Henderson <=
[Qemu-devel] [PULL 08/11] tcg: Move TCG_TYPE_COUNT out of enum TCGType, Richard Henderson, 2014/09/22
[Qemu-devel] [PULL 10/11] qemu/compiler: Define QEMU_ARTIFICIAL, Richard Henderson, 2014/09/22
[Qemu-devel] [PULL 11/11] tcg: Always enable TCGv type checking, Richard Henderson, 2014/09/22
[Qemu-devel] [PULL 09/11] tcg-aarch64: Use 32-bit loads for qemu_ld_i32, Richard Henderson, 2014/09/22