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[Qemu-devel] [PATCH v2 13/16] hw/intc/arm_gic: Change behavior of IAR wr
From: |
Greg Bellows |
Subject: |
[Qemu-devel] [PATCH v2 13/16] hw/intc/arm_gic: Change behavior of IAR writes |
Date: |
Thu, 30 Oct 2014 17:12:09 -0500 |
From: Fabian Aggeler <address@hidden>
Grouping (GICv2) and Security Extensions change the behavior of IAR
reads. Acknowledging Group0 interrupts is only allowed from Secure
state and acknowledging Group1 interrupts from Secure state is only
allowed if AckCtl bit is set.
Signed-off-by: Fabian Aggeler <address@hidden>
---
v1 -> v2
- Fix issue in gic_acknowledge_irq() where the GICC_CTLR_S_ACK_CTL flag is
applied without first checking whether the read is secure or non-secure.
Secure reads of IAR when AckCtl is 0 return a spurious ID of 1022, but
non-secure ignores the flag.
---
hw/intc/arm_gic.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 2d83225..7eb72df 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -190,11 +190,36 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu)
int ret, irq, src;
int cm = 1 << cpu;
irq = s->current_pending[cpu];
+ bool isGrp0;
if (irq == 1023
|| GIC_GET_PRIORITY(irq, cpu) >= s->running_priority[cpu]) {
DPRINTF("ACK no pending IRQ\n");
return 1023;
}
+
+ if (s->revision >= 2 || s->security_extn) {
+ isGrp0 = GIC_TEST_GROUP0(irq, (1 << cpu));
+ if ((isGrp0 && (!s->enabled_grp[0]
+ || !(s->cpu_control[cpu][0] & GICC_CTLR_S_EN_GRP0)))
+ || (!isGrp0 && (!s->enabled_grp[1]
+ || !(s->cpu_control[cpu][1] & GICC_CTLR_NS_EN_GRP1)))) {
+ return 1023;
+ }
+
+ if ((s->revision >= 2 && !s->security_extn)
+ || (s->security_extn && !ns_access())) {
+ if (!isGrp0 && !ns_access() &&
+ !(s->cpu_control[cpu][0] & GICC_CTLR_S_ACK_CTL)) {
+ DPRINTF("Read of IAR ignored for Group1 interrupt %d "
+ "(AckCtl disabled)\n", irq);
+ return 1022;
+ }
+ } else if (s->security_extn && ns_access() && isGrp0) {
+ DPRINTF("Non-secure read of IAR ignored for Group0 interrupt %d\n",
+ irq);
+ return 1023;
+ }
+ }
s->last_active[irq][cpu] = s->running_irq[cpu];
if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) {
--
1.8.3.2
- [Qemu-devel] [PATCH v2 14/16] hw/intc/arm_gic: Restrict priority view, (continued)
- [Qemu-devel] [PATCH v2 14/16] hw/intc/arm_gic: Restrict priority view, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 11/16] hw/intc/arm_gic: Handle grouping for GICC_HPPIR, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 05/16] hw/intc/arm_gic: Add ns_access() function, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 01/16] hw/intc/arm_gic: Request FIQ sources, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 10/16] hw/intc/arm_gic: Implement Non-secure view of RPR, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 03/16] hw/arm/virt.c: Wire FIQ between CPU <> GIC, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 16/16] hw/intc/arm_gic: add gic_update() for grouping, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 08/16] hw/intc/arm_gic: Make ICCICR/GICC_CTLR banked, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 09/16] hw/intc/arm_gic: Make ICCBPR/GICC_BPR banked, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 07/16] hw/intc/arm_gic: Make ICDDCR/GICD_CTLR banked, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 13/16] hw/intc/arm_gic: Change behavior of IAR writes,
Greg Bellows <=
- [Qemu-devel] [PATCH v2 02/16] hw/arm/vexpress.c: Wire FIQ between CPU <> GIC, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 04/16] hw/intc/arm_gic: Add Security Extensions property, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 12/16] hw/intc/arm_gic: Change behavior of EOIR writes, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 06/16] hw/intc/arm_gic: Add Interrupt Group Registers, Greg Bellows, 2014/10/31