Re: [Qemu-devel] [PATCH v8 19/27] target-arm: make DACR banked

[Greg Bellows]

Added DACR32_EL2 definition and converted dacr fields to uint64_t in v9.

On 31 October 2014 10:38, Peter Maydell <address@hidden> wrote:

On 30 October 2014 21:28, Greg Bellows <address@hidden> wrote:
> From: Fabian Aggeler <address@hidden>
>
> When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
> DACR has a secure and a non-secure instance.
>
> Signed-off-by: Fabian Aggeler <address@hidden>
> Signed-off-by: Greg Bellows <address@hidden>
> ---
>  hw/arm/pxa2xx.c     |  2 +-
>  target-arm/cpu.h    | 13 +++++++++++--
>  target-arm/helper.c | 19 +++++++++++--------
>  3 files changed, 23 insertions(+), 11 deletions(-)
>
> diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
> index 641b148..ac13d0b 100644
> --- a/hw/arm/pxa2xx.c
> +++ b/hw/arm/pxa2xx.c
> @@ -276,7 +276,7 @@ static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri,
>          s->cpu->env.cp15.sctlr_ns = 0;
>          s->cpu->env.cp15.c1_coproc = 0;
>          s->cpu->env.cp15.ttbr0_el[1] = 0;
> -        s->cpu->env.cp15.c3 = 0;
> +        s->cpu->env.cp15.dacr_ns = 0;
>          s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
>          s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 6e9f1c3..6d39af1 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -236,8 +236,17 @@ typedef struct CPUARMState {
>          };
>          uint32_t c2_data; /* MPU data cachable bits.  */
>          uint32_t c2_insn; /* MPU instruction cachable bits.  */
> -        uint32_t c3; /* MMU domain access control register
> -                        MPU write buffer control.  */
> +        union { /* MMU domain access control register
> +                 * MPU write buffer control.
> +                 */
> +            struct {
> +                uint32_t dacr_ns;
> +                uint32_t dacr_s;
> +            };
> +            struct {
> +                uint32_t dacr32_el2;
> +            };

If we're going to define a dacr32_el2 field here we should
actually implement the reginfo for it (it just has to be a
simple reads-as-written PL2_RW register). It's also going to
have to be uint64_t, which means the dacr_ns/dacr_s fields
also should be 64 bit.

Someday we should split out the MPU use of this encoding
properly into its own field because it isn't anything to
do with the DACR. I guess not today, though.

-- PMM