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[Qemu-devel] [PULL 16/33] target-arm: respect SCR.FW, SCR.AW and SCTLR.N
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 16/33] target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI |
Date: |
Thu, 11 Dec 2014 12:19:38 +0000 |
From: Fabian Aggeler <address@hidden>
Add checks of SCR AW/FW bits when performing writes of CPSR. These SCR bits
are used to control whether the CPSR masking bits can be adjusted from
non-secure state.
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 54 +++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 769a182..d43d208 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3644,6 +3644,8 @@ uint32_t cpsr_read(CPUARMState *env)
void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
{
+ uint32_t changed_daif;
+
if (mask & CPSR_NZCV) {
env->ZF = (~val) & CPSR_Z;
env->NF = val;
@@ -3666,6 +3668,58 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t
mask)
env->GE = (val >> 16) & 0xf;
}
+ /* In a V7 implementation that includes the security extensions but does
+ * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
+ * whether non-secure software is allowed to change the CPSR_F and CPSR_A
+ * bits respectively.
+ *
+ * In a V8 implementation, it is permitted for privileged software to
+ * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
+ */
+ if (!arm_feature(env, ARM_FEATURE_V8) &&
+ arm_feature(env, ARM_FEATURE_EL3) &&
+ !arm_feature(env, ARM_FEATURE_EL2) &&
+ !arm_is_secure(env)) {
+
+ changed_daif = (env->daif ^ val) & mask;
+
+ if (changed_daif & CPSR_A) {
+ /* Check to see if we are allowed to change the masking of async
+ * abort exceptions from a non-secure state.
+ */
+ if (!(env->cp15.scr_el3 & SCR_AW)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Ignoring attempt to switch CPSR_A flag from "
+ "non-secure world with SCR.AW bit clear\n");
+ mask &= ~CPSR_A;
+ }
+ }
+
+ if (changed_daif & CPSR_F) {
+ /* Check to see if we are allowed to change the masking of FIQ
+ * exceptions from a non-secure state.
+ */
+ if (!(env->cp15.scr_el3 & SCR_FW)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Ignoring attempt to switch CPSR_F flag from "
+ "non-secure world with SCR.FW bit clear\n");
+ mask &= ~CPSR_F;
+ }
+
+ /* Check whether non-maskable FIQ (NMFI) support is enabled.
+ * If this bit is set software is not allowed to mask
+ * FIQs, but is allowed to set CPSR_F to 0.
+ */
+ if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) &&
+ (val & CPSR_F)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Ignoring attempt to enable CPSR_F flag "
+ "(non-maskable FIQ [NMFI] support enabled)\n");
+ mask &= ~CPSR_F;
+ }
+ }
+ }
+
env->daif &= ~(CPSR_AIF & mask);
env->daif |= val & CPSR_AIF & mask;
--
1.9.1
- [Qemu-devel] [PULL 28/33] hw/arm/realview.c: Fix memory leak in realview_init(), (continued)
- [Qemu-devel] [PULL 28/33] hw/arm/realview.c: Fix memory leak in realview_init(), Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 31/33] target-arm/kvm: make reg sync code common between kvm32/64, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 24/33] target-arm: make PAR banked, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 23/33] target-arm: make IFAR/DFAR banked, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 21/33] target-arm: make IFSR banked, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 26/33] target-arm: make c13 cp regs banked (FCSEIDR, ...), Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 29/33] hw/arm/boot: fix uninitialized scalar variable warning reported by coverity, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 17/33] target-arm: make CSSELR banked, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 18/33] target-arm: make TTBR0/1 banked, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 19/33] target-arm: make TTBCR banked, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 16/33] target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI,
Peter Maydell <=
- [Qemu-devel] [PULL 22/33] target-arm: make DFSR banked, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 14/33] target-arm: add MVBAR support, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 12/33] target-arm: add NSACR register, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 25/33] target-arm: make VBAR banked, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 15/33] target-arm: add SCTLR_EL3 and make SCTLR banked, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 11/33] target-arm: implement IRQ/FIQ routing to Monitor mode, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 10/33] target-arm: move AArch32 SCR into security reglist, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 09/33] target-arm: insert AArch32 cpregs twice into hashtable, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 07/33] target-arm: add CPREG secure state support, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 06/33] target-arm: add non-secure Translation Block flag, Peter Maydell, 2014/12/11