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[Qemu-devel] [PATCH 6/8] target-tricore: Add missing 1.6 insn of BOL opc
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PATCH 6/8] target-tricore: Add missing 1.6 insn of BOL opcode format |
Date: |
Fri, 12 Dec 2014 17:31:42 +0000 |
Some of the 1.6 ISA instructions were still missing. So let's add them.
Signed-off-by: Bastian Koppelmann <address@hidden>
---
target-tricore/translate.c | 49 +++++++++++++++++++++++++++++++++++++++-
target-tricore/tricore-opcodes.h | 6 +++++
2 files changed, 54 insertions(+), 1 deletion(-)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 87945f4..f2f03be 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -3340,8 +3340,49 @@ static void decode_bol_opc(CPUTriCoreState *env,
DisasContext *ctx, int32_t op1)
case OPC1_32_BOL_ST_W_LONGOFF:
gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL);
break;
+ case OPC1_32_BOL_LD_B_LONGOFF:
+ if (tricore_feature(env, TRICORE_FEATURE_16)) {
+ gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
+ } else {
+ /* raise illegal opcode trap */
+ }
+ break;
+ case OPC1_32_BOL_LD_BU_LONGOFF:
+ if (tricore_feature(env, TRICORE_FEATURE_16)) {
+ gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_UB);
+ } else {
+ /* raise illegal opcode trap */
+ }
+ break;
+ case OPC1_32_BOL_LD_H_LONGOFF:
+ if (tricore_feature(env, TRICORE_FEATURE_16)) {
+ gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
+ } else {
+ /* raise illegal opcode trap */
+ }
+ break;
+ case OPC1_32_BOL_LD_HU_LONGOFF:
+ if (tricore_feature(env, TRICORE_FEATURE_16)) {
+ gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUW);
+ } else {
+ /* raise illegal opcode trap */
+ }
+ break;
+ case OPC1_32_BOL_ST_B_LONGOFF:
+ if (tricore_feature(env, TRICORE_FEATURE_16)) {
+ gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
+ } else {
+ /* raise illegal opcode trap */
+ }
+ break;
+ case OPC1_32_BOL_ST_H_LONGOFF:
+ if (tricore_feature(env, TRICORE_FEATURE_16)) {
+ gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
+ } else {
+ /* raise illegal opcode trap */
+ }
+ break;
}
-
}
/* RC format */
@@ -4667,6 +4708,12 @@ static void decode_32Bit_opc(CPUTriCoreState *env,
DisasContext *ctx)
case OPC1_32_BOL_LEA_LONGOFF:
case OPC1_32_BOL_ST_W_LONGOFF:
case OPC1_32_BOL_ST_A_LONGOFF:
+ case OPC1_32_BOL_LD_B_LONGOFF:
+ case OPC1_32_BOL_LD_BU_LONGOFF:
+ case OPC1_32_BOL_LD_H_LONGOFF:
+ case OPC1_32_BOL_LD_HU_LONGOFF:
+ case OPC1_32_BOL_ST_B_LONGOFF:
+ case OPC1_32_BOL_ST_H_LONGOFF:
decode_bol_opc(env, ctx, op1);
break;
/* BRC Format */
diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h
index 0badb28..5274765 100644
--- a/target-tricore/tricore-opcodes.h
+++ b/target-tricore/tricore-opcodes.h
@@ -451,6 +451,12 @@ enum {
OPC1_32_BOL_LEA_LONGOFF = 0xd9,
OPC1_32_BOL_ST_W_LONGOFF = 0x59,
OPC1_32_BOL_ST_A_LONGOFF = 0xb5, /* 1.6 only */
+ OPC1_32_BOL_LD_B_LONGOFF = 0x79, /* 1.6 only */
+ OPC1_32_BOL_LD_BU_LONGOFF = 0x39, /* 1.6 only */
+ OPC1_32_BOL_LD_H_LONGOFF = 0xc9, /* 1.6 only */
+ OPC1_32_BOL_LD_HU_LONGOFF = 0xb9, /* 1.6 only */
+ OPC1_32_BOL_ST_B_LONGOFF = 0xe9, /* 1.6 only */
+ OPC1_32_BOL_ST_H_LONGOFF = 0xf9, /* 1.6 only */
/* BRC Format */
OPCM_32_BRC_EQ_NEQ = 0xdf,
OPCM_32_BRC_GE = 0xff,
--
2.1.3
- Re: [Qemu-devel] [PATCH 3/8] target-tricore: Add instructions of RR opcode format, that have 0xf as the first opcode, (continued)
- [Qemu-devel] [PATCH 5/8] target-tricore: Add instructions of RR opcode format, that have 0x4b as the first opcode, Bastian Koppelmann, 2014/12/12
- [Qemu-devel] [PATCH 7/8] target-tricore: Fix MFCR/MTCR insn and B format offset., Bastian Koppelmann, 2014/12/12
- [Qemu-devel] [PATCH 8/8] target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as first opcode, Bastian Koppelmann, 2014/12/12
- [Qemu-devel] [PATCH 1/8] target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32, Bastian Koppelmann, 2014/12/12
- [Qemu-devel] [PATCH 6/8] target-tricore: Add missing 1.6 insn of BOL opcode format,
Bastian Koppelmann <=
- [Qemu-devel] [PATCH 2/8] target-tricore: Add instructions of RR opcode format, that have 0xb as the first opcode, Bastian Koppelmann, 2014/12/12