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[Qemu-devel] [PATCH 1/9] target-ppc: Introduce Instruction Type for Tran
From: |
Tom Musta |
Subject: |
[Qemu-devel] [PATCH 1/9] target-ppc: Introduce Instruction Type for Transactional Memory |
Date: |
Thu, 18 Dec 2014 10:34:29 -0600 |
Add a category (PPC2_TM) for the Transactional Memory instructions
introduced in Power ISA 2.07.
Signed-off-by: Tom Musta <address@hidden>
---
target-ppc/cpu.h | 4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 068fcb2..3510083 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -2010,6 +2010,8 @@ enum {
PPC2_ISA207S = 0x0000000000008000ULL,
/* Double precision floating point conversion for signed integer 64 */
PPC2_FP_CVT_S64 = 0x0000000000010000ULL,
+ /* Transactional Memory (ISA 2.07, Book II) */
+ PPC2_TM = 0x0000000000020000ULL,
#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
@@ -2017,7 +2019,7 @@ enum {
PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
- PPC2_FP_CVT_S64)
+ PPC2_FP_CVT_S64 | PPC2_TM)
};
/*****************************************************************************/
--
1.7.1
[Qemu-devel] [PATCH 6/9] target-ppc: Introduce tbegin, Tom Musta, 2014/12/18
[Qemu-devel] [PATCH 7/9] target-ppc: Introduce TM Noops, Tom Musta, 2014/12/18