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[Qemu-devel] [PULL 02/13] target-tricore: typo in BOL format
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PULL 02/13] target-tricore: typo in BOL format |
Date: |
Sun, 21 Dec 2014 18:47:38 +0000 |
From: Alex Zuepke <address@hidden>
Signed-off-by: Alex Zuepke <address@hidden>
Reviewed-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
---
target-tricore/translate.c | 4 ++--
target-tricore/tricore-opcodes.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 65abf45..c132223 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -3203,7 +3203,7 @@ static void decode_bol_opc(CPUTriCoreState *env,
DisasContext *ctx, int32_t op1)
tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL);
tcg_temp_free(temp);
break;
- case OPC1_32_BOL_LD_W_LONFOFF:
+ case OPC1_32_BOL_LD_W_LONGOFF:
temp = tcg_temp_new();
tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL);
@@ -3930,7 +3930,7 @@ static void decode_32Bit_opc(CPUTriCoreState *env,
DisasContext *ctx)
break;
/* BOL-format */
case OPC1_32_BOL_LD_A_LONGOFF:
- case OPC1_32_BOL_LD_W_LONFOFF:
+ case OPC1_32_BOL_LD_W_LONGOFF:
case OPC1_32_BOL_LEA_LONGOFF:
case OPC1_32_BOL_ST_W_LONGOFF:
case OPC1_32_BOL_ST_A_LONGOFF:
diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h
index 70ac5ff..7aa6aed 100644
--- a/target-tricore/tricore-opcodes.h
+++ b/target-tricore/tricore-opcodes.h
@@ -447,7 +447,7 @@ enum {
OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR = 0x69,
/* BOL Format */
OPC1_32_BOL_LD_A_LONGOFF = 0x99,
- OPC1_32_BOL_LD_W_LONFOFF = 0x19,
+ OPC1_32_BOL_LD_W_LONGOFF = 0x19,
OPC1_32_BOL_LEA_LONGOFF = 0xd9,
OPC1_32_BOL_ST_W_LONGOFF = 0x59,
OPC1_32_BOL_ST_A_LONGOFF = 0xb5, /* 1.6 only */
--
2.2.1
- [Qemu-devel] [PULL 00/13] tricore patches, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 01/13] target-tricore: fix offset masking in BOL format, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 02/13] target-tricore: typo in BOL format,
Bastian Koppelmann <=
- [Qemu-devel] [PULL 06/13] target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 04/13] target-tricore: pretty-print register dump and show more status registers, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 11/13] target-tricore: Add missing 1.6 insn of BOL opcode format, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 07/13] target-tricore: Add instructions of RR opcode format, that have 0xb as the first opcode, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 05/13] target-tricore: Fix mask handling JNZ.T being 7 bit long, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 10/13] target-tricore: Add instructions of RR opcode format, that have 0x4b as the first opcode, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 12/13] target-tricore: Fix MFCR/MTCR insn and B format offset., Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 03/13] target-tricore: add missing 64-bit MOV in RLC format, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 08/13] target-tricore: Add instructions of RR opcode format, that have 0xf as the first opcode, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 09/13] target-tricore: Add instructions of RR opcode format, that have 0x1 as the first opcode, Bastian Koppelmann, 2014/12/21