[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 03/13] target-tricore: add missing 64-bit MOV in RLC
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PULL 03/13] target-tricore: add missing 64-bit MOV in RLC format |
Date: |
Sun, 21 Dec 2014 18:47:39 +0000 |
From: Alex Zuepke <address@hidden>
Signed-off-by: Alex Zuepke <address@hidden>
Reviewed-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
---
target-tricore/translate.c | 12 ++++++++++++
target-tricore/tricore-opcodes.h | 1 +
2 files changed, 13 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index c132223..e3eeedb 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -3781,6 +3781,17 @@ static void decode_rlc_opc(CPUTriCoreState *env,
DisasContext *ctx,
case OPC1_32_RLC_MOV:
tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
break;
+ case OPC1_32_RLC_MOV_64:
+ if (tricore_feature(env, TRICORE_FEATURE_16)) {
+ if ((r2 & 0x1) != 0) {
+ /* TODO: raise OPD trap */
+ }
+ tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
+ tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15);
+ } else {
+ /* TODO: raise illegal opcode trap */
+ }
+ break;
case OPC1_32_RLC_MOV_U:
const16 = MASK_OP_RLC_CONST16(ctx->opcode);
tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
@@ -4021,6 +4032,7 @@ static void decode_32Bit_opc(CPUTriCoreState *env,
DisasContext *ctx)
case OPC1_32_RLC_ADDIH_A:
case OPC1_32_RLC_MFCR:
case OPC1_32_RLC_MOV:
+ case OPC1_32_RLC_MOV_64:
case OPC1_32_RLC_MOV_U:
case OPC1_32_RLC_MOV_H:
case OPC1_32_RLC_MOVH_A:
diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h
index 7aa6aed..a76a7e4 100644
--- a/target-tricore/tricore-opcodes.h
+++ b/target-tricore/tricore-opcodes.h
@@ -487,6 +487,7 @@ enum {
OPC1_32_RLC_ADDIH_A = 0x11,
OPC1_32_RLC_MFCR = 0x4d,
OPC1_32_RLC_MOV = 0x3b,
+ OPC1_32_RLC_MOV_64 = 0xfb, /* 1.6 only */
OPC1_32_RLC_MOV_U = 0xbb,
OPC1_32_RLC_MOV_H = 0x7b,
OPC1_32_RLC_MOVH_A = 0x91,
--
2.2.1
- [Qemu-devel] [PULL 00/13] tricore patches, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 01/13] target-tricore: fix offset masking in BOL format, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 02/13] target-tricore: typo in BOL format, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 06/13] target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 04/13] target-tricore: pretty-print register dump and show more status registers, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 11/13] target-tricore: Add missing 1.6 insn of BOL opcode format, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 07/13] target-tricore: Add instructions of RR opcode format, that have 0xb as the first opcode, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 05/13] target-tricore: Fix mask handling JNZ.T being 7 bit long, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 10/13] target-tricore: Add instructions of RR opcode format, that have 0x4b as the first opcode, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 12/13] target-tricore: Fix MFCR/MTCR insn and B format offset., Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 03/13] target-tricore: add missing 64-bit MOV in RLC format,
Bastian Koppelmann <=
- [Qemu-devel] [PULL 08/13] target-tricore: Add instructions of RR opcode format, that have 0xf as the first opcode, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 09/13] target-tricore: Add instructions of RR opcode format, that have 0x1 as the first opcode, Bastian Koppelmann, 2014/12/21
- [Qemu-devel] [PULL 13/13] target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as first opcode, Bastian Koppelmann, 2014/12/21
- Re: [Qemu-devel] [PULL 00/13] tricore patches, Peter Maydell, 2014/12/22