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[Qemu-devel] [PATCH v2 7/9] target-arm: Add EL3 and EL2 TCR checking
From: |
Greg Bellows |
Subject: |
[Qemu-devel] [PATCH v2 7/9] target-arm: Add EL3 and EL2 TCR checking |
Date: |
Wed, 22 Apr 2015 12:09:19 -0500 |
Updated get_phys_addr_lpae to check the appropriate TTBCR/TCR depending on the
current EL. Support includes using the different TCR format as well as checks to
insure TTBR1 is not used when in EL2 or EL3.
Signed-off-by: Greg Bellows <address@hidden>
---
target-arm/helper.c | 45 ++++++++++++++++++++++++++++++++-------------
1 file changed, 32 insertions(+), 13 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 69a5891..e7ab5c4 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -5397,21 +5397,34 @@ static int get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
int32_t tbi = 0;
TCR *tcr = regime_tcr(env, mmu_idx);
int ap, ns, xn, pxn;
+ uint32_t el = regime_el(env, mmu_idx);
+ bool ttbr1_valid = true;
/* TODO:
- * This code assumes we're either a 64-bit EL1 or a 32-bit PL1;
- * it doesn't handle the different format TCR for TCR_EL2, TCR_EL3,
- * and VTCR_EL2, or the fact that those regimes don't have a split
- * TTBR0/TTBR1. Attribute and permission bit handling should also
- * be checked when adding support for those page table walks.
+ * This code does not handle the different format TCR for VTCR_EL2.
+ * This code also does not support shareability levels.
+ * Attribute and permission bit handling should also be checked when adding
+ * support for those page table walks.
*/
- if (arm_el_is_aa64(env, regime_el(env, mmu_idx))) {
+ if (arm_el_is_aa64(env, el)) {
va_size = 64;
- if (extract64(address, 55, 1))
- tbi = extract64(tcr->raw_tcr, 38, 1);
- else
- tbi = extract64(tcr->raw_tcr, 37, 1);
+ if (el > 1) {
+ tbi = extract64(tcr->raw_tcr, 20, 1);
+ } else {
+ if (extract64(address, 55, 1)) {
+ tbi = extract64(tcr->raw_tcr, 38, 1);
+ } else {
+ tbi = extract64(tcr->raw_tcr, 37, 1);
+ }
+ }
tbi *= 8;
+
+ /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
+ * invalid.
+ */
+ if (el > 1) {
+ ttbr1_valid = false;
+ }
}
/* Determine whether this address is in the region controlled by
@@ -5432,13 +5445,14 @@ static int get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
if (t0sz && !extract64(address, va_size - t0sz, t0sz - tbi)) {
/* there is a ttbr0 region and we are in it (high bits all zero) */
ttbr_select = 0;
- } else if (t1sz && !extract64(~address, va_size - t1sz, t1sz - tbi)) {
+ } else if (ttbr1_valid && t1sz &&
+ !extract64(~address, va_size - t1sz, t1sz - tbi)) {
/* there is a ttbr1 region and we are in it (high bits all one) */
ttbr_select = 1;
} else if (!t0sz) {
/* ttbr0 region is "everything not in the ttbr1 region" */
ttbr_select = 0;
- } else if (!t1sz) {
+ } else if (!t1sz && ttbr1_valid) {
/* ttbr1 region is "everything not in the ttbr0 region" */
ttbr_select = 1;
} else {
@@ -5467,6 +5481,9 @@ static int get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
granule_sz = 11;
}
} else {
+ /* We should only be here if TTBR1 is valid */
+ assert(ttbr1_valid);
+
ttbr = regime_ttbr(env, mmu_idx, 1);
epd = extract32(tcr->raw_tcr, 23, 1);
tsz = t1sz;
@@ -5485,7 +5502,9 @@ static int get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
*/
if (epd) {
- /* Translation table walk disabled => Translation fault on TLB miss */
+ /* Translation table walk disabled => Translation fault on TLB miss
+ * Note: This is always 0 on 64-bit EL2 and EL3.
+ */
goto do_fault;
}
--
1.8.3.2
- [Qemu-devel] [PATCH v2 0/9] target-arm: EL3 trap support, Greg Bellows, 2015/04/22
- [Qemu-devel] [PATCH v2 2/9] target-arm: Extend helpers to route exceptions, Greg Bellows, 2015/04/22
- [Qemu-devel] [PATCH v2 1/9] target-arm: Add exception target el infrastructure, Greg Bellows, 2015/04/22
- [Qemu-devel] [PATCH v2 3/9] target-arm: Update interrupt handling to use target EL, Greg Bellows, 2015/04/22
- [Qemu-devel] [PATCH v2 4/9] target-arm: Add AArch64 CPTR registers, Greg Bellows, 2015/04/22
- [Qemu-devel] [PATCH v2 6/9] target-arm: Add TTBR regime function and use, Greg Bellows, 2015/04/22
- [Qemu-devel] [PATCH v2 5/9] target-arm: Extend FP checks to use an EL, Greg Bellows, 2015/04/22
- [Qemu-devel] [PATCH v2 7/9] target-arm: Add EL3 and EL2 TCR checking,
Greg Bellows <=
- [Qemu-devel] [PATCH v2 9/9] target-arm: Add WFx instruction trap support, Greg Bellows, 2015/04/22
- Re: [Qemu-devel] [PATCH v2 9/9] target-arm: Add WFx instruction trap support, Edgar E. Iglesias, 2015/04/22
- Re: [Qemu-devel] [PATCH v2 9/9] target-arm: Add WFx instruction trap support, Peter Maydell, 2015/04/23
- Re: [Qemu-devel] [PATCH v2 9/9] target-arm: Add WFx instruction trap support, Edgar E. Iglesias, 2015/04/23
- Re: [Qemu-devel] [PATCH v2 9/9] target-arm: Add WFx instruction trap support, Peter Maydell, 2015/04/23
- Re: [Qemu-devel] [PATCH v2 9/9] target-arm: Add WFx instruction trap support, Edgar E. Iglesias, 2015/04/23
- Re: [Qemu-devel] [PATCH v2 9/9] target-arm: Add WFx instruction trap support, Peter Maydell, 2015/04/23
- Re: [Qemu-devel] [PATCH v2 9/9] target-arm: Add WFx instruction trap support, Edgar E. Iglesias, 2015/04/23
- Re: [Qemu-devel] [PATCH v2 9/9] target-arm: Add WFx instruction trap support, Greg Bellows, 2015/04/23
- Re: [Qemu-devel] [PATCH v2 9/9] target-arm: Add WFx instruction trap support, Peter Maydell, 2015/04/23