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[Qemu-devel] [PATCH 5/7] target-mips: correct MFC0 for CP0.EntryLo in MI
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PATCH 5/7] target-mips: correct MFC0 for CP0.EntryLo in MIPS64 |
Date: |
Tue, 28 Apr 2015 13:41:12 +0100 |
Since PFNX is now supported the bits 31:30 have to be cleared.
Signed-off-by: Leon Alrae <address@hidden>
---
target-mips/translate.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index f95b655..a41fc98 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -5144,10 +5144,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo0));
#if defined(TARGET_MIPS64)
if (ctx->rxi) {
+ /* Move RI/XI fields to bits 31:30 */
TCGv tmp = tcg_temp_new();
- tcg_gen_andi_tl(tmp, arg, (3ull << CP0EnLo_XI));
- tcg_gen_shri_tl(tmp, tmp, 32);
- tcg_gen_or_tl(arg, arg, tmp);
+ tcg_gen_shri_tl(tmp, arg, CP0EnLo_XI);
+ tcg_gen_deposit_tl(arg, arg, tmp, 30, 2);
tcg_temp_free(tmp);
}
#endif
@@ -5199,10 +5199,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo1));
#if defined(TARGET_MIPS64)
if (ctx->rxi) {
+ /* Move RI/XI fields to bits 31:30 */
TCGv tmp = tcg_temp_new();
- tcg_gen_andi_tl(tmp, arg, (3ull << CP0EnLo_XI));
- tcg_gen_shri_tl(tmp, tmp, 32);
- tcg_gen_or_tl(arg, arg, tmp);
+ tcg_gen_shri_tl(tmp, arg, CP0EnLo_XI);
+ tcg_gen_deposit_tl(arg, arg, tmp, 30, 2);
tcg_temp_free(tmp);
}
#endif
[Qemu-devel] [PATCH 7/7] target-mips: enable XPA and LPA features, Leon Alrae, 2015/04/28