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Re: [Qemu-devel] [Consult] About SPRs information
From: |
Chen Gang |
Subject: |
Re: [Qemu-devel] [Consult] About SPRs information |
Date: |
Wed, 29 Apr 2015 21:32:31 +0800 |
User-agent: |
Mozilla/5.0 (Macintosh; Intel Mac OS X 10.10; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 |
On 4/29/15 05:43, Peter Maydell wrote:
> On 28 April 2015 at 22:32, Chen Gang <address@hidden> wrote:
>> The related information for cmpexch instruction:
>>
>> Description
>>
>> Compare the 8-byte contents of the CmpValue SPR with the 8-byte
>> value in memory at the address held in the first source register. If
>> the values are not equal, then no memory operation is performed. If
>> the values are equal, the 8-byte quantity from the second source
>> register is written into memory at the address held in the first
>> source register. In either case, the result of the instruc- tion is
>> the value read from memory. The compare and write to memory are
>> atomic and thus can be used for synchronization purposes. This
>> instruction only operates for addresses aligned to a 8-byte boundary.
>> Unaligned memory access causes an Unaligned Data Reference interrupt.
>
> I suggest you look at how existing CPUs handle this kind of
> atomic operation.
>
OK, thanks.
> I also suggest you stop adding implementations of *new* instructions
> and concentrate on getting a basic set into shape for inclusion.
> The more stuff you keep adding the bigger your patchset is going
> to get and the harder it is going to get to review.
>
For me, current code is not quite much, and really easy enough. At
present I am still going smoothly (the issues are mainly about
understanding new instructions which I shall meet).
I still want to reach "display hello world" successfully (it does not
seem quite difficult to me), then reconstruct current code, and send
patch to upstream.
But sorry, it seems I can not finish it within this month (and I shall
try to finish within next month).
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed